Universal IO data acquisition module circuit

Abstract

The utility model relates to a universal IO data acquisition module circuit, which comprises a signal compatible input module and a main control module, and is characterized in that the signal compatible input module comprises a signal input terminal and a switch management unit; the signal input terminal is provided with a plurality of first trigger ends, a plurality of second trigger ends, a first common reference voltage end and a second common reference voltage end, and the first common reference voltage end is used for being matched with each first trigger end to form a plurality of high-level trigger signal channels. The second common reference voltage end is used for cooperating with each second trigger end to form a plurality of low-level trigger signal channels, and the high-level trigger signal channels and the low-level trigger signal channels are connected with the signal input end of the switch management unit, thereby achieving the unified collection of a plurality of different-level trigger signals. Therefore, simultaneous access and accurate identification of different level input signals are effectively supported, and the limitation that a traditional IO module can only receive similar level signals is solved.

Description

Technical Field

[0001] This application relates to the technical field of a general-purpose I / O data acquisition module, and more particularly to a general-purpose I / O data acquisition module circuit. Background Technology

[0002] Currently, existing general-purpose I / O data acquisition modules still have significant shortcomings in terms of signal input port compatibility. Specifically, existing acquisition circuits generally adopt a coupled structure, with different input channels sharing the same reference voltage as a trigger reference. This results in the ability to acquire signals with the same trigger logic. "Same type of signal" means that all input signals must be triggered in the same direction as the set reference voltage. For example, when the reference voltage is high, only high-level trigger signals can be input. If a low-level trigger signal is input, it will not be properly recognized and may even cause acquisition anomalies, affecting system stability.

[0003] Because existing modules cannot simultaneously accommodate input signals with different trigger directions, they struggle to meet application requirements when faced with mixed scenarios requiring the simultaneous acquisition of both high-level and low-level trigger signals, thus limiting the system's scalability and versatility. If users forcibly connect signals of different level types, it may cause logical conflicts in the internal acquisition circuitry, resulting in false triggers or signal loss, and in severe cases, even leading to module malfunctions. Utility Model Content

[0004] To address the issue that existing IO data acquisition modules cannot simultaneously acquire both high-level and low-level trigger signals, this application provides a general-purpose IO data acquisition module circuit.

[0005] A general-purpose I / O data acquisition module circuit includes a signal-compatible input module and a main control module. The signal-compatible input module includes signal input terminals and a switch management unit. The signal input terminals are respectively provided with multiple first trigger terminals, multiple second trigger terminals, a first common reference voltage terminal that maintains a high potential, and a second common reference voltage terminal that maintains a low potential. The first common reference voltage terminal is used to cooperate with each of the first trigger terminals to form multiple high-level trigger signal channels, and the second common reference voltage terminal is used to cooperate with each of the second trigger terminals to form multiple low-level trigger signal channels. Both the high-level trigger signal channels and the low-level trigger signal channels are connected to the signal input terminal of the switch management unit, and the signal output terminal of the switch management unit is connected to the signal input terminal of the main control module.

[0006] By adopting the above technical solution and setting up a signal compatible input module and a main control module, it is possible to uniformly acquire multiple trigger signals with different levels. By using the first and second common reference voltage terminals in conjunction with the first and second trigger terminals to form high and low level trigger channels, it can effectively support the simultaneous access and accurate identification of input signals with different levels, thus solving the limitation of traditional IO modules that can only receive signals of the same level.

[0007] Preferably, the switch management unit includes a first opto-isolation subunit and a second opto-isolation subunit. The first common reference voltage terminal is connected to the optical signal input terminal of the first opto-isolation subunit, the optical signal output terminal of the first opto-isolation subunit is connected to the first trigger terminal, the electrical signal output terminal of the first opto-isolation subunit is connected to the first signal input terminal of the main control module, the second trigger terminal is connected to the optical signal input terminal of the second opto-isolation subunit, the optical signal output terminal of the second opto-isolation subunit is connected to the second common reference voltage terminal, and the electrical signal output terminal of the second opto-isolation subunit is connected to the second signal input terminal of the main control module.

[0008] By adopting the above technical solution, and by refining the switch management unit into first and second opto-isolated sub-units, it is possible to independently acquire high-level trigger and low-level trigger signals through opto-isolation, thereby avoiding signal interference under different trigger logics and improving the independence of signal processing and the reliability of the system.

[0009] Preferably, the first opto-isolation subunit includes at least one first bidirectional optocoupler. The high-level trigger signal channel is provided with a first resistor and a second resistor. The first common reference voltage terminal is connected to the optical signal input terminal of the first bidirectional optocoupler. The optical signal output terminal of the first bidirectional optocoupler is connected to the first end of the first resistor. The second end of the first resistor is connected to the first trigger terminal. The first common reference voltage terminal is connected to the first end of the second resistor. The second end of the second resistor is connected to the first end of the first resistor. The first resistor and the second resistor form a series current limiting network for current limiting of the first bidirectional optocoupler. The electrical signal output terminal of the first bidirectional optocoupler is connected to the first signal input terminal of the main control module.

[0010] By adopting the above technical solution, by setting a first bidirectional optocoupler on the high-level trigger signal channel and connecting a first resistor and a second resistor in series at its input terminal to form a current limiting structure, the input signal current entering the optocoupler can be stably limited, thereby ensuring the normal operation of the optocoupler and improving the safety and adaptability of the high-level signal channel.

[0011] Preferably, a third resistor is connected between the electrical signal output terminal of the first bidirectional optocoupler and the power supply, and the common node between the third resistor and the electrical signal output terminal of the first bidirectional optocoupler is connected to the first signal input terminal of the main control module.

[0012] By adopting the above technical solution, a pull-up voltage channel can be formed in the output path, thereby maintaining the signal line at a stable high level when the optocoupler is not conducting, effectively preventing signal jitter or misjudgment caused by the input terminal being floating. At the same time, when the optocoupler is conducting, a clear level pull-down action is achieved, enabling the main control module to accurately distinguish the signal state and improve the anti-interference capability of signal recognition and the reliability of level conversion.

[0013] Preferably, the second opto-isolation subunit includes at least one second bidirectional optocoupler. A fourth resistor and a fifth resistor are provided on the low-level trigger signal channel. The second trigger terminal is connected to the first terminal of the fourth resistor. The second terminal of the fourth resistor is connected to the optical signal input terminal of the second bidirectional optocoupler. The optical signal output terminal of the second bidirectional optocoupler is connected to the second common reference voltage terminal. The second terminal of the fourth resistor is connected to the first terminal of the fifth resistor. The second terminal of the fifth resistor is connected to the second common reference voltage terminal. The fourth resistor and the fifth resistor form a series current limiting network for current limiting of the second bidirectional optocoupler. The electrical signal output terminal of the second bidirectional optocoupler is connected to the second signal input terminal of the main control module.

[0014] By adopting the above technical solution, and by setting a second bidirectional optocoupler on the low-level trigger signal channel, and connecting a fourth resistor and a fifth resistor in series to form a current-limiting structure, it is possible to ensure that the input current entering the optocoupler is within a safe range, thereby improving the safety and isolation effect of the low-level trigger signal acquisition and ensuring the reliable operation of the bidirectional optocoupler.

[0015] Preferably, a sixth resistor is connected between the electrical signal output terminal of the second bidirectional optocoupler and the power supply, and the common node between the sixth resistor and the electrical signal output terminal of the second bidirectional optocoupler is connected to the second signal input terminal of the main control module.

[0016] By adopting the above technical solution, a stable high-level effect can be achieved in the signal path, ensuring that the signal is in a high-level state when the optocoupler is not conducting, thereby preventing level fluctuations or misjudgments caused by the signal input terminal being floating. When the optocoupler is conducting, the signal is clearly pulled low, ensuring that the main control module can accurately receive the low-level signal, improving the reliability and anti-interference capability of signal recognition, and guaranteeing the stability of the system under different operating conditions.

[0017] Preferably, the general-purpose IO data acquisition module circuit further includes a WIFI control module, the data communication terminal of which is connected to the data communication terminal of the main control module to realize data transmission operation via WIFI communication.

[0018] By adopting the above technical solution and adding a WIFI control module that communicates with the main control module, data can be transmitted remotely wirelessly, thereby expanding the module's communication capabilities and enabling signal acquisition results to be flexibly uploaded to a remote system or platform, improving communication flexibility and deployment convenience.

[0019] Preferably, the general-purpose IO data acquisition module circuit further includes an EEPROM storage module, and the I2C serial communication data terminal of the EEPROM storage module is connected to the I2C serial communication data terminal of the WIFI control module.

[0020] By adopting the above technical solution, and by introducing an EEPROM storage module and connecting it to the WIFI control module via I²C communication, the control commands issued by the user can be persistently stored locally, thereby supporting the breakpoint resumption and reliable execution of remote control logic, and improving the intelligent management of the module and the execution stability of the control strategy.

[0021] Preferably, the general-purpose IO data acquisition module circuit further includes a power management module. The power management module includes a power chip U1, a power input terminal DC1, and a rectifier diode D16. The power input terminal DC1 is connected to a power source. The power output terminal of the power input terminal DC1 is connected to the positive terminal of the rectifier diode D16, and the negative terminal of the rectifier diode D16 is connected to the power input terminal of the power chip U1. The power chip is used for level conversion and outputs 5V power through the power output terminal of the power chip for power supply.

[0022] By adopting the above technical solution and setting up a power management module including rectifier diodes, power chips and DC input terminals, the external input power can be rectified and level converted to output a stable 5V DC power supply, thereby ensuring the power supply reliability and working stability of the entire IO data acquisition module.

[0023] Preferably, the power management module further includes a step-down chip IC1, the power input terminal of which is connected to the power output terminal of the power chip, and the power output terminal of the step-down chip IC1 outputs 3.3V power for power supply.

[0024] By adopting the above technical solution, and by adding a step-down chip at the output end of the power chip to output 3.3V power, a voltage source compatible with a variety of low-voltage logic circuits can be provided, thereby supporting the normal operation of devices with different operating levels inside the module and improving the module's adaptability to various device structures.

[0025] In summary, this application includes at least one of the following beneficial technical effects:

[0026] This application introduces a structural design with two different trigger level signal channels. It employs a high-level trigger path formed by combining a first common reference voltage terminal with multiple first trigger terminals, and a low-level trigger path formed by combining a second common reference voltage terminal with multiple second trigger terminals. This enables the signal input terminal to simultaneously accept trigger signals of different levels, overcoming the limitation of traditional coupled acquisition circuits that can only process single-trigger type signals. By physically separating the high and low level signal paths and managing them uniformly through a switch management unit before sending them to the main control module, this structure effectively avoids signal coupling interference and trigger logic conflicts. It achieves stable acquisition and highly compatible processing of multi-source heterogeneous signals, improving the application flexibility and system adaptability of the entire IO data acquisition module, and providing a reliable electrical solution for the unified access of different device interfaces in complex industrial environments. Attached Figure Description

[0027] Figure 1 This is a flowchart of a general-purpose I / O data acquisition module circuit according to one embodiment of this application;

[0028] Figure 2 This is a partial circuit structure diagram of the main control module in a general-purpose IO data acquisition module according to an embodiment of this application;

[0029] Figure 3 This is a partial circuit diagram of a signal-compatible input module in a general-purpose I / O data acquisition module according to an embodiment of this application;

[0030] Figure 4 This is a partial circuit structure diagram of the WIFI control module in a general IO data acquisition module according to an embodiment of this application;

[0031] Figure 5 This is a partial circuit structure diagram of the EEPROM storage module in a general-purpose I / O data acquisition module according to an embodiment of this application;

[0032] Figure 6 This is a schematic diagram of a portion of the circuit structure of the power management module in a general-purpose I / O data acquisition module according to an embodiment of this application. Figure 1 ;

[0033] Figure 7This is a schematic diagram of a portion of the circuit structure of the power management module in a general-purpose I / O data acquisition module according to an embodiment of this application. Figure 2 . Detailed Implementation

[0034] The present application will be further described in detail below with reference to the accompanying drawings.

[0035] In one embodiment, such as Figures 1-3 As shown, this application discloses a general-purpose I / O data acquisition module circuit. The general-purpose I / O data acquisition module circuit includes a signal compatible input module and a main control module. The signal compatible input module includes signal input terminals and a switch management unit. The signal input terminals are respectively provided with multiple first trigger terminals, multiple second trigger terminals, a first common reference voltage terminal that maintains a high potential, and a second common reference voltage terminal that maintains a low potential. The first common reference voltage terminal is used to cooperate with each of the first trigger terminals to form multiple high-level trigger signal channels. The second common reference voltage terminal is used to cooperate with each of the second trigger terminals to form multiple low-level trigger signal channels. Both the high-level trigger signal channels and the low-level trigger signal channels are connected to the signal input terminal of the switch management unit. The signal output terminal of the switch management unit is connected to the signal input terminal of the main control module.

[0036] In this embodiment, the signal input terminals are respectively provided with multiple first trigger terminals, multiple second trigger terminals, a first common reference voltage terminal, and a second common reference voltage terminal. The first common reference voltage terminal is maintained at a high potential, and the second common reference voltage terminal is maintained at a low potential. A high-level trigger signal channel is formed between the first trigger terminals and the first common reference voltage terminal. In this channel, when the potential of one of the first trigger terminals is lower than that of the first common reference voltage terminal, a current path is formed, thereby triggering signal acquisition. A low-level trigger signal channel is formed between the second trigger terminals and the second common reference voltage terminal. In this path, when the potential of the second trigger terminal is higher than that of the second common reference voltage terminal, a loop is formed, triggering a valid signal. The aforementioned multiple high-level trigger signal channels and low-level trigger signal channels are independently connected to the signal input terminal of the switch management unit. Physically, they are isolated from the switch management unit through their respective independent input paths, ensuring that the signals do not interfere with or interconnect. Internally, the switch management unit performs photoelectric conversion and signal isolation through devices such as bidirectional optocouplers based on the level changes of the signal input path, outputting a standard logic level signal to the signal input terminal of the main control module. The main control module, as the core processing unit, receives standardized electrical signals from the switch management unit, enabling real-time acquisition and processing of input states from multiple signal channels. Logically, by pairing the first common reference voltage terminal with the first trigger terminal triggered by a high level, and the second common reference voltage terminal with the second trigger terminal triggered by a low level, and connecting them to the switch management unit via independent paths, simultaneous acquisition of different trigger logic signals is achieved, thus constructing a signal acquisition platform with high compatibility and high reliability.

[0037] Furthermore, such as Figure 3 As shown, the switch management unit includes a first opto-isolation subunit and a second opto-isolation subunit. The first common reference voltage terminal is connected to the optical signal input terminal of the first opto-isolation subunit, the optical signal output terminal of the first opto-isolation subunit is connected to the first trigger terminal, the electrical signal output terminal of the first opto-isolation subunit is connected to the first signal input terminal of the main control module, the second trigger terminal is connected to the optical signal input terminal of the second opto-isolation subunit, the optical signal output terminal of the second opto-isolation subunit is connected to the second common reference voltage terminal, and the electrical signal output terminal of the second opto-isolation subunit is connected to the second signal input terminal of the main control module.

[0038] In this embodiment, the switch management unit consists of a first opto-isolation subunit and a second opto-isolation subunit, corresponding to different types of input signal channels. A first common reference voltage terminal, using a high potential as a trigger reference, is directly connected to the optical signal input terminal of the first opto-isolation subunit. This input terminal contains a light-emitting diode structure for sensing current flow. When a potential difference is formed between the first common reference voltage terminal and the first trigger terminal, generating current, the optical signal input terminal is activated. The optical signal response is converted into an electrical signal by the optocoupler mechanism inside the first opto-isolation subunit. Simultaneously, its optical signal output terminal is connected to the first trigger terminal, forming a closed loop in the input path to maintain the continuity of photoelectric action. The converted electrical signal is led out from the electrical signal output terminal of the first opto-isolation subunit and transmitted to the first signal input terminal of the main control module for subsequent data processing and logic recognition. Conversely, the second trigger terminal receives a low-level trigger signal and connects to the optical signal input terminal of the second opto-isolation subunit. Its triggering mechanism is the opposite of that of the first opto-isolation subunit. That is, when the second trigger terminal is at a high potential and the second common reference voltage terminal is at a low potential, the optical signal input terminal generates current due to the potential difference, which also activates the internal light-emitting element to emit an optical signal. This optical signal is converted into an electrical signal output through the optocoupler system of the second opto-isolation subunit. At the same time, the optical signal output terminal of the second opto-isolation subunit is connected to the second common reference voltage terminal, forming a closed circuit to ensure that the excitation conditions are met. Finally, the converted standard electrical signal is sent to the second signal input terminal of the main control module for reading and logical judgment through the electrical signal output terminal. The entire connection logic ensures that the input signals of the two different triggering methods are processed separately through opto-isolation and that the corresponding signal paths are respectively connected to the main control module. This achieves electrical isolation of the input paths and avoids logical conflicts or signal interference caused by differences in triggering conditions, enabling the module to operate stably in a multi-source heterogeneous signal environment.

[0039] Furthermore, such as Figure 3 As shown, the first opto-isolation subunit includes at least one first bidirectional optocoupler. A first resistor and a second resistor are provided on the high-level trigger signal channel. The first common reference voltage terminal is connected to the optical signal input terminal of the first bidirectional optocoupler. The optical signal output terminal of the first bidirectional optocoupler is connected to the first end of the first resistor. The second end of the first resistor is connected to the first trigger terminal. The first common reference voltage terminal is connected to the first end of the second resistor. The second end of the second resistor is connected to the first end of the first resistor. The first resistor and the second resistor form a series current limiting network for current limiting of the first bidirectional optocoupler. The electrical signal output terminal of the first bidirectional optocoupler is connected to the first signal input terminal of the main control module.

[0040] In this embodiment, in the high-level trigger path of the general-purpose IO data acquisition module circuit, the structure of the first opto-isolation subunit includes at least one first bidirectional optocoupler, serving as a core component for signal isolation and conversion. The first common reference voltage terminal is maintained at a high potential, and its electrical connection extends directly to the optical signal input terminal of the first bidirectional optocoupler, providing a driving voltage for the internal light-emitting diode. When a trigger event occurs, the first resistor connected to the optical signal output terminal of the first bidirectional optocoupler begins to conduct. The other end of this resistor is connected to the first trigger terminal, which receives a low-level signal. This forms a current path from the first common reference voltage terminal to the first trigger terminal, thereby triggering the internal light-emitting component of the optocoupler to respond. Simultaneously, the first common reference voltage terminal is also connected to the first end of the first resistor, i.e., the connection point of the optocoupler's optical signal output terminal, through a second resistor. This creates a series current-limiting structure between the first and second resistors, forming current shunting and current control throughout the path, preventing overcurrent damage to the internal components of the optocoupler due to a high input signal voltage. In the above structure, the node between the first and second resistors is located on the optocoupler output path. Its series current-limiting effect precisely controls the current flowing into the optocoupler, ensuring the device operates within its safe operating range. Once triggered, the optocoupler converts the input optical signal into an output electrical signal and stably transmits the conversion result to the first signal input of the main control module through its electrical signal output terminal, enabling the identification, acquisition, and transmission of the high-level trigger signal. The overall path design ensures that, with a high level as a reference, a closed conduction path can be formed when the first trigger terminal uses a low level as a valid input. The series current-limiting structure triggers the optocoupler, simultaneously achieving signal isolation and logic conversion, ultimately completing the standardized data reception and processing at the main control module.

[0041] Furthermore, such as Figure 3 As shown, a third resistor is connected between the electrical signal output terminal of the first bidirectional optocoupler and the power supply. The common node between the third resistor and the electrical signal output terminal of the first bidirectional optocoupler is connected to the first signal input terminal of the main control module.

[0042] In this embodiment, a pull-up voltage channel can be formed in the output path, thereby maintaining the signal line at a stable high level when the optocoupler is not conducting, effectively preventing signal jitter or misjudgment caused by the input terminal being floating. At the same time, when the optocoupler is conducting, a clear level pull-down action is achieved, enabling the main control module to accurately distinguish the signal state and improve the anti-interference capability of signal recognition and the reliability of level conversion.

[0043] Furthermore, such as Figure 3As shown, the second opto-isolation subunit includes at least one second bidirectional optocoupler. A fourth resistor and a fifth resistor are provided on the low-level trigger signal channel. The second trigger terminal is connected to the first terminal of the fourth resistor. The second terminal of the fourth resistor is connected to the optical signal input terminal of the second bidirectional optocoupler. The optical signal output terminal of the second bidirectional optocoupler is connected to the second common reference voltage terminal. The second terminal of the fourth resistor is connected to the first terminal of the fifth resistor. The second terminal of the fifth resistor is connected to the second common reference voltage terminal. The fourth resistor and the fifth resistor form a series current limiting network for current limiting of the second bidirectional optocoupler. The electrical signal output terminal of the second bidirectional optocoupler is connected to the second signal input terminal of the main control module.

[0044] In this embodiment, the second opto-isolation subunit of the general-purpose I / O data acquisition module circuit contains at least one second bidirectional optocoupler, which is used to realize the isolated acquisition function of low-level trigger signals. The second trigger terminal serves as a signal access point and is directly connected to the first terminal of the fourth resistor, used to input a high-level signal when the trigger condition is met. The second terminal of the fourth resistor is connected to the optical signal input terminal of the second bidirectional optocoupler. This input terminal is equipped with an internal light-emitting device, which can excite the optical signal output when current flows through it, realizing the response of the input signal. In order to control the current flowing from the second trigger terminal to the optocoupler, the fourth resistor and the fifth resistor form a series current limiting network. Specifically, the second terminal of the fourth resistor is connected not only to the optical signal input terminal but also to the first terminal of the fifth resistor, forming an intermediate current limiting node. The second terminal of the fifth resistor is connected to the second common reference voltage terminal, which is in a low potential state. The above connection structure forms a stable current path, that is, when the second trigger terminal is at a high potential and the second common reference voltage terminal is at a low potential, the current enters the optical signal input terminal after being connected in series through the fourth resistor and the fifth resistor, driving the light-emitting device of the optocoupler to work. The optical signal output terminal corresponding to the light-emitting output is connected to the second common reference voltage terminal to ensure loop closure and complete optical signal transmission. Simultaneously, after the second bidirectional optocoupler completes photoelectric conversion, its electrical signal output terminal transmits the generated standard logic level signal to the second signal input terminal of the main control module, achieving accurate acquisition of low-level trigger signals. This path, through a combination of resistor voltage divider and opto-isolation, ensures stable and controlled input signal current while achieving logical standardization and processing isolation of the input signal, effectively improving the system's ability to identify different logic inputs and its operational stability.

[0045] Furthermore, such as Figure 3 As shown, a sixth resistor is connected between the electrical signal output terminal of the second bidirectional optocoupler and the power supply. The common node between the sixth resistor and the electrical signal output terminal of the second bidirectional optocoupler is connected to the second signal input terminal of the main control module.

[0046] In this embodiment, a stable high-level effect can be achieved in the signal path, ensuring that the signal is in a high-level state when the optocoupler is not conducting, thereby preventing level fluctuations or misjudgments caused by the signal input terminal being floating. When the optocoupler is conducting, the signal is clearly pulled low, ensuring that the main control module can accurately receive the low-level signal, improving the reliability and anti-interference capability of signal recognition, and ensuring the stability of the system under different operating states.

[0047] Furthermore, such as Figure 4 As shown, the general-purpose IO data acquisition module circuit also includes a WIFI control module. The data communication terminal of the WIFI control module is connected to the data communication terminal of the main control module to realize data transmission operation in WIFI communication mode.

[0048] In this embodiment, by adding a WIFI control module and connecting it to the main control module for data communication, data can be transmitted remotely via wireless means, thereby expanding the module's communication capabilities and enabling signal acquisition results to be flexibly uploaded to a remote system or platform, improving communication flexibility and deployment convenience.

[0049] Furthermore, such as Figure 5 As shown, the general-purpose IO data acquisition module circuit also includes an EEPROM storage module, and the I2C serial communication data terminal of the EEPROM storage module is connected to the I2C serial communication data terminal of the WIFI control module.

[0050] In this embodiment, the EEPROM storage module, as a non-volatile storage unit, is used to retain user-issued configuration information and control commands even when power is off. Its communication method uses the I2C serial port protocol for bidirectional data exchange. The I2C serial communication data terminal of this module serves as a logical interface and is directly connected to the I2C serial communication data terminal of the WIFI control module, forming a master-slave communication structure. In the data link, the WIFI control module acts as the master device, possessing the proactive ability to send commands and request data, while the EEPROM storage module acts as a slave device, responding to master requests and performing data read and write operations. When a user remotely sends control parameters or configuration information via a network platform, the WIFI control module receives the data and transmits it to the communication port of the EEPROM storage module through its I2C serial communication data terminal, completing the writing of the data content. Simultaneously, during system operation, if it is necessary to read previously saved data from the EEPROM for system recovery or state initialization, the WIFI control module can also send a read request to the EEPROM through the same I2C serial data link, which will then feed back the stored content to the main control module. This achieves persistent module operation logic, breakpoint resumption control, and remote configuration functions. This structure effectively integrates storage and wireless communication functions, establishing a highly reliable, low-power data buffer and synchronization mechanism, which helps improve the overall intelligence level and scenario adaptability of the module.

[0051] Furthermore, such as Figure 6 As shown, the general-purpose IO data acquisition module circuit also includes a power management module. The power management module includes a power chip U1, a power input terminal DC1, and a rectifier diode D16. The power input terminal DC1 is connected to a power source. The power output terminal of the power input terminal DC1 is connected to the positive terminal of the rectifier diode D16, and the negative terminal of the rectifier diode D16 is connected to the power input terminal of the power chip U1. The power chip is used for level conversion and outputs 5V power through the power output terminal of the power chip for power supply.

[0052] Furthermore, such as Figure 7 As shown, the power management module also includes a step-down chip IC1. The power input terminal of the step-down chip IC1 is connected to the power output terminal of the power chip, and the power output terminal of the step-down chip IC1 outputs 3.3V power for power supply.

[0053] In this embodiment, the power management module is responsible for providing a stable operating voltage for the entire system. Its internal structure consists of a power chip U1, a power input terminal DC1, a rectifier diode D16, and a buck chip IC1, forming a complete multi-stage voltage regulation and distribution chain. The power input terminal DC1 serves as an external power access point, with one end directly connected to an external power supply device to receive input DC power or DC voltage rectified by an adapter. This input power is first transmitted to the power output terminal of the power input terminal DC1. The power output terminal of the power input terminal DC1 is connected to the positive terminal of the rectifier diode D16 via a wire. The function of the rectifier diode D16 is to prevent reverse connection of the power supply. Its negative terminal establishes an electrical connection with the power input terminal of the power chip U1, ensuring that the voltage flowing through the power chip U1 is in the correct direction and providing a certain degree of surge protection. The main function of the power chip U1 is to stabilize and regulate the input voltage and perform level conversion. After internal buck-boost and filtering processing, it provides a stable 5V DC voltage through its power output terminal for powering subsequent modules. To further meet the power supply requirements of some low-voltage logic devices, the power management module also includes a buck converter IC1. The power input of IC1 is directly connected to the power output of power chip U1, meaning it receives a 5V regulated power supply from U1 as its input. Internally, IC1 uses a buck conversion mechanism to generate a 3.3V output for devices operating at 3.3V, such as the Wi-Fi module and EEPROM storage module. IC1's power output distributes power to all 3.3V operating units in the circuit, achieving precise voltage adaptation for modules operating at different voltages and preventing device malfunctions due to voltage mismatch. This structure, through two-stage voltage conversion and a reasonable power path layout, ensures overall power supply stability while providing highly compatible, multi-level stable power support for different modules, significantly improving the safety and adaptability of the module system.

[0054] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A universal IO data acquisition module circuit, characterized in that, The general-purpose I / O data acquisition module circuit includes a signal-compatible input module and a main control module. The signal-compatible input module includes signal input terminals and a switch management unit. The signal input terminals are respectively provided with multiple first trigger terminals, multiple second trigger terminals, a first common reference voltage terminal that maintains a high potential, and a second common reference voltage terminal that maintains a low potential. The first common reference voltage terminal is used to cooperate with each of the first trigger terminals to form multiple high-level trigger signal channels, and the second common reference voltage terminal is used to cooperate with each of the second trigger terminals to form multiple low-level trigger signal channels. Both the high-level trigger signal channels and the low-level trigger signal channels are connected to the signal input terminal of the switch management unit, and the signal output terminal of the switch management unit is connected to the signal input terminal of the main control module.

2. The universal IO data acquisition module circuit according to claim 1, wherein, The switch management unit includes a first opto-isolation subunit and a second opto-isolation subunit. The first common reference voltage terminal is connected to the optical signal input terminal of the first opto-isolation subunit, the optical signal output terminal of the first opto-isolation subunit is connected to the first trigger terminal, the electrical signal output terminal of the first opto-isolation subunit is connected to the first signal input terminal of the main control module, the second trigger terminal is connected to the optical signal input terminal of the second opto-isolation subunit, the optical signal output terminal of the second opto-isolation subunit is connected to the second common reference voltage terminal, and the electrical signal output terminal of the second opto-isolation subunit is connected to the second signal input terminal of the main control module.

3. The universal IO data acquisition module circuit of claim 2, wherein, The first opto-isolation subunit includes at least one first bidirectional optocoupler. A first resistor and a second resistor are provided on the high-level trigger signal channel. The first common reference voltage terminal is connected to the optical signal input terminal of the first bidirectional optocoupler. The optical signal output terminal of the first bidirectional optocoupler is connected to the first end of the first resistor. The second end of the first resistor is connected to the first trigger terminal. The first common reference voltage terminal is connected to the first end of the second resistor. The second end of the second resistor is connected to the first end of the first resistor. The first resistor and the second resistor form a series current limiting network for current limiting of the first bidirectional optocoupler. The electrical signal output terminal of the first bidirectional optocoupler is connected to the first signal input terminal of the main control module.

4. The universal IO data acquisition module circuit of claim 3, wherein, A third resistor is connected between the electrical signal output terminal of the first bidirectional optocoupler and the power supply. The common node between the third resistor and the electrical signal output terminal of the first bidirectional optocoupler is connected to the first signal input terminal of the main control module.

5. The universal IO data acquisition module circuit of claim 2, wherein, The second opto-isolation subunit includes at least one second bidirectional optocoupler. A fourth resistor and a fifth resistor are provided on the low-level trigger signal channel. The second trigger terminal is connected to the first terminal of the fourth resistor. The second terminal of the fourth resistor is connected to the optical signal input terminal of the second bidirectional optocoupler. The optical signal output terminal of the second bidirectional optocoupler is connected to the second common reference voltage terminal. The second terminal of the fourth resistor is connected to the first terminal of the fifth resistor. The second terminal of the fifth resistor is connected to the second common reference voltage terminal. The fourth resistor and the fifth resistor form a series current limiting network for current limiting of the second bidirectional optocoupler. The electrical signal output terminal of the second bidirectional optocoupler is connected to the second signal input terminal of the main control module.

6. The universal IO data acquisition module circuit of claim 5, wherein, A sixth resistor is connected between the electrical signal output terminal of the second bidirectional optocoupler and the power supply. The common node between the sixth resistor and the electrical signal output terminal of the second bidirectional optocoupler is connected to the second signal input terminal of the main control module.

7. The universal IO data acquisition module circuit of claim 1, wherein, The general-purpose IO data acquisition module circuit also includes a WIFI control module. The data communication terminal of the WIFI control module is connected to the data communication terminal of the main control module to realize data transmission operation in WIFI communication mode.

8. The universal IO data acquisition module circuit of claim 7, wherein, The general-purpose IO data acquisition module circuit also includes an EEPROM storage module, and the I2C serial communication data terminal of the EEPROM storage module is connected to the I2C serial communication data terminal of the WIFI control module.

9. The universal IO data acquisition module circuit of claim 1, wherein, The general-purpose I / O data acquisition module circuit also includes a power management module. The power management module includes a power chip U1, a power input terminal DC1, and a rectifier diode D16. The power input terminal DC1 is connected to a power source. The power output terminal of the power input terminal DC1 is connected to the positive terminal of the rectifier diode D16, and the negative terminal of the rectifier diode D16 is connected to the power input terminal of the power chip U1. The power chip is used for level conversion and outputs 5V power through the power output terminal of the power chip for power supply.

10. The universal IO data acquisition module circuit of claim 9, wherein, The power management module also includes a step-down chip IC1, the power input terminal of which is connected to the power output terminal of the power chip, and the power output terminal of the step-down chip IC1 outputs 3.3V power for power supply.

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