Integrated circuit

Abstract

An integrated circuit is provided and includes: a header circuit coupled to a first voltage terminal, providing a first supply voltage and configured to provide a second supply voltage at a second voltage terminal; a receiver / transmitter circuit coupled between the second voltage terminal and a third voltage terminal and providing a third supply voltage less than the second supply voltage; and an electrostatic discharge (ESD) protection circuit coupled to a pad and the receiver / transmitter circuit and further coupled between the first voltage terminal and the third voltage terminal.

Description

Technical Field

[0001] One embodiment disclosed herein relates to an integrated circuit, and more particularly to an integrated circuit having an electrostatic discharge current structure for discharging an integrated circuit. Background Technology

[0002] The recent trend of miniaturizing integrated circuits (ICs) has resulted in smaller, more power-efficient devices capable of operating at higher speeds. Minimization processes have also introduced more stringent design and manufacturing specifications and reliability challenges. Specifically, there are concerns regarding the performance and regional efficiency of input and output devices within IC devices. Utility Model Content

[0003] One embodiment of this disclosure provides an integrated circuit. The integrated circuit includes: a header circuit coupled to a first voltage terminal, providing a first power supply voltage and for providing a second power supply voltage at a second voltage terminal; a receiver / transmitter circuit coupled between the second voltage terminal and a third voltage terminal, providing a third power supply voltage lower than the second power supply voltage; and an electrostatic discharge (ESD) protection circuit coupled to a pad and the receiver / transmitter circuit and further coupled between the first voltage terminal and the third voltage terminal.

[0004] Another embodiment of this disclosure provides an integrated circuit. The integrated circuit is provided and includes: a receiver / transmitter circuit coupled between a first voltage terminal and a second voltage terminal and including a first transistor having a first terminal coupled to the first voltage terminal and a second terminal coupled to a pad; and an electrostatic discharge protection circuit including a second transistor coupled to the receiver / transmitter circuit at the pad and further coupled to a third voltage terminal different from the second voltage terminal. The first transistor and the second transistor have the same conduction type.

[0005] In another embodiment of this disclosure, an integrated circuit is provided. The integrated circuit includes a receiver / transmitter circuit, an electrostatic discharge (ESD) protection circuit, and a power clamping circuit. The receiver / transmitter circuit is coupled between a first voltage terminal and a second voltage terminal. The ESD protection circuit is coupled between the second voltage terminal and a third voltage terminal. The third voltage terminal is different from the first and second voltage terminals. The receiver / transmitter circuit and the ESD protection circuit are coupled to a pad. The power clamping circuit is coupled between the second and third voltage terminals. The ESD protection circuit discharges a first ESD current from the pad to the third voltage terminal. The ESD protection circuit and the power clamping circuit discharge a second ESD current from the pad through the third voltage terminal to the second voltage terminal. Attached Figure Description

[0006] This disclosure presents an embodiment of the form in conjunction with the accompanying documents. Figure 1 The best way to understand this text is by referring to the detailed description below. Please note that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 This is a schematic diagram of an IC device 100 according to some embodiments;

[0008] Figure 2 According to some embodiments, corresponding to Figure 1 A schematic diagram of part of the input / output circuit;

[0009] Figure 3 This is a schematic diagram of the layout of a portion of an integrated circuit according to some embodiments;

[0010] Figure 4A This is a schematic diagram of the layout of a portion of an integrated circuit according to some embodiments;

[0011] Figure 4B Depicting according to some embodiments Figure 4A A cross-sectional view of the integrated circuit obtained along line AA';

[0012] Figure 5 This is a schematic diagram of the layout of a portion of an integrated circuit according to some embodiments;

[0013] Figure 6A This is a schematic diagram of the layout of a portion of an integrated circuit according to some embodiments;

[0014] Figure 6B Depicting according to some embodiments Figure 6A A cross-sectional view of the integrated circuit obtained along line BB';

[0015] Figure 6C Depicting according to some embodiments Figure 6A A cross-sectional view of the integrated circuit obtained along line CC';

[0016] Figure 7 This is a schematic diagram of the layout of a portion of an integrated circuit according to some embodiments;

[0017] Figure 8 According to some embodiments Figure 7 A schematic diagram of the layout of a portion of an integrated circuit;

[0018] Figure 9A and Figure 9B According to some embodiments, corresponding to Figure 1 and Figure 7 A schematic diagram of an antenna effect protection circuit;

[0019] Figure 10 This is a flowchart of a method 1000 for manufacturing an integrated circuit according to some embodiments;

[0020] Figure 11 This is a block diagram of a system for designing integrated circuit layout designs according to some embodiments of this disclosure;

[0021] Figure 12 This is a block diagram of an integrated circuit manufacturing system according to some embodiments, and an integrated circuit manufacturing process associated with the integrated circuit manufacturing system.

[0022] [Symbol Explanation]

[0023] 10: Connecting pad

[0024] 11: Electrostatic Discharge (ESD) Protection Circuit

[0025] 12: Head Circuit

[0026] 13: Receiver / Transmitter Circuit

[0027] 15: Capacitor Unit

[0028] 16: Power clamping circuit

[0029] 30: Integrated Circuits

[0030] 40: Integrated Circuits

[0031] 50: Integrated Circuits

[0032] 60: Integrated Circuits

[0033] 70: Integrated Circuits

[0034] 100: IC device

[0035] 101: Active Region

[0036] 102: Active Region

[0037] 201-205: Conductive Section

[0038] 209: Conductive section

[0039] 301: Gate structure

[0040] 302: Gate structure

[0041] 303: Gate structure

[0042] 308: Gate structure

[0043] 401~409: Conductive wiring

[0044] 501~502: Conductive rails

[0045] 507: Conductive rails

[0046] 601: Conductive trace

[0047] 608: Conductive wiring

[0048] 900: Antenna effect protection circuit

[0049] 901: Transistor

[0050] 902: Transistor

[0051] 931: Gate region

[0052] 932: Gate region

[0053] 1000: Methods for manufacturing integrated circuits

[0054] 1100: Electronic Design Automation (EDA) System

[0055] 1110: I / O Interface

[0056] 1120: Hardware processor

[0057] 1130: Network Interface

[0058] 1140: Network

[0059] 1150: Bus

[0060] 1160: Non-transitory computer-readable storage media

[0061] 1161: Computer program code (instruction)

[0062] 1162: Standard Component Library

[0063] 1163: User Interface (UI)

[0064] 1170: Manufacturing equipment

[0065] 1200: IC Manufacturing System

[0066] 1210: Design Factory

[0067] 1211: IC Design Layout Diagram

[0068] 1220: Photomask Factory

[0069] 1221: Data Preparation

[0070] 1222: Photomask Manufacturing

[0071] 1223: Light Mask

[0072] 1230: IC manufacturer / factory

[0073] 1231: Wafer Manufacturing

[0074] 1232: Wafer

[0075] 1240: IC device

[0076] ANT: Antenna effect protection circuit

[0077] C304: Active Region Edge (CPODE)

[0078] D1: First chip

[0079] D2: Second chip

[0080] DDI: Chip-to-chip interconnect

[0081] EC: Electrostatic Discharge (ESD) Protection Circuit

[0082] FC: Representative Functional Circuit

[0083] I: Connector (or foot)

[0084] I_ND: Positive electrostatic discharge (ESD) current

[0085] I_NS: Positive electrostatic discharge (ESD) current

[0086] I_PD: Electrostatic discharge (ESD) current

[0087] I_PS: Electrostatic discharge (ESD) current

[0088] IE: Input enable signal

[0089] IOC: Representative I / O circuit

[0090] MN1: N-type transistor

[0091] MN2: N-type transistor

[0092] MN71: N-type transistor

[0093] MP1_2: Transistor

[0094] MP1_3: P-type transistor

[0095] MP1: P-type transistor

[0096] MP2: P-type transistor

[0097] MP2_1: P-type transistor

[0098] MP7_1: P-type transistor

[0099] n1: Voltage terminal

[0100] n2: Voltage terminal

[0101] n3: Voltage terminal

[0102] NW: N-type well

[0103] N+: N-type doped region

[0104] OE: Output enable signal

[0105] P+: P-type doped region

[0106] Psub: Substrate

[0107] RX: Receiver

[0108] S1001~S1002: Operation

[0109] TVDD: Actual power supply voltage VDD

[0110] TX: Transmitter

[0111] VD1: Through hole

[0112] VD2: Through hole

[0113] VD3: Through hole

[0114] VDR: Conductive structure

[0115] VDR8: Conductive structure

[0116] VG1: Through hole

[0117] VG3: Through Hole

[0118] VIA0_1: Through hole

[0119] VIA0_2: Through hole

[0120] VIA0_8: Through hole

[0121] VIA1_1: Through hole

[0122] VIA1_2: Through-hole

[0123] VIA1_8: Through-hole

[0124] VSS: Power supply voltage

[0125] VDD: Power supply voltage Detailed Implementation

[0126] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify one embodiment of this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of an embodiment of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0127] The terms used in this specification generally have their ordinary meaning in the art and in the specific context in which each term is used. Examples in this specification, including instances of any term discussed herein, are illustrative only and are not intended to limit the scope and meaning of any embodiment of this disclosure or any of the illustrative terms. Similarly, this disclosure is not limited to the various embodiments given in this specification.

[0128] Although the terms “first,” “second,” etc., are used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the embodiments. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0129] As used herein, the terms “comprising,” “including,” “having,” “containing,” “involving,” and the like should be understood as open-ended, meaning including but not limited to.

[0130] As used herein, “approximately,” “about,” “roughly,” or “substantially” should generally refer to any approximation or range of a given value, which varies depending on the various techniques to which the value is concerned, and whose range should be understood by the broadest understanding of those skilled in the art regarding an embodiment of this disclosure, so as to cover all similar modifications and similar structures. In some embodiments, it should generally mean within 20%, preferably within 10%, and more preferably within 5% of a given value or range. The quantities given herein are approximations, thus meaning that the terms “approximately,” “about,” “roughly,” or “substantially” may be inferred without explicit statement, or mean other approximations.

[0131] See now Figure 1 . Figure 1 This is a schematic block diagram of an IC device 100 according to some embodiments. The IC device 100 includes a first wafer D1 and a second wafer D2 electrically and / or physically connected to each other. In some embodiments, the first wafer D1 and the second wafer D2 are stacked on top of each other and are physically bonded and electrically coupled to each other in a 3D IC. In some embodiments, the first wafer D1 and the second wafer D2 are disposed side-by-side on another substrate or wafer (not shown) and are physically bonded to and electrically coupled to each other via the other substrate or wafer. In some embodiments, the IC device 100 includes two or more wafers electrically and / or physically coupled to each other. In some embodiments, the IC device 100 has one wafer, such as the first wafer D1; while another wafer, such as the second wafer D2, is omitted. Figure 1 In the example configuration, the second chip D2 is similar to the configuration of the first chip D1. The first chip D1 is described in detail herein, while the detailed description of the second chip D2 is omitted.

[0132] The first chip D1 includes one or more functional circuits and one or more input / output (I / O) circuits electrically coupled to the one or more functional circuits. Figure 1 The diagram shows a representative functional circuit FC and a representative I / O circuit IOC of the first chip D1.

[0133] The functional circuit FC is used to perform the desired function of the IC device 100, such as data processing or data storage. Examples of one or more circuits, logic, or units included in the functional circuit FC include, but are not limited to, AND, OR, NAND, NOR, XOR, INV, OR-AND-Invert (OAI), MUX, flip-flops, buffers, latches, delays, clocks, memory, or the like. The circuits, logic, or units included in the functional circuit FC include functional transistors or core transistors, which are protected from antenna effects during the manufacture of the IC device 100. Examples of transistors in the functional circuit FC and other circuits described herein include, but are not limited to, semiconductor field-effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, P-channel metal-oxide semiconductor (PMOS), N-channel metal-oxide semiconductor (NMOS), bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, P-channel and / or N-channel field-effect transistors (PFETs / NFETs), FinFETs, planar MOS transistors with boosted source / drain, nanosheet FETs, nanowire FETs, or the like.

[0134] The I / O circuit IOC is electrically coupled to the functional circuit FC, and is configured as an interface between the functional circuit FC on the first chip D1 and external circuits outside the first chip D1. Figure 1In the example configuration, the I / O circuit IOC includes a receiver RX (also referred to as the "input circuit"), a transmitter TX (also referred to as the "output circuit"), an electrostatic discharge (ESD) protection circuit, and an antenna effect protection circuit ANT, all of which are electrically coupled to the pads or pins I of the I / O pins. In some embodiments, the first chip D1 includes additional antenna effect protection circuitry external to the I / O circuit IOC, which is also electrically coupled to pin I.

[0135] The receiver RX is used to send a signal on pin 1 to the functional circuit FC. The receiver RX is used to receive the input enable signal IE. The receiver RX is enabled to send a signal on pin 1 to the functional circuit FC in response to the logic state of the input enable signal IE, and is disabled in response to a different logic state of the input enable signal IE, thus not sending a signal on pin 1 to the functional circuit FC. The transmitter TX is used to send a signal output from the functional circuit FC to pin 1. The transmitter TX is used to receive the output enable signal OE. The transmitter TX is enabled to send a signal output from the functional circuit FC to pin 1 in response to the logic state of the output enable signal OE, and is disabled in response to a different logic state of the output enable signal OE, thus not sending a signal output from the functional circuit FC to pin 1. Examples of signals input from or output from pin 1 to pin 1 include, but are not limited to, data, power, clock, control, or the like. Examples of one or more of the circuits in at least one of the receiver TX or transmitter TX include, but are not limited to, buffers, latches, level shifters, or the like.

[0136] The ESD protection circuit EC is used to protect other circuits, including the functional circuit FC, from ESD events that occur during the operation or disposal of the first chip D1 or IC device 100. These other circuits are electrically coupled to pin I. In some embodiments, the transistors in the ESD protection circuit EC are larger than and / or have a configuration different from the functional transistors or core transistors of the functional circuit FC to be able to hold and handle the high voltages and / or currents of ESD events.

[0137] The antenna effect protection circuit ANT is located within the I / O circuit IOC. The antenna effect protection circuit ANT protects the transistors of the functional circuit FC from damage caused by antenna effects attributable to the first wafer D1 or IC device 100 during manufacturing. For example, the transistors of the functional circuit FC having gate electrodes electrically coupled to pin I by one or more conductive patterns and / or vias are protected from antenna effects by the antenna effect protection circuit ANT. In some embodiments, the transistors in the antenna effect protection circuit ANT have the same size and / or configuration as the transistors in the functional circuit FC. In at least one embodiment, the transistors in the antenna effect protection circuit ANT are equivalent to the transistors in the functional circuit FC. The transistors in the antenna effect protection circuit ANT are smaller than the transistors in the ESD protection circuit EC and / or have a different configuration than the transistors in the ESD protection circuit EC.

[0138] In at least one embodiment, the layout of the I / O circuit IOC, including the antenna effect protection circuit ANT, is stored as a cell or module in a standard component library (also referred to as a "cell library"). During the design phase, the APR tool, as part of the I / O circuit IOC, places the antenna effect protection circuit ANT in the layout of the first chip D1. The APR tool performs little or no other routing for the antenna effect protection circuit ANT. The APR tool then performs routing individually for the placed one or more antenna elements. In some embodiments, the antenna effect protection circuit ANT includes one or more antenna elements individually placed and / or routed by the APR tool. In some embodiments, one or more antenna elements or the antenna effect protection circuit is included in the functional circuit FC to provide transistor antenna effect protection for transistors that are too far from pin I and / or not electrically coupled to pin I.

[0139] The first wafer D1 is electrically coupled to the second wafer D2 at one or more wafer-to-wafer interconnects. Figure 1 In the diagram, a representative chip-to-chip interconnect (DDI) is shown, electrically coupled to pin 1 of a first chip D1 and the corresponding pin 1 of a second chip D2. Therefore, pin 1 of the first chip D1 is electrically coupled to the corresponding pin 1 of the second chip D2 via the chip-to-chip interconnect (DDI). In some embodiments, the chip-to-chip interconnect (DDI) is a pad in one or more chips of the IC device 100.

[0140] See now Figure 2 . Figure 2 According to some embodiments, corresponding to Figure 1 A schematic diagram of the input / output circuit IOC section.

[0141] For illustration purposes, the I / O circuit IOC includes an electrostatic discharge (ESD) protection circuit 11, a header circuit 12, a receiver / transmitter circuit 13 coupled to the functional circuit FC, a capacitor unit 15, and a power clamping circuit 16. In some embodiments, the ESD protection circuit 11 is configured to, for example... Figure 1 The ESD protection circuit EC configuration. Receiver / transmitter circuit 13 regarding, for example... Figure 1 The receiver RX and transmitter TX are configured.

[0142] like Figure 2 As illustrated, the ESD protection circuit 11 and the power clamping circuit 16 are coupled in parallel between voltage terminals n1 and n2. The header circuit 12 is coupled to voltage terminal n1 and another voltage terminal n3. The receiver / transmitter circuit 13 and the capacitor unit 15 are coupled in parallel between voltage terminals n2 and n3. In other words, in some embodiments, the capacitor unit 15 is disconnected from the terminal of transistor MP1.

[0143] In some embodiments, voltage terminal n1 is used to receive the actual power supply voltage VDD (“TVDD” herein). In some embodiments, the power supply voltage TVDD is determined by… Figure 1 The power supply voltage TVDD is generated by an external power source outside the IC device 100. In some embodiments, the power supply voltage TVDD is generated by an internal power source included in the IC device 100.

[0144] The voltage terminal n2 is used to couple to the power supply voltage VSS. In some embodiments, the power supply voltage is ground, or a voltage level having a voltage level lower than the power supply voltage TVDD.

[0145] In some embodiments, the head circuit 12 is used to receive the power supply voltage TVDD from the voltage terminal n1 and further provide the power supply voltage VDD to the voltage terminal n3. In some embodiments, the power supply voltage VDD is referred to as a virtual power supply. In some embodiments, the power supply voltage TVDD is different from the power supply voltage VDD. For example, the power supply voltage is 0.3 to 0.5 volts greater than the power supply voltage VDD. In some embodiments, the power supply voltage TVDD is the same as the power supply voltage VDD.

[0146] Specifically, the ESD protection circuit 11 includes a P-type transistor MP1 and an N-type transistor MN1. Transistor MP1 has a drain / source terminal coupled to pad 10, and a gate terminal and a source / drain terminal coupled to voltage terminal n1. Transistor MN1 has a drain / source terminal coupled to the source / drain terminal of transistor MP1 and the receiver / transmitter circuit 13 at pad 10, and a gate terminal and a source / drain terminal coupled to voltage terminal n2.

[0147] The receiver / transmitter circuit 13 includes a P-type transistor MP2 and an N-type transistor MN2. Transistor MP2 has a source / drain terminal coupled to voltage terminal n3 and a drain / source terminal coupled to pad 10. Transistor MN2 has a gate terminal coupled to the gate terminal of transistor MP2, a source / drain terminal coupled to voltage terminal n2, and a drain / source terminal coupled to pad 10 and ESD protection circuit 11. The gate terminals of transistors MP2 and MN2 are coupled to functional circuit FC.

[0148] In some embodiments, the body terminals of transistors MP1 to MP2 are coupled to voltage terminal n1 to receive power supply voltage TVDD. In other words, the body terminal of transistor MP2 in receiver / transmitter circuit 13 is coupled to the gate and source / drain terminals of transistor MP1. The body terminals of transistors MN1 to MN2 are coupled to voltage terminal n2 to receive power supply voltage VSS.

[0149] According to some embodiments, the ESD protection circuit 11 is used to discharge the ESD current induced by the charge introduced into the pad 10 during an ESD event.

[0150] For example, during a positive ESD event to VDD (hereinafter referred to as "PD mode") or a positive electrostatic discharge event, transistor MP1 discharges the positive electrostatic charge introduced at pad 10 as an ESD current I_PD, which flows from pad 10 to voltage terminal n1.

[0151] In another embodiment, during the positive to VSS (hereinafter referred to as "PS mode") of ESD, the transistor MP1 and the power clamping circuit 16 in the ESD protection circuit 11 discharge the positive electrostatic charge introduced at the pad 10 as an ESD current I_PS, which flows from the pad 10 to the voltage terminal n2.

[0152] In another embodiment, during a negative to VSS (hereinafter referred to as "NS mode") or positive electrostatic discharge event of ESD, transistor MN1 of ESD protection circuit 11 discharges negative electrostatic charge from pad 10 to voltage terminal n2, which is referred to as positive ESD current I_NS flowing to pad 10.

[0153] In some embodiments, during a negative to VDD (hereinafter referred to as "ND mode") or negative electrostatic discharge event of ESD, the transistor MN1 of the ESD protection circuit 11 and the power clamping circuit 16 discharge the negative electrostatic charge from the pad 10 to the voltage terminal n1, which is referred to as the positive ESD current I_ND flowing to the pad 10.

[0154] While some chip-to-chip interconnect input / output circuitry methods optimize components such as ESD protection, transmitter, and receiver circuits for electrical performance and electromagnetic compatibility with antenna regulations, they often result in increased usable area. This is primarily due to the inclusion of TAP embeddings and multiple power clamping circuits connected to the power supply voltage terminals. Specifically, the need for power clamping circuitry between the VDD and VSS voltage terminals for ESD discharge in PS and ND modes contributes to this area penalty and can increase leakage current.

[0155] This application's configuration minimizes area and leakage performance by directly integrating ESD protection into the power delivery network. Ground-gate controlled N-type and P-type MOSFETs provide ESD protection with their source / drain terminals and gate connected to the TVDD voltage. This eliminates the need for separate power supply clamping circuitry between VDD and VSS, thereby reducing both chip area and leakage current.

[0156] See now Figure 3 . Figure 3 This is a schematic layout diagram of a portion of an integrated circuit 30 according to some embodiments. In some embodiments, the integrated circuit 30 relates to, for example... Figure 2 The I / O circuit IOC configuration.

[0157] Integrated circuit 30 has, for example, information about Figure 2 Transistor MP1 is configured as transistor MP1_2. For example... Figure 3 The transistor MP1 is illustrated schematically as follows: an active region (e.g., oxide diffusion, "OD") 101 extending in the x-direction, conductive segments (e.g., on-device metal, "MD") 201 to 202 extending in the y-direction, and a gate structure (e.g., polysilicon, "POLY") 301 extending in the y-direction and introduced between the conductive segments 201 and 202. The integrated circuit 30 further includes conductive wirings (e.g., metal zero layer, "M0") 401 to 403, conductive tracks (e.g., metal layer one, "M1") 501 to 502, and conductive traces 601 (e.g., metal layer two, "M2").

[0158] In some embodiments, conductive segments 201 to 202 and gate structure 301 are in a first layer above active region 101. Conductive connections 401 to 403 extend in the x-direction and are disposed in a second layer above the first layer. Conductive connections 401 to 403 are separated from each other in the y-direction. Conductive tracks 501 to 502 extend in the y-direction and are disposed in a third layer above the second layer. Conductive tracks 501 to 502 are separated from each other in the x-direction. Conductive trace 601 is in a fourth layer above the third layer and extends in the x-direction. In some embodiments, gate structure 301 is diced from a polycrystalline diced layer (also referred to as "CPO" in some embodiments).

[0159] In some embodiments, gate structure 301 corresponds to the gate terminal of transistor MP1_2. Conductive segment 201 corresponds to the drain / source terminals of transistor MP1_2. Conductive segment 202 corresponds to the source / drain terminals of transistor MP1_2.

[0160] Conductive segment 201 is coupled to conductive terminal 401 via via VD1, wherein conductive terminal 401 is coupled to a pad. Gate structure 301 is coupled to conductive terminal 402 via via VG1. Conductive segment 202 is coupled to conductive terminal 403 via via VD2. Conductive terminals 402 and 403 are coupled to conductive rails 501 and 502 via vias VIA0_1 and VIA0_2, respectively. Conductive rails 501 and 502 are coupled to conductive trace 601 via vias VIA1_1 and VIA1_2, respectively, wherein conductive trace 601 is coupled to the voltage terminal n1 of the receiving power supply voltage TVDD.

[0161] See now Figure 4A . Figure 4A This is a schematic diagram of the layout of a portion of an integrated circuit 40 according to some embodiments. Regarding... Figures 1 to 3 Implementation examples, Figure 4A Similar elements are designated with the same reference numerals for ease of understanding. Specific operations of similar elements that have been discussed in detail in the preceding paragraphs are omitted here for brevity.

[0162] exist Figure 4A In one embodiment, integrated circuit 40 further includes a P-type transistor MP1_3 coupled in parallel with transistor MP1_2 to implement... Figure 2 The transistor MP1. Specifically, the integrated circuit 40 includes a conductive segment 203 disposed above the active region 101 and a gate structure 302.

[0163] In some embodiments, conductive segment 203 corresponds to the source / drain terminals of transistor MP1_3, which are coupled to voltage terminal n1 via via VD3, conductive wiring 403, conductive rail 502, and conductive trace 601. Conductive segment 201 further corresponds to the drain / source terminals of transistor MP1_3.

[0164] The gate structure 302 corresponds to the gate terminal of transistor MP1_3 and is coupled to conductive wiring 402, and is further coupled to power supply voltage TVDD via conductive rail 501 and conductive trace 601.

[0165] Figure 4B Depicting according to some embodiments Figure 4A A cross-sectional view of integrated circuit 40 obtained along line AA'.

[0166] like Figure 4B The diagram illustrates that conductive wiring 402 is positioned below conductive rail 501 and conductive trace 601, and is electrically coupled to conductive rail 501 via via VIA0_1. Conductive rail 501 is coupled to conductive trace 601 via via VIA1_1. Therefore, in some embodiments, ESD protection circuit 11 discharges ESD current (e.g., I_PD and / or I_PS) via conductive wiring 402, conductive rail 501, and conductive trace 601.

[0167] See now Figure 5 . Figure 5 This is a schematic layout diagram of a portion of an integrated circuit 50 according to some embodiments. The integrated circuit 50 relates to, for example... Figure 3 The integrated circuit has 30 configurations.

[0168] and Figure 3 In comparison, Figure 5 The conductive wires 402 to 403 of the integrated circuit 50 are coupled to the conductive rail 501 and further coupled to the conductive trace 601 via the via VIA1_1, instead of coupling the conductive wires 402 to 403 to separate conductive wires.

[0169] See now Figure 6A . Figure 6A This is a schematic diagram of the layout of a portion of an integrated circuit 60 according to some embodiments. Regarding... Figures 1 to 5 Implementation examples, Figure 6A Similar elements are designated with the same reference numerals for ease of understanding. In some embodiments, integrated circuit 60 refers to, for example, Figure 2 I / O circuits IOC and Figure 5 The integrated circuit 50 configuration.

[0170] like Figure 6AAs illustrated, integrated circuit 60 further includes a P-type transistor MP2_1. In some embodiments, transistor MP2_1 is configured with respect to, for example... Figure 2 The transistor MP2 configuration of receiver / transmitter circuit 13 in the circuit.

[0171] Specifically, the integrated circuit 60 further includes an active region 102, conductive segments 204 to 205, a gate structure 303, and conductive connections 404 to 405. In some embodiments, the active region 102 is configured with respect to, for example, active region 101. The gate structure 303 is configured with respect to, for example, gate structure 301. The conductive connections 404 and 405 are configured with respect to, for example, conductive connection 401.

[0172] Active regions 101 and 102 are separated from each other by a continuous polysilicon wiring along the x-direction above the active region edge (CPODE) C304. In some embodiments, the CPODE can be formed using shallow trench isolation (STI) technology. The trench may be deposited with a dielectric material. By using a dielectric material, the CPODE does not provide an electrical or conductive path and prevents or at least reduces / minimizes current leakage across active regions 101 and 102.

[0173] Conductive segments 204 to 205 and gate structure 303 extend across active region 102. Conductive segments 201 and 204 are disposed between conductive segments 202 and 205. In some embodiments, conductive segment 204 corresponds to the drain / source terminals of transistor MP2_1 and is coupled to pad 10 via conductive connection 401. Conductive segment 205 corresponds to the source / drain terminals of transistor MP2_1 and is coupled to conductive connection 405 via conductive structure VDR extending in the x-direction and overlapping conductive connection 405. Conductive connection 405 is further coupled to voltage terminal n3 to receive power supply voltage VDD.

[0174] In some embodiments, the CMD layer (i.e., a dummy source / drain electrode) covers the conductive segment 204 to isolate the conductive segment 204 from the conductive structure VDR and the conductive wiring 405. In other words, as Figure 6A As shown in the diagram, conductive sections 201, 202 and 204 are disconnected from the voltage terminal n3 that provides the power supply voltage VDD.

[0175] Conductive wire 404 is electrically isolated from conductive wire 402 by a CM0A layer (i.e., a dummy metal contact). In other words, wires 402 and 404 are separated from each other along the x-direction.

[0176] Gate structure 303 corresponds to the gate terminal of transistor MP2_1 and is coupled to an internal signal via via VG3 and conductive wiring 404. This internal signal is... Figure 2The functional circuit FC.

[0177] See now Figure 6B . Figure 6B Depicting according to some embodiments Figure 6A A cross-sectional view of integrated circuit 60 obtained along line BB'.

[0178] For illustrative purposes, conductor sections 201 and 204 to 205 are separated from conductive wiring 403 along the z-direction and electrically isolated from conductive rail 501. Conductive section 202 is coupled to conductive wiring 403 via via VD2 and further coupled to conductive rail 501 via via VIA0_2.

[0179] See now Figure 6C . Figure 6C Depicting according to some embodiments Figure 6A A cross-sectional view of integrated circuit 60 obtained along line CC'.

[0180] For illustration purposes, conductive segment 205 is coupled to conductive terminal 405 via conductive structure VDR, which is introduced between conductive terminal 405 and conductive segment 205. Conductive terminal 405 is separated from conductive rail 501 along the x-direction.

[0181] See now Figure 7 . Figure 7 This is a schematic diagram of the layout of a portion of an integrated circuit 70 according to some embodiments. Regarding... Figures 1 to 6C Implementation examples, Figure 7 Similar elements in the design are specified by the same reference numerals for ease of understanding. In some embodiments, integrated circuit 70 refers to, for example, Figure 2 I / O circuits IOC and Figure 5 The integrated circuit 50 configuration.

[0182] like Figure 7 The diagram schematically illustrates that an ESD protection circuit 11 is configured between the receiver RX, transmitter TX, and antenna effect protection circuit ANT in a layout diagram. In some embodiments, the ESD protection circuit 11 includes features for implementing... Figure 2 The transistor MP1 and multiple P-type transistors MP71 and used for implementation Figure 2 The transistor MN1 has multiple N-type transistors MN71.

[0183] See now Figure 8 . Figure 8 According to some embodiments Figure 7 A schematic diagram of the layout of part of integrated circuit 70. Regarding... Figures 1 to 7 Implementation examples, Figure 8 Similar elements are specified using the same reference numerals for ease of understanding.

[0184] like Figure 8 As illustrated, the conductive segment 202 corresponding to the drain / source terminals of transistor MP71 is shared by MN71 and corresponds to the drain / source terminals of transistor MN71. The conductive segment 202 is further coupled to pad 10 via: via VD1 coupled to conductive wiring 407, via VIA0_8 coupling conductive wiring 407 to conductive rail 507, and via VIA1_8 coupling conductive rail 507 to conductive wiring 608. Conductive trace 608 is coupled to pad 10.

[0185] Furthermore, the conductive segment 209 extends in the y-direction and corresponds to the source / drain terminals of the transistor MN71. The conductive segment 209 is further coupled to the conductive connection 409 via the conductive structure VDR8. In some embodiments, the conductive connection 409 is coupled to the power supply voltage VSS provided by the voltage terminal n2.

[0186] Gate structure 308 extends in the y-direction and corresponds to the gate terminal of transistor MN71. Gate structure 308 is coupled to conductive wiring 408, which is coupled to the power supply voltage VSS provided by voltage terminal n2.

[0187] In some embodiments, conductive segment 209 is configured, for example, with conductive segment 201. Gate structure 308 is configured, for example, with gate structure 301. Wire connections 407 to 409 are configured, for example, with conductive connection 401. Conductive rail 507 is configured, for example, with conductive rail 501. Conductive trace 608 is configured, for example, with conductive trace 601. Conductive structure VDR8 is configured, for example, with conductive structure VDR.

[0188] See now Figures 9A to 9B . Figure 9A and Figure 9B This is a schematic diagram of a portion of an antenna effect protection circuit 900 according to some embodiments. In some embodiments, the antenna effect protection circuit 900 relates to, for example... Figure 1 and Figure 7 The antenna effect protection circuit ANT configuration.

[0189] In some embodiments, the antenna effect protection circuit 900 includes a first type, such as... Figure 9A The diagram illustrates at least one N-type transistor 901 and a second type, such as... Figure 9B At least one P-type transistor 902 is illustrated. The gate, source, and drain of each transistor are electrically coupled together to a pad 10.

[0190] Therefore, the transistors are dummy transistors electrically coupled and do not affect the operation or functionality of the IC device after the manufacturing process. The P-type transistor 901 and N-type transistor 902 of the antenna effect protection circuit 900 form corresponding diode structures together with the IC device substrate Psub. These corresponding diode structures protect other functional transistors from damage caused by antenna effects attributable to the IC device manufacturing process.

[0191] like Figure 9A As illustrated, an N-type dopant is added to the substrate Psub to form an N-type doped region N+ corresponding to the N-type transistor 901. The N-type doped region N+ is coupled to the gate region 931 and the pad 10 of the N-type transistor 901. In addition, a P-type doped region P+ is formed in the substrate Psub and coupled to the voltage terminal n2 to receive the power supply voltage VSS.

[0192] exist Figure 9A In this process, a P-type dopant is added to an N-type well NW in the substrate Psub to form a P-type doped region P+ corresponding to the P-type transistor 902. The P-type doped region P+ is coupled to the gate region 932 and the pad 10 of the P-type transistor 902. In addition, an N-type doped region N+ is formed in the N-type well NW and coupled to the voltage terminal n3 to receive the power supply voltage VDD.

[0193] Figures 1 to 9B The configurations are shown for illustrative purposes. Various implementations are within the scope of the embodiments disclosed herein.

[0194] Figure 10 This is a flowchart of a method 1000 for manufacturing an integrated circuit according to some embodiments. It should be understood that additional operations may be performed by... Figure 10 The processes illustrated are provided before, during, and after, and some additional embodiments of the method described below may be replaced or eliminated. The order of operations / processes may be interchangeable. Similar reference numerals are used to designate similar elements throughout the various views and illustrative embodiments. Method 1000 has operations S1001 to S1002, and will be referred to Figures 2 to 3 The following is a discussion of the implementation examples.

[0195] In operation S1001, the ESD current I_PD is discharged from the pad 10 to the voltage terminal n1 via the ESD protection circuit 11. In some embodiments, the P-type transistor MP1 is turned on to transmit the ESD current I_PD.

[0196] In operation S1002, the ESD current I_PS is discharged from the pad 10 to the voltage terminal n2 via the ESD protection circuit 11 and the power clamping circuit 16.

[0197] See now Figure 11 . Figure 11This is a block diagram of an electronic design automation (EDA) system 1100 for designing integrated circuit layout designs according to some embodiments of this disclosure. The EDA system 1100 is used to implement one or more operations for manufacturing IC devices 100, integrated circuits 30, 40, 50, 60, and 70, and in conjunction with... Figures 1 to 10 Further explanation. In some embodiments, EDA system 1100 includes an APR system.

[0198] In some embodiments, the EDA system 1100 is a general-purpose computing device including a hardware processor 1120 and a non-transitory computer-readable storage medium 1160. The storage medium 1160 is specifically encoded with, i.e., storing, computer program code (instructions) 1161, i.e., an executable instruction set. Execution of the instructions 1161 performed by the hardware processor 1120 represents (at least partially) an EDA tool that implements, for example, the manufacture of some or all of integrated circuits 30, 40, 50, 60, and 70.

[0199] Processor 1120 is electrically coupled to computer-readable storage medium 1160 via bus 1150. Processor 1120 is also electrically coupled to I / O interface 1110 and manufacturing equipment 1170 via bus 1150. Network interface 1130 is also electrically connected to processor 1120 via bus 1150. Network interface 1130 is connected to network 1140, enabling processor 1120 and computer-readable storage medium 1160 to be connected to external components via network 1140. Processor 1120 is used to execute computer program code 1161 encoded in computer-readable storage medium 1160 so that EDA system 1100 can be used to perform some or all of the mentioned processes and / or methods. In one or more embodiments, processor 1120 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0200] In one or more embodiments, the computer-readable storage medium 1160 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 1160 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 1160 includes compact disk-read-only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0201] In one or more embodiments, storage medium 1160 stores computer program code 1161 that enables EDA system 1100 (wherein this execution represents (at least partially) EDA tools) to perform part or all of the mentioned programs and / or methods. In one or more embodiments, storage medium 1160 also stores information that facilitates the execution of part or all of the mentioned programs and / or methods. In one or more embodiments, storage medium 1160 stores a standard component library 1162 that includes standard components such as those disclosed herein, for example, cells included in portions of integrated circuits 30, 40, 50, 60, and 70.

[0202] EDA system 1100 includes an I / O interface 1110. The I / O interface 1110 is coupled to external circuitry. In one or more embodiments, the I / O interface 1110 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or directional keys for transmitting information and commands to processor 1120.

[0203] EDA system 1100 also includes a network interface 1130 coupled to processor 1120. Network interface 1130 allows EDA system 1100 to communicate with network 1140, to which one or more other computer systems are connected. Network interface 1130 includes a wireless network interface, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the mentioned programs and / or methods are implemented in two or more systems 1100.

[0204] EDA system 1100 also includes manufacturing equipment 1170 coupled to processor 1120. Manufacturing equipment 1170 is used to manufacture integrated circuits, such as integrated circuits 30, 40, 50, 60 and 70, according to design documents processed by processor 1120.

[0205] EDA system 1100 receives information via I / O interface 1110. The information received via I / O interface 1110 includes one or more of the following: instructions, data, design rules, standard component libraries, and / or other parameters for processing by processor 1120. The information is transmitted to processor 1120 via bus 1150. EDA system 1100 also receives UI-related information via I / O interface 1110. This information is stored in computer-readable storage medium 1160 as a user interface (UI) 1163.

[0206] In some embodiments, some or all of the mentioned programs and / or methods are implemented as standalone software applications for processor execution. In some embodiments, some or all of the mentioned programs and / or methods are implemented as software applications that are part of additional software applications. In some embodiments, some or all of the mentioned programs and / or methods are implemented as plug-ins to software applications. In some embodiments, at least one of the mentioned programs and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the mentioned programs and / or methods are implemented as software applications used by EDA system 1100. In some embodiments, layout diagrams including standard components are generated using tools such as VIRTUOSO®, available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generation tool.

[0207] In some embodiments, the program is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / embedded storage or memory units, such as one or more of the following: optical discs, such as DVDs; magnetic disks, such as hard disks; semiconductor memory, such as ROM, RAM, memory cards, and the like.

[0208] Figure 12 This is a block diagram of an IC manufacturing system 1200 according to some embodiments and an IC manufacturing process associated with the IC manufacturing system. In some embodiments, based on the layout diagram, at least one of the following is manufactured using the IC manufacturing system 1200: (A) one or more semiconductor photomasks, or (B) at least one element in a layer of a semiconductor integrated circuit.

[0209] exist Figure 12In this IC manufacturing system 1200, entities such as a design plant 1210, a photomask plant 1220, and an IC manufacturer / fab (“fab”) 1230 interact with each other in design, development, and manufacturing cycles and / or services related to the manufacture of IC devices 1240. The entities in the IC manufacturing system 1200 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as Ethernet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more of the other entities and / or receives services from one or more of the other entities. In some embodiments, two or more of the design plant 1210, photomask plant 1220, and IC fabrication plant 1230 are owned by a single company. In some embodiments, two or more of the design plant 1210, photomask plant 1220, and IC fabrication plant 1230 coexist in a common facility and use common resources.

[0210] Design facility (or design team) 1210 produces IC design layout 1211. IC design layout 1211 includes various geometric patterns, such as those designed for IC device 1240, as mentioned above. Figures 3 to 9B The integrated circuits 30, 40, 50, 60, and 70 described in the discussion are... Figures 3 to 8 The IC layout design is described in the document. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute the various components of the IC device 1240 to be manufactured. Various layers are combined to form various IC features. For example, a portion of the IC layout diagram 1211 includes various IC features, such as active regions, gate electrodes, source and drain electrodes, conductive segments, or vias for interlayer interconnects to be formed in and on a semiconductor substrate (such as a silicon wafer) and in various material layers disposed on the semiconductor substrate. The design plant 1210 performs appropriate design procedures to form the IC layout diagram 1211. Design procedures include one or more of logic design, physical design, or placement and routing. The IC layout diagram 1211 is presented in one or more data files containing information about the geometric patterns. For example, the IC layout diagram 1211 may be expressed in GDSII or DFII file format.

[0211] Photomask fabrication plant 1220 includes data preparation 1221 and photomask fabrication 1222. Photomask fabrication plant 1220 uses an IC design layout 1211 to fabricate one or more photomasks 1223 for fabricating various layers of an IC device 1240 according to the IC design layout 1211. Photomask fabrication plant 1220 performs photomask data preparation 1221, in which the IC design layout 1211 is translated to a representative data file ("RDF"). Photomask data preparation 1221 provides the RDF to photomask fabrication 1222. Photomask fabrication 1222 includes a photomask writer. The photomask writer converts the RDF into an image on a substrate, such as a photomask (master photomask) 1223 or a semiconductor wafer 1232. The IC design layout 1211 is manipulated by photomask data preparation 1221 to conform to the specific characteristics of the photomask writer and / or the requirements of the IC fabrication plant 1230. Figure 12 In this context, data preparation 1221 and photomask fabrication 1222 are described as separate elements. In some embodiments, data preparation 1221 and photomask fabrication 1222 can be collectively referred to as photomask data preparation.

[0212] In some embodiments, data preparation 1221 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that can cause self-diffraction, interference, other process effects, and the like. OPC adjusts the IC design layout diagram 1211. In some embodiments, data preparation 1221 includes other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-transfer masks, other suitable techniques, and combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0213] In some embodiments, data preparation 1221 includes checking an IC design layout 1211 using a mask rule checker (MRC) that has undergone processing in an OPC using a set of mask production rules containing certain geometric and / or connectivity constraints to ensure sufficient margin, take into account variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout 1211 to compensate for constraints during mask fabrication 1222, which may undo modifications performed via the OPC to satisfy the mask production rules.

[0214] In some embodiments, data preparation 1221 includes lithography process checking (LPC), which simulates the process implemented by IC manufacturing plant 1230 to manufacture IC device 1240. LPC simulates this process based on IC design layout 1211 to produce a simulated manufactured device, such as IC device 1240. Processing parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as virtual image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and similar or combinations thereof. In some embodiments, after the simulated manufactured device has been produced by LPC, if the simulated device shape does not sufficiently approximate the design rules, OPC and / or MRC are repeated to further refine the IC design layout 1211.

[0215] It should be understood that the above description of data preparation 1221 has been simplified for clarity. In some embodiments, data preparation 1221 includes additional features, such as logic operations (LOPs), to modify the IC design layout 1211 according to manufacturing rules. Additionally, the processes applied to the IC design layout 1211 during data preparation 1221 may be performed in a variety of different sequences.

[0216] Following data preparation 1221 and during photomask fabrication 1222, photomask 1223 or a group of photomasks 1223 is fabricated based on a modified IC design layout 1211. In some embodiments, photomask fabrication 1222 includes performing one or more lithography exposures based on the IC design layout 1211. In some embodiments, an electron beam (e-beam, e-beam) or multiple electron beams are used to pattern the photomask (photomask or master photomask) 1223 based on the modified IC design layout 1211. Photomask 1223 can be formed using various techniques. In some embodiments, photomask 1223 is formed using a binary technique. In some embodiments, the photomask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image-sensitive material layer (e.g., photoresist) layer coated on the wafer is blocked through the opaque areas and transmitted through the transparent areas. In one example, a binary photomask version of photomask 1223 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas. In another example, photomask 1223 is formed using a phase shift mask (PSM) technique. In a phase shift mask (PSM) version of photomask 1223, various features in a pattern formed on the PSM are used to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The photomask produced by photomask fabrication 1222 is used in a variety of processes. For example, such photomasks are used in ion implantation processes to form various active regions in semiconductor wafer 1232, in etching processes to form various etched regions in semiconductor wafer 1232, and / or in other suitable processes.

[0217] IC manufacturing plant 1230 includes wafer fabrication 1231. IC manufacturing plant 1230 is an IC manufacturing operation that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC manufacturing plant 1230 is a semiconductor foundry. For example, there may be manufacturing facilities for front-end-of-line (FEOL) manufacturing of various IC products, a second manufacturing facility that provides back-end-of-line (BEOL) manufacturing for interconnecting and packaging of IC products, and a third manufacturing facility that provides other services for the foundry business.

[0218] IC manufacturing plant 1230 uses a photomask 1223 manufactured by photomask fabrication plant 1220 to manufacture IC device 1240. Therefore, IC manufacturing plant 1230 uses IC design layout 1211 at least indirectly to manufacture IC device 1240. In some embodiments, semiconductor wafer 1232 is manufactured by IC manufacturing plant 1230 using photomask 1223 to form IC device 1240. In some embodiments, IC manufacturing includes performing one or more lithography exposures at least indirectly based on IC design layout 1211. Semiconductor wafer 1232 includes a silicon substrate, or other suitable substrate on which a material layer is formed. Semiconductor wafer 1232 further includes one or more of various active regions, dielectric features, multiple quasi-interconnects, and the like (formed in subsequent manufacturing steps).

[0219] An integrated circuit is provided and includes: a header circuit coupled to a first voltage terminal, providing a first power supply voltage and for providing a second power supply voltage at a second voltage terminal; a receiver / transmitter circuit coupled between the second voltage terminal and a third voltage terminal, providing a third power supply voltage less than the second power supply voltage; and an electrostatic discharge (ESD) protection circuit coupled to a pad and the receiver / transmitter circuit and further coupled between the first voltage terminal and the third voltage terminal.

[0220] In some embodiments, the ESD protection circuit includes: a first transistor having a gate terminal and a source / drain terminal coupled to the first voltage terminal; and a second transistor having a gate terminal and a source / drain terminal coupled to the third voltage terminal; and a drain / source terminal coupled to a drain / source terminal of the first transistor, the pad, and the receiver / transmitter circuit.

[0221] In some embodiments, the receiver / transmitter circuit includes: a third transistor having: a source / drain terminal coupled to the second voltage terminal; a drain / source terminal coupled to the pad; and a body terminal of the third transistor coupled to the first voltage terminal; and a fourth transistor having: a gate terminal coupled to a gate terminal of the third transistor; a source / drain terminal coupled to the third voltage terminal; and a drain / source terminal coupled to the pad.

[0222] In some embodiments, the first transistor and the third transistor have a first conduction type, and the second transistor and the fourth transistor have a second conduction type different from the first conduction type.

[0223] In some embodiments, the first transistor and the third transistor are P-type transistors, and the second transistor and the fourth transistor are N-type transistors.

[0224] In some embodiments, the ESD protection circuit is used to discharge an ESD current flowing from the pad to the first voltage terminal. The integrated circuit further includes a power clamping circuit coupled between the first voltage terminal and the third voltage terminal and used to discharge the ESD current from the first voltage terminal to the third voltage terminal.

[0225] In some embodiments, the receiver / transmitter circuit includes: a first transistor having: a source / drain terminal coupled to the second voltage terminal; and a drain / source terminal coupled to the pad. The ESD protection circuit includes: a second transistor having a gate terminal and a source / drain terminal, the gate terminal and the source / drain terminal being coupled to a body terminal of the first transistor.

[0226] In some embodiments, the ESD protection circuit is used to discharge an ESD current from the pad to the first voltage terminal.

[0227] In some embodiments, the integrated circuit further includes: a capacitor coupled to the head circuit and the receiver / transmitter circuit and disconnected from the second transistor.

[0228] In some embodiments, the first power supply voltage is greater than the second power supply voltage.

[0229] An integrated circuit is provided and includes: a receiver / transmitter circuit coupled between a first voltage terminal and a second voltage terminal and including a first transistor having a first terminal coupled to the first voltage terminal and a second terminal coupled to a pad; and an electrostatic discharge (ESD) protection circuit including a second transistor coupled to the receiver / transmitter circuit at the pad and further coupled to a third voltage terminal different from the second voltage terminal. The first transistor and the second transistor have the same conduction type.

[0230] In some embodiments, the first transistor and the second transistor are P-type transistors.

[0231] In some embodiments, the integrated circuit further includes a first conductive connection and a second conductive connection extending in a first direction, wherein the first conductive connection is coupled to the pad and the second conductive connection is coupled to the second voltage terminal. A first transistor includes a first conductive segment and a second conductive segment extending in a second direction. The first conductive segment is coupled to the first conductive connection, and the second conductive segment is coupled to the second conductive connection via a conductive structure overlapping the second conductive connection. A second transistor includes a third conductive segment and a fourth conductive segment extending in the second direction. The third conductive segment is coupled to the first conductive connection, and the fourth conductive segment is coupled to the third voltage terminal.

[0232] In some embodiments, the integrated circuit further includes a third conductive connection extending in the first direction and coupled to the fourth conductive segment, wherein the first conductive connection and the third conductive connection are separated from each other along the second direction; and a conductive rail coupled to the third voltage terminal and the third conductive connection. The conductive rail is disposed in a layer above where the third conductive connection is disposed.

[0233] In some embodiments, the ESD protection circuit is used to discharge an ESD current from the pad to the third voltage terminal via the conductive rail.

[0234] In some embodiments, the first conductive segment and the third conductive segment are disposed between the second conductive segment and the fourth conductive segment.

[0235] In some embodiments, a voltage level at the first voltage terminal is equal to a voltage level at the third voltage terminal.

[0236] A method for discharging electrostatic discharge (ESD) current in an integrated circuit, wherein the integrated circuit includes a receiver / transmitter circuit coupled to a pad and an ESD protection circuit, wherein the receiver / transmitter circuit is coupled between a first voltage terminal and a second voltage terminal, and the ESD protection circuit is coupled between the second voltage terminal and a third voltage terminal different from the first and second voltage terminals. The method includes: discharging a first ESD current from the pad to the third voltage terminal via the ESD protection circuit; and discharging a second ESD current from the pad to the second voltage terminal via the ESD protection circuit and a power clamping circuit.

[0237] In some embodiments, the power clamping circuit is electrically connected between the second voltage terminal and the third voltage terminal.

[0238] In some embodiments, discharging the second ESD current further includes turning on a P-type transistor having a gate terminal and a source terminal coupled together to the third voltage terminal and a drain terminal coupled to the pad.

[0239] An integrated circuit is provided, comprising a receiver / transmitter circuit, an electrostatic discharge (ESD) protection circuit, a power clamping circuit, and a power supply clamping circuit. The receiver / transmitter circuit is coupled between a first voltage terminal and a second voltage terminal. The ESD protection circuit is coupled between the second voltage terminal and a third voltage terminal. The third voltage terminal is different from the first and second voltage terminals. The receiver / transmitter circuit and the ESD protection circuit are coupled to a pad. The power supply clamping circuit is coupled between the second and third voltage terminals. The ESD protection circuit discharges a first ESD current from the pad to the third voltage terminal. The ESD protection circuit and the power supply clamping circuit discharge a second ESD current from the pad through the third voltage terminal to the second voltage terminal.

[0240] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of an embodiment disclosed herein. Those skilled in the art will understand that an embodiment disclosed herein can be used as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of an embodiment disclosed herein, and that such equivalent constructions can be modified, substituted, and replaced in various ways without departing from the spirit and scope of an embodiment disclosed herein.

Claims

1. An integrated circuit, characterized in that, Include: A head circuit coupled to a first voltage terminal provides a first power supply voltage and is used to provide a second power supply voltage at a second voltage terminal; A receiver / transmitter circuit coupled between the second voltage terminal and a third voltage terminal provides a third power supply voltage that is lower than the second power supply voltage; and An electrostatic discharge protection circuit is coupled to a pad and the receiver / transmitter circuit and further coupled between the first voltage terminal and the third voltage terminal.

2. The integrated circuit as described in claim 1, characterized in that, This electrostatic discharge protection circuit includes: A first transistor has: A gate terminal and a source / drain terminal are coupled to the first voltage terminal; A second transistor having: A gate terminal and a source / drain terminal are coupled to the third voltage terminal; and A drain / source terminal is coupled to a drain / source terminal of the first transistor, the pad, and the receiver / transmitter circuit.

3. The integrated circuit as described in claim 2, characterized in that, The receiver / transmitter circuit includes: A third transistor, having: A source / drain terminal coupled to the second voltage terminal; Coupled to one drain / source terminal of the pad; and One of the main terminals of the third transistor is coupled to the first voltage terminal; and A fourth transistor, having: Coupled to a gate terminal of the third transistor; A source / drain terminal coupled to the third voltage terminal; and Coupled to one drain / source terminal of the pad.

4. The integrated circuit as described in claim 3, characterized in that, The first transistor and the third transistor have a first conduction type, and the second transistor and the fourth transistor have a second conduction type different from the first conduction type.

5. The integrated circuit as described in claim 3, characterized in that, The first transistor and the third transistor are P-type transistors, and the second transistor and the fourth transistor are N-type transistors.

6. The integrated circuit as described in claim 2, characterized in that, The electrostatic discharge protection circuit is used to discharge an electrostatic discharge current flowing from the pad to the first voltage terminal. The integrated circuit further includes: A power clamping circuit is coupled between the first voltage terminal and the third voltage terminal and is used to discharge the electrostatic discharge current from the first voltage terminal to the third voltage terminal.

7. The integrated circuit as claimed in claim 1, characterized in that, The receiver / transmitter circuit includes: A first transistor has: One source / drain terminal coupled to the second voltage terminal; and Coupled to one drain / source terminal of the pad; The electrostatic discharge protection circuit includes: A second transistor having a gate terminal and a source / drain terminal, the gate terminal and the source / drain terminal being coupled to a body terminal of the first transistor.

8. The integrated circuit as described in claim 7, characterized in that, The electrostatic discharge protection circuit is used to discharge an electrostatic discharge current from the pad to the first voltage terminal.

9. An integrated circuit, characterized in that, Include: A receiver / transmitter circuit coupled between a first voltage terminal and a second voltage terminal and including a first transistor having a first terminal coupled to the first voltage terminal and a second terminal coupled to a pad; and An electrostatic discharge protection circuit includes a second transistor, which is coupled to the receiver / transmitter circuit at the pad and further coupled to a third voltage terminal different from the second voltage terminal. The first transistor and the second transistor have the same conduction type.

10. An integrated circuit, characterized in that, Include: A receiver / transmitter circuit is coupled between a first voltage terminal and a second voltage terminal; An electrostatic discharge protection circuit is coupled between the second voltage terminal and a third voltage terminal, wherein the third voltage terminal is different from the first voltage terminal and the second voltage terminal, and wherein the receiver / transmitter circuit and the electrostatic discharge protection circuit are coupled to a pad. and A power clamping circuit is coupled between the second voltage terminal and the third voltage terminal, wherein: The electrostatic discharge protection circuit is used to discharge a first electrostatic discharge current from the pad to the third voltage terminal; and The electrostatic discharge protection circuit and the power clamping circuit are used to discharge a second electrostatic discharge current from the pad to the second voltage terminal via the third voltage terminal.

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