Modular equipment bus system based on 485 serial port

Abstract

The utility model relates to the technical field of modularized equipment communication, in particular to a modularized equipment bus system based on a 485 serial port, which comprises host equipment and slave equipment. The host device comprises a first microcontroller (an integrated serial port and a timer), a first 485 transceiver and a host side auxiliary logic circuit. And the logic circuit is connected with the timer output and the serial port sending end, and controls the sending enabling of the first 485 transceiver. And the slave equipment comprises a second microcontroller and a second 485 transceiver. And the 485 transceivers of the host equipment and the slave equipment are connected through a differential line. According to the utility model, the combination of the MCU serial port, the DMA, the timer, the 485 and the auxiliary logic is utilized, the bus communication with high speed, interference resistance, low cost and strong universality is realized, and the bandwidth is easy to expand.

Description

Technical Field

[0001] This utility model relates to the field of modular device communication technology, and more specifically, to a modular device bus system based on a 485 serial port. Background Technology

[0002] Modular I / O devices are widely used in current industrial automation, embedded systems, and IoT devices due to their flexibility and scalability. These devices typically utilize cost-effective, highly integrated microcontroller units (MCUs), such as the common STM32 series microcontrollers. These MCUs provide developers with various built-in communication bus interfaces to facilitate data exchange between modules or between devices and host computers. Common communication methods include the TTL serial interface provided by a Universal Asynchronous Receiver / Transmitter (UART), a widely used point-to-point or simple multi-point communication method with simple hardware implementation and relatively straightforward software programming. Furthermore, the I2C (Inter-Integrated Circuit) bus, requiring only two signal lines for multi-master / multi-slave communication, is popular for short-range board-level communication and is often used to connect peripherals such as sensors and memory. The SPI (Serial Peripheral Interface) bus, with its full-duplex, high-speed characteristics, excels in applications requiring fast data transmission, such as communication with high-speed peripherals like Flash memory and ADC / DAC. For specific applications requiring large-scale parallel data transmission or extremely high real-time performance, some MCUs also support parallel bus interfaces. In industrial control, where high reliability and interference immunity are crucial, the CAN (Controller Area Network) bus, with its differential signal transmission and robust error detection and handling mechanisms, has become a standard choice, widely used in automotive electronics, industrial automation, and other scenarios. These communication interfaces each have their own design intent and applicable scope, collectively forming the foundation of modular device communication technology and providing diverse options for data interaction in different application scenarios. Designers typically choose the most suitable communication scheme based on the module's functional requirements, cost budget, development cycle, and specific requirements for communication speed, distance, and reliability. However, in the pursuit of higher communication speeds, stronger interference immunity, and better cost-effectiveness in modular device bus design, the limitations of the aforementioned traditional communication methods are gradually becoming apparent. On the one hand, while TTL serial ports are simple to implement, their transmission rate often fails to meet the demands of high-speed data exchange when used as a bus, and their single-ended signal transmission makes them susceptible to interference in complex electromagnetic environments, affecting communication stability. On the other hand, the communication rate limit of the I2C bus (such as 400Kbit / s in standard mode) is insufficient for many modern applications, and subtle differences in the I2C hardware implementations of different MCU manufacturers can sometimes cause problems for system integration. As for the SPI bus, although it has a higher speed, its communication distance is usually shorter, and it is mainly suitable for board-level chip communication, making it difficult to use directly as a medium-to-long-distance bus between modules.Furthermore, while parallel communication is direct, it consumes a significant amount of MCU I / O pin resources, leading to increased hardware design complexity and cost, and the interface typically requires specialized design. Additionally, although the CAN bus offers good interference immunity, CAN 2.0B's maximum speed is only 1 Mbit / s, resulting in lower effective data bandwidth, which is insufficient to meet the ever-increasing bandwidth demands. While CANFD offers a significant speed improvement, the cost of MCUs supporting CANFD is relatively high, and the design and implementation of the CAN protocol stack is also complex, placing higher demands on development resources and timelines. Utility Model Content

[0003] The purpose of this invention is to provide a modular device bus system based on the 485 serial port. Through a specific structural combination of MCU serial port, DMA, timer, 485PHY and host-side auxiliary logic circuit, it realizes high-speed and high anti-interference modular device bus communication, and has the advantages of low hardware cost, strong versatility and easy bandwidth expansion.

[0004] The embodiments of this utility model are achieved through the following technical solutions:

[0005] A modular device bus system based on a 485 serial port includes: a master device and a slave device;

[0006] The host device includes: a first microcontroller unit, a first 485 physical layer transceiver, and host-side auxiliary logic circuitry; the first microcontroller unit integrates a serial communication interface and a timer module; the data transceiver terminal of the first 485 physical layer transceiver is connected to the serial communication interface of the first microcontroller unit; the first input terminal of the host-side auxiliary logic circuitry is connected to the output terminal of the timer module of the first microcontroller unit; the second input terminal of the host-side auxiliary logic circuitry is connected to the transmitting terminal of the serial communication interface of the first microcontroller unit; and the output terminal of the host-side auxiliary logic circuitry is connected to the transmitting enable terminal of the first 485 physical layer transceiver.

[0007] The slave device includes: a second microcontroller unit and a second 485 physical layer transceiver. The second microcontroller unit integrates a serial communication interface. The data transceiver terminals of the second 485 physical layer transceiver are connected to the serial communication interface of the second microcontroller unit. The second 485 physical layer transceiver includes a receive enable terminal and a transmit enable terminal. The first 485 physical layer transceiver and the second 485 physical layer transceiver are connected via differential signal lines.

[0008] Optionally, the first microcontroller unit further includes a direct memory access controller, wherein the data output channel of the direct memory access controller is connected to the serial communication interface of the first microcontroller unit, and the trigger input channel of the direct memory access controller is connected to the output of the timer module of the first microcontroller unit.

[0009] Optionally, the host-side auxiliary logic circuit includes gate circuits and delay circuits. The gate circuits are connected to the first input terminal of the host-side auxiliary logic circuit, the input terminal of the delay circuit is connected to the second input terminal of the host-side auxiliary logic circuit, and the output terminals of the gate circuits and delay circuits are connected to the output terminal of the host-side auxiliary logic circuit.

[0010] Optionally, an inverter is also included; the receive enable terminal of the second 485 physical layer transceiver is connected to the output terminal of the host-side auxiliary logic circuit via the inverter.

[0011] Optionally, the second microcontroller unit further includes a clearing flow control input pin, which is connected to the output of the inverter.

[0012] Optionally, the transmit enable pin of the second 485 physical layer transceiver is connected to a preset output pin of the second microcontroller unit.

[0013] Optionally, both the serial communication interface of the first microcontroller unit and the serial communication interface of the second microcontroller unit are TTL level interfaces.

[0014] Optionally, the host device includes at least two sets of parallel transmission channels, each transmission channel consisting of a serial communication interface of the first microcontroller unit, a first 485 physical layer transceiver, and host-side auxiliary logic circuitry; the slave device includes at least two sets of parallel receive / transmit channels, each receive / transmit channel consisting of a serial communication interface of the second microcontroller unit and a second 485 physical layer transceiver.

[0015] The technical solution of this utility model embodiment has at least the following advantages and beneficial effects:

[0016] This invention, on the one hand, effectively solves the problem of data start bit loss caused by the switching delay of the 485 physical layer transceiver during high-speed communication by combining the TTL serial port, DMA controller, and timer module of the MCU with an external 485 physical layer transceiver and host-side auxiliary logic circuit through a specific connection structure. This enables communication rates up to 10 Mbit / s or even higher. Furthermore, by utilizing the characteristics of 485 differential signal transmission, it significantly enhances the bus's anti-interference capability, ensuring data transmission stability and reliability in complex industrial environments. On the other hand, it is compatible with most microcontroller units possessing basic serial port, timer, and DMA functions, providing developers with a wide range of economical hardware options. Moreover, the physical layer mainly uses common 485 chips and a small number of standard gate circuits and / or delay circuits to construct the host-side auxiliary logic circuit, effectively controlling the overall hardware cost and improving the cost-effectiveness and market competitiveness of the solution. Where MCU resources permit, the structure of this invention supports the linear expansion of bus communication bandwidth by setting multiple sets of transmit and receive / transmit channels in parallel, meeting the application requirements for higher data throughput in the future. Attached Figure Description

[0017] Figure 1 Schematic diagram of the host device provided by this utility model;

[0018] Figure 2 This utility model provides a basic architecture diagram of a modular device bus system based on a 485 serial port. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. The components of the embodiments of this utility model described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0020] like Figure 1 As shown, this utility model provides one embodiment: a modular device bus system based on a 485 serial port, including: a master device and a slave device;

[0021] The host device includes: a first microcontroller unit, a first 485 physical layer transceiver, and host-side auxiliary logic circuitry; the first microcontroller unit integrates a serial communication interface and a timer module; the data transceiver terminal of the first 485 physical layer transceiver is connected to the serial communication interface of the first microcontroller unit; the first input terminal of the host-side auxiliary logic circuitry is connected to the output terminal of the timer module of the first microcontroller unit; the second input terminal of the host-side auxiliary logic circuitry is connected to the transmitting terminal of the serial communication interface of the first microcontroller unit; and the output terminal of the host-side auxiliary logic circuitry is connected to the transmitting enable terminal of the first 485 physical layer transceiver.

[0022] The slave device includes: a second microcontroller unit and a second 485 physical layer transceiver. The second microcontroller unit integrates a serial communication interface. The data transceiver terminals of the second 485 physical layer transceiver are connected to the serial communication interface of the second microcontroller unit. The second 485 physical layer transceiver includes a receive enable terminal and a transmit enable terminal. The first 485 physical layer transceiver and the second 485 physical layer transceiver are connected via differential signal lines.

[0023] In practice, the host device controls the host-side auxiliary logic circuit through a timer module and a serial communication interface transmitter, thereby precisely controlling the transmit enable timing of the first 485 physical layer transceiver. When the host transmits, its transmit enable signal is also transmitted to the slave device to control the slave device's receive enable, achieving efficient bus communication.

[0024] Furthermore, the first microcontroller unit also includes a direct memory access controller, the data output channel of which is connected to the serial communication interface of the first microcontroller unit, and the trigger input channel of which is connected to the output of the timer module of the first microcontroller unit.

[0025] In the aforementioned host device, the configuration of the Direct Memory Access Controller (DMA) within the first microcontroller unit is crucial for achieving high-speed data transmission. Specifically, at least one data output channel of this DMA is configured to directly transfer the data block to be sent from memory to the transmit data register of the serial communication interface of the first microcontroller unit, thereby reducing the CPU load and improving data throughput efficiency. Simultaneously, at least one trigger input channel of this DMA is connected to the output of the timer module of the first microcontroller unit (e.g., a timer update event or a capture / compare match event). This allows the timer module to precisely trigger the start of the DMA transfer. In practical applications, the two DMA channels can be configured to form a chained operation. For example, a timer triggers DMA channel one (CH1). After channel one completes its preset task (such as a no-operation or a specific configuration write), it automatically triggers DMA channel two (CH2), which is responsible for sending the actual business data through the serial communication interface.

[0026] Specifically, the host-side auxiliary logic circuit includes gate circuits and delay circuits. The gate circuits are connected to the first input terminal of the host-side auxiliary logic circuit, the input terminal of the delay circuit is connected to the second input terminal of the host-side auxiliary logic circuit, and the output terminals of the gate circuits and delay circuits are connected to the output terminal of the host-side auxiliary logic circuit.

[0027] The host-side auxiliary logic circuit is crucial for achieving precise control of host transmit enable. This host-side auxiliary logic circuit includes at least one gate circuit, such as a combination of AND, OR, and NOT gates, and / or at least one delay circuit, such as an RC delay circuit or a dedicated delay chip. The inputs of the gate circuits and delay circuits are connected to at least one or all of the first and second inputs of the host-side auxiliary logic circuit. Their outputs are connected to the final output of the host-side auxiliary logic circuit, or directly constitute that output. Before data transmission begins, the output signal of the timer module preferentially forces the transmit state of the first 485 physical layer transceiver to overcome transceiver switching delay. After the serial communication interface begins transmitting data, the transmit (TX) signal of the serial communication interface maintains the transmit enable state through this logic circuit until data transmission is complete.

[0028] In this embodiment, an inverter is also included; the receive enable terminal of the second 485 physical layer transceiver is connected to the output terminal of the host-side auxiliary logic circuit via the inverter.

[0029] In implementation, to enable the slave device to automatically switch the operating mode of its second 485 physical layer transceiver based on the master's transmitting status, an inverter is also included. The receive enable pin of the slave device's second 485 physical layer transceiver, typically active low and labeled / RE, is not directly connected to the output of the master-side auxiliary logic circuit. Instead, it is connected to the output of the master-side auxiliary logic circuit via the input and output of the inverter. Thus, when the master-side auxiliary logic circuit outputs a high level, it becomes low after passing through the inverter, thereby enabling the slave device's second 485 physical layer transceiver's receiving function. Conversely, when the master is not transmitting, the slave device's receiving function is disabled.

[0030] Specifically, the second microcontroller unit further includes a clearing and sending flow control input pin, which is connected to the output of the inverter.

[0031] The slave device's second microcontroller unit also has a Clear To Send (CTS) flow control input pin. This pin is connected to the output of the inverter. When the master is sending data (i.e., the master-side auxiliary logic circuit outputs a high level, the inverter outputs a low level, and the slave's CTS pin receives a low-level signal, indicating that the bus is busy; the slave should not attempt to send data at this time. When the master finishes sending data (i.e., the master-side auxiliary logic circuit outputs a low level, the inverter outputs a high level, and the slave's CTS pin receives a high-level signal, indicating that the bus is idle; the slave can then send data), which helps avoid bus conflicts and allows the slave to quickly determine the bus status and issue a acknowledgment after receiving and processing the data.

[0032] In one embodiment, the transmit enable pin of the second 485 physical layer transceiver is connected to a preset output pin of the second microcontroller unit.

[0033] The slave device needs to receive data and also send data to the master. To this end, the transmit enable pin of the slave device's second 485 physical layer transceiver is connected to a preset general-purpose output pin of its own second microcontroller unit. When data transmission is needed, this preset output pin is controlled to output an appropriate level, thereby activating the transmit function of the second 485 physical layer transceiver and sending the data to the master via the 485 bus. After the data transmission is complete, the second microcontroller unit controls the pin to return to the non-transmit state.

[0034] More specifically, both the serial communication interface of the first microcontroller unit and the serial communication interface of the second microcontroller unit are TTL level interfaces.

[0035] Specifically, the host device includes at least two sets of parallel transmission channels, each transmission channel consisting of a serial communication interface of the first microcontroller unit, a first 485 physical layer transceiver, and host-side auxiliary logic circuitry; the slave device includes at least two sets of parallel receive / transmit channels, each receive / transmit channel consisting of a serial communication interface of the second microcontroller unit and a second 485 physical layer transceiver.

[0036] In implementation, the structure of this embodiment supports parallel expansion. On the host device side, at least two sets of parallel transmission channels can be included. Each transmission channel consists of an independent serial communication interface of the first microcontroller unit, an independent first 485 physical layer transceiver, and an independent host-side auxiliary logic circuit. Crucially, each set of host-side auxiliary logic circuits is connected to the corresponding independent timer module output channel and the corresponding independent serial communication interface transmitter of the first microcontroller unit. Each parallel transmission channel has its own independent timing control and data path. On the slave device side, at least two sets of parallel receive / transmit channels can also be included. Each receive / transmit channel consists of an independent serial communication interface of the second microcontroller unit and an independent second 485 physical layer transceiver. Through the configuration of parallel channels, the total data throughput can be increased approximately linearly, provided microcontroller resources allow, to meet the application requirements for higher bandwidth. Each parallel physical bus can operate independently and be allocated and managed via upper-layer protocols.

[0037] The above are merely preferred embodiments of this utility model and are not intended to limit the scope of this utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A modular device bus system based on 485 serial port, characterized in that, include: Master equipment and slave equipment; The host device includes: a first microcontroller unit, a first 485 physical layer transceiver, and host-side auxiliary logic circuitry; the first microcontroller unit integrates a serial communication interface and a timer module; the data transceiver terminal of the first 485 physical layer transceiver is connected to the serial communication interface of the first microcontroller unit; the first input terminal of the host-side auxiliary logic circuitry is connected to the output terminal of the timer module of the first microcontroller unit; the second input terminal of the host-side auxiliary logic circuitry is connected to the transmitting terminal of the serial communication interface of the first microcontroller unit; and the output terminal of the host-side auxiliary logic circuitry is connected to the transmitting enable terminal of the first 485 physical layer transceiver. The slave device includes: a second microcontroller unit and a second 485 physical layer transceiver. The second microcontroller unit integrates a serial communication interface. The data transceiver terminals of the second 485 physical layer transceiver are connected to the serial communication interface of the second microcontroller unit. The second 485 physical layer transceiver includes a receive enable terminal and a transmit enable terminal. The first 485 physical layer transceiver and the second 485 physical layer transceiver are connected via differential signal lines.

2. The 485 serial port based modular device bus system of claim 1, wherein, The first microcontroller unit further includes a direct memory access controller, the data output channel of which is connected to the serial communication interface of the first microcontroller unit, and the trigger input channel of which is connected to the output of the timer module of the first microcontroller unit.

3. The 485 serial port based modular device bus system of claim 1, wherein, The host-side auxiliary logic circuit includes gate circuits and delay circuits. The gate circuits are connected to the first input terminal of the host-side auxiliary logic circuit, the input terminal of the delay circuit is connected to the second input terminal of the host-side auxiliary logic circuit, and the output terminals of the gate circuits and delay circuits are connected to the output terminal of the host-side auxiliary logic circuit.

4. The 485 serial based modular device bus system of claim 1, wherein, It also includes an inverter; the receive enable terminal of the second 485 physical layer transceiver is connected to the output terminal of the host-side auxiliary logic circuit via the inverter.

5. The 485 serial port based modular device bus system of claim 4, wherein, The second microcontroller unit further includes a clearing and sending flow control input pin, which is connected to the output of the inverter.

6. The 485 serial port based modular device bus system of claim 1, wherein, The transmit enable pin of the second 485 physical layer transceiver is connected to a preset output pin of the second microcontroller unit.

7. The 485 serial based modular device bus system of claim 1, wherein, Both the serial communication interface of the first microcontroller unit and the serial communication interface of the second microcontroller unit are TTL level interfaces.

8. The 485 serial based modular device bus system of claim 1, wherein, The host device includes at least two sets of parallel transmission channels, each transmission channel consisting of a serial communication interface of the first microcontroller unit, a first 485 physical layer transceiver, and host-side auxiliary logic circuitry; the slave device includes at least two sets of parallel receive / transmit channels, each receive / transmit channel consisting of a serial communication interface of the second microcontroller unit and a second 485 physical layer transceiver.

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