Operational amplifier circuit

Abstract

The utility model discloses an operational amplifier circuit, which comprises a rail-to-rail input stage and a switching circuit, the rail-to-rail input stage comprises a P-type transistor pair, an N-type transistor pair, a first current unit and a second current unit, the switching circuit comprises a first transistor and a bias circuit, and the first current unit is connected with the first end of the P-type transistor pair and the first end of the first transistor so as to provide first bias voltage for the first end of the first transistor; the bias circuit is connected with the control end of the first transistor to provide second bias voltage for the control end of the first transistor, the first end of the N-type transistor pair is connected with the second current unit, and the second end of the first transistor is connected with the second current unit to adjust current on the second current unit. According to the operational amplifier circuit, different transistor pairs work when the input voltage is close to the upper limit and the lower limit of a power supply by using the switching circuit, and the input rail-to-rail characteristic is realized, so that the complexity of the circuit is reduced, and the common-mode switching transition interval is reduced.

Description

Technical Field

[0001] This utility model belongs to the field of integrated circuit technology, and specifically relates to an operational amplifier circuit. Background Technology

[0002] In operational amplifiers, for certain special applications, it is required that the input common-mode voltage of the op-amp can be from the positive supply voltage to the negative supply voltage, that is, it can be rail to rail input (RRI). However, achieving rail to rail input is more complex than rail to rail output and often requires special methods to handle it. It is usually achieved through a folded cascode structure.

[0003] Existing technologies often achieve this by connecting a set of PMOS input transistors and a set of NMOS input transistors in parallel and then folding them into a common-source, common-gate configuration. When the input common-mode voltage is high (close to the upper limit of the power supply voltage), the NMOS input pair is turned on; when the input common-mode voltage is low (close to the lower limit of the power supply voltage), the PMOS input pair is turned on. However, when the input common-mode voltage is half of the power supply voltage, both the PMOS and NMOS differential pairs are turned on simultaneously. This causes the op-amp's transconductance, stability, and offset voltage to fluctuate significantly with the input common-mode voltage, generally requiring additional methods to handle this, such as a 3X current mirror (a current mirror magnified by 3 times) or a trim (calibration) circuit. However, for high-voltage op-amps, these methods are all quite complex.

[0004] The information disclosed in this background section is intended only to enhance the understanding of the overall background of this utility model and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Utility Model Content

[0005] The purpose of this invention is to provide an operational amplifier circuit that can ensure that its transconductance, offset voltage, etc., remain stable with the input common-mode voltage.

[0006] To achieve the above objectives, a specific embodiment of this utility model provides the following technical solution: an operational amplifier circuit, including a rail-to-rail input stage and a switching circuit; the rail-to-rail input stage includes a P-type transistor pair, an N-type transistor pair, a first current unit, and a second current unit; the switching circuit includes a first transistor and a bias circuit; the first current unit is connected to a first terminal of the P-type transistor pair and a first terminal of the first transistor to provide a first bias voltage to the first terminal of the first transistor; the bias circuit is connected to a control terminal of the first transistor to provide a second bias voltage to the control terminal of the first transistor; the first terminal of the N-type transistor pair is connected to the second current unit; and the second terminal of the first transistor is connected to the second current unit to adjust the current in the second current unit.

[0007] In one or more embodiments of the present invention, the bias circuit includes a third current unit, a second transistor, and a third transistor. The first terminal of the second transistor is connected to the power supply voltage, the control terminal of the second transistor is connected to the first terminal of the third transistor, and the second terminal of the second transistor is connected to the control terminal of the third transistor, the third current unit, and the control terminal of the first transistor.

[0008] In one or more embodiments of the present invention, the bias circuit further includes a first resistor, a first end of which is connected to a power supply voltage, and a second end of which is connected to a first end of a second transistor.

[0009] In one or more embodiments of this utility model, the first transistor, the second transistor, and the third transistor are triodes.

[0010] In one or more embodiments of the present invention, the bias circuit includes a fourth transistor and a fourth current unit. The first terminal of the fourth transistor is connected to the power supply voltage, and the control terminal of the fourth transistor is connected to the second terminal of the fourth transistor, the fourth current unit, and the control terminal of the first transistor.

[0011] In one or more embodiments of the present invention, the bias circuit further includes a second resistor, the first end of which is connected to the power supply voltage, and the second end of which is connected to the first end of the fourth transistor.

[0012] In one or more embodiments of this utility model, the first transistor and the fourth transistor are MOS transistors.

[0013] In one or more embodiments of the present invention, the second current unit includes a first current mirror, which is connected to a first terminal of an N-type transistor pair and a second terminal of the first transistor.

[0014] In one or more embodiments of this utility model, the rail-to-rail input stage further includes a second current mirror and a third current mirror, the two second terminals of the N-type transistor pair are respectively connected to the second current mirror and the third current mirror, and the second current mirror and the third current mirror are simultaneously connected to the two second terminals of the P-type transistor pair.

[0015] In one or more embodiments of the present invention, the P-type transistor pair includes a pair of PNP transistors, and the N-type transistor pair includes a pair of NPN transistors.

[0016] Compared with existing technologies, the operational amplifier circuit of this invention solves the problem that existing rail-to-rail operational amplifiers often require relatively complex means (such as 3X current mirrors, trim circuits, etc.) to achieve rail-to-rail characteristics, especially for high-voltage operational amplifiers with high complexity, by using P-type transistor pairs and N-type transistor pairs in conjunction with a switching circuit. This allows different transistor pairs to operate when the input voltage is close to the upper and lower limits of the power supply, thereby achieving rail-to-rail characteristics, reducing circuit complexity and reducing the common-mode switching transition range. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a circuit diagram of the operational amplifier circuit in Embodiment 1 of this utility model.

[0019] Figure 2 This is a circuit diagram of the operational amplifier circuit in Embodiment 2 of this utility model. Detailed Implementation

[0020] To enable those skilled in the art to better understand the technical solutions of this utility model, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this utility model.

[0021] The terms "coupled," "connected," or "linked" in this specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in utility models, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0022] In the detailed description of this specification, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein exemplary embodiments are shown by way of example that may be implemented. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this application. Therefore, the following detailed description should not be considered limiting.

[0023] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0024] For the purposes of this application, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this application, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0025] Various components and devices may be referred to or shown in the singular (e.g., “MOS transistor”, “transistor”, “switch”, etc.) in this document, but only for the convenience of discussion, and any element referred to in the singular may include multiple such elements as taught herein.

[0026] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used in relation to embodiments of this application are synonymous.

[0027] Example 1

[0028] like Figure 1 As shown, an operational amplifier circuit in one embodiment of the present invention includes a rail-to-rail input stage, a switching circuit 10, and a subsequent stage circuit.

[0029] The rail-to-rail input stage includes a pair of P-type transistors, a pair of N-type transistors, a first current unit I1, and a second current unit. The switching circuit 10 includes a first transistor Q1 and a bias circuit.

[0030] The first terminal of the first current unit I1 is connected to the first terminal of the P-type transistor pair and the first terminal of the first transistor Q1 to provide a first bias voltage V1 to the first terminal of the first transistor Q1. The second terminal of the first current unit I1 is connected to the power supply voltage VCC. The bias circuit is connected to the control terminal of the first transistor Q1 to provide a second bias voltage V2 to the control terminal of the first transistor Q1. The first terminal of the N-type transistor pair is connected to the second current unit. The second terminal of the first transistor Q1 is connected to the second current unit to adjust the current on the second current unit.

[0031] The second current unit includes a first current mirror, which is connected to the first terminal of the N-type transistor pair and the second terminal of the first transistor Q1.

[0032] The rail-to-rail input stage also includes a second current mirror and a third current mirror. The two second terminals of the N-type transistor pair are connected to the second current mirror and the third current mirror, respectively. The second current mirror and the third current mirror are also connected to the two second terminals of the P-type transistor pair, respectively.

[0033] A P-type transistor pair includes a pair of PNP transistors, namely a first PNP transistor Qp1 and a second PNP transistor Qp2. The first terminal of the first PNP transistor Qp1 and the first terminal of the second PNP transistor Qp2 are connected to form the first terminal of the P-type transistor pair. The second terminal of the first PNP transistor Qp1 and the second terminal of the second PNP transistor Qp2 form the two second terminals of the P-type transistor pair. The control terminal of the first PNP transistor Qp1 and the control terminal of the second PNP transistor Qp2 form the two control terminals of the P-type transistor pair to receive differential input voltage.

[0034] An N-type transistor pair includes a pair of NPN transistors, namely a first NPN transistor Qn1 and a second NPN transistor Qn2. The first terminal of the first NPN transistor Qn1 and the first terminal of the second NPN transistor Qn2 are connected to form the first terminal of the N-type transistor pair. The second terminal of the first NPN transistor Qn1 and the second terminal of the second NPN transistor Qn2 form the two second terminals of the N-type transistor pair. The control terminal of the first NPN transistor Qn1 and the control terminal of the second NPN transistor Qn2 form the two control terminals of the N-type transistor pair to receive differential input voltage.

[0035] like Figure 1As shown, the first current mirror includes a first image transistor M1 and a second image transistor M2. The second end of the first image transistor M1 is connected to the control terminal of the first image transistor M1, the second end of the first transistor Q1, and the control terminal of the second image transistor M2. The second end of the second image transistor M2 is connected to the first end of the first NPN transistor Qn1 and the first end of the second NPN transistor Qn2. The first ends of the first image transistor M1 and the first ends of the second image transistor M2 are connected to the ground voltage VEE.

[0036] The second current mirror includes a third image transistor Q5 and a fourth image transistor Q6. The second terminal of the third image transistor Q5 is connected to the control terminal of the third image transistor Q5, the second terminal of the first NPN transistor Qn1, and the control terminal of the fourth image transistor Q6. The second terminal of the fourth image transistor Q6 is connected to the second terminal of the second PNP transistor Qp2. The first terminals of the third image transistor Q5 and the first terminals of the fourth image transistor Q6 are connected to the power supply voltage VCC.

[0037] The third current mirror includes a fifth image transistor Q7 and a sixth transistor Q8. The second terminal of the sixth transistor Q8 is connected to the control terminal of the sixth transistor Q8, the second terminal of the second NPN transistor Qn2, and the control terminal of the fifth image transistor Q7. The second terminal of the fifth image transistor Q7 is connected to the second terminal of the first PNP transistor Qp1. The first terminal of the fifth image transistor Q7 and the first terminal of the sixth transistor Q8 are connected to the power supply voltage VCC.

[0038] The second terminal of the first PNP transistor Qp1 and the second terminal of the second PNP transistor Qp2 are connected to the subsequent circuit. In one embodiment, the subsequent circuit can be a folded common-source common-gate circuit.

[0039] like Figure 1 As shown, the bias circuit includes a first resistor R1, a third current unit I3, a second transistor Q2, and a third transistor Q3. The first terminal of the first resistor R1 is connected to the power supply voltage VCC. The second terminal of the first resistor R1 is connected to the first terminal of the second transistor Q2. The control terminal of the second transistor Q2 is connected to the first terminal of the third transistor Q3. The second terminal of the third transistor Q3 is connected to the ground voltage VEE. The second terminal of the second transistor Q2 is connected to the control terminal of the third transistor Q3, the first terminal of the third current unit I3, and the control terminal of the first transistor Q1. The second terminal of the third current unit I3 is connected to the ground voltage VEE. In some embodiments, the first resistor R1 may be omitted.

[0040] In one embodiment, the first mirror transistor M1 and the second mirror transistor M2 are N-channel MOS transistors. The first end of the first mirror transistor M1 and the first end of the second mirror transistor M2 are the sources, the second end of the first mirror transistor M1 and the second end of the second mirror transistor M2 are the drains, and the control terminal of the first mirror transistor M1 and the control terminal of the second mirror transistor M2 are the gates.

[0041] The first transistor Q1, the second transistor Q2, the third transistor Q3, the third image transistor Q5, the fourth image transistor Q6, the fifth image transistor Q7, and the sixth transistor Q8 are PNP transistors. The first terminal of the first PNP transistor Qp1, the first terminal of the second PNP transistor Qp2, the first terminal of the first NPN transistor Qn1, the first terminal of the second NPN transistor Qn2, the first terminal of the first transistor Q1, the first terminal of the second transistor Q2, the first terminal of the third transistor Q3, the first terminal of the third image transistor Q5, the first terminal of the fourth image transistor Q6, the first terminal of the fifth image transistor Q7, and the first terminal of the sixth transistor Q8 are emitters. The second terminals of the first PNP transistor Qp1, the second terminal of the second PNP transistor Qp2, the second terminal of the first NPN transistor Qn1, the second terminal of the second NPN transistor Qn2, and the first terminal of the first transistor Q1 are emitters. The second terminal of the second transistor Q2, the second terminal of the third transistor Q3, the second terminal of the third image transistor Q5, the second terminal of the fourth image transistor Q6, the second terminal of the fifth image transistor Q7, and the second terminal of the sixth transistor Q8 are collectors. The control terminals of the first PNP transistor Qp1, the second PNP transistor Qp2, the first NPN transistor Qn1, the second NPN transistor Qn2, the first transistor Q1, the second transistor Q2, the third transistor Q3, the third image transistor Q5, the fourth image transistor Q6, the fifth image transistor Q7, and the second terminal of the sixth transistor Q8 are bases.

[0042] like Figure 1 As shown, the first bias voltage V1 is clamped by the emitter-junction voltage (voltage between emitter and base) of the first PNP transistor Qp1 or the second PNP transistor Qp2, and is approximately higher than the input voltage by an emitter-junction voltage |VBE|. The second bias voltage V2 is approximately the power supply voltage VCC minus the emitter-junction voltage of the second transistor Q2, the emitter-junction voltage of the third transistor Q3 (assuming that the emitter-junction voltages of all transistors are equal to |VBE|), and the voltage drop VR1 across the first resistor R1, i.e., VCC - 2|VBE| - VR1.

[0043] When the input voltage is low, the first bias voltage V1 decreases, the emitter junction of the first transistor Q1 is reverse biased (|VBE| is approximately less than 0.7V), the first transistor Q1 is turned off, and the current in the first current unit I1 flows into the P-type transistor pair, at which point the P-type transistor pair is working. However, as the input voltage gradually increases, the first bias voltage V1 increases, causing the emitter junction of the first transistor Q1 to be forward biased (|VBE| is greater than 0.7V), the first transistor Q1 turns on, and the current in the first current unit I1 begins to shunt to the first transistor Q1 and the first image transistor M1. At this time, the P-type transistor pair and the N-type transistor pair will work simultaneously. Since the current in a transistor follows an exponential relationship, i.e.:

[0044] I = I0 * e^(|VBE| / Vt), where I0 is the saturation current, |VBE| is the emitter junction voltage, and Vt = KT / q, where K is the Boltzmann constant, T is the temperature, and q is the electron charge.

[0045] Therefore, when the input voltage increases slightly (approximately several hundred millivolts), the current of the first current unit I1 will all flow into the first image transistor M1 through the first transistor Q1. At this time, the P-type transistor pair is turned off, so only the N-type transistor pair works, completing the switching while the transition range is also small.

[0046] Alternatively, the common-mode switching point can be changed by altering the value of the first resistor R1 and the magnitude of the second bias voltage V2.

[0047] In summary, the solution in this embodiment can achieve rail-to-rail input while reducing circuit complexity and exhibiting good stability.

[0048] This invention also provides a chip, including the above-described operational amplifier circuit.

[0049] Example 2

[0050] like Figure 2 As shown, based on Embodiment 1, the switching circuit 10 is modified. In one embodiment, the first transistor Q1 is a P-channel MOSFET, and the bias circuit includes a second resistor R2, a fourth transistor Q4, and a fourth current unit I4. The first terminal of the second resistor R2 is connected to the power supply voltage VCC, and the second terminal of the second resistor R2 is connected to the first terminal of the fourth transistor Q4. The control terminal of the fourth transistor Q4 is connected to the second terminal of the fourth transistor Q4, the first terminal of the fourth current unit I4, and the control terminal of the first transistor Q1. The second terminal of the fourth current unit I4 is connected to the ground voltage VEE. In other embodiments, the fourth transistor Q4 is a P-channel MOSFET.

[0051] In one embodiment, the fourth transistor Q4 is a P-channel MOS transistor, the first terminal of the first transistor Q1 and the first terminal of the fourth transistor Q4 are the source, the second terminal of the first transistor Q1 and the second terminal of the fourth transistor Q4 are the drain, and the control terminal of the first transistor Q1 and the control terminal of the fourth transistor Q4 are the gate.

[0052] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0053] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. An operational amplifier circuit, characterized in that, The system includes a rail-to-rail input stage and a switching circuit. The rail-to-rail input stage includes a pair of P-type transistors, a pair of N-type transistors, a first current unit, and a second current unit. The switching circuit includes a first transistor and a bias circuit. The first current unit is connected to a first terminal of the P-type transistor pair and a first terminal of the first transistor to provide a first bias voltage to the first terminal of the first transistor. The bias circuit is connected to a control terminal of the first transistor to provide a second bias voltage to the control terminal of the first transistor. The first terminal of the N-type transistor pair is connected to the second current unit, and the second terminal of the first transistor is connected to the second current unit to adjust the current in the second current unit.

2. The operational amplifier circuit according to claim 1, characterized in that, The bias circuit includes a third current unit, a second transistor, and a third transistor. The first terminal of the second transistor is connected to the power supply voltage. The control terminal of the second transistor is connected to the first terminal of the third transistor. The second terminal of the second transistor is connected to the control terminal of the third transistor, the third current unit, and the control terminal of the first transistor.

3. The operational amplifier circuit according to claim 2, characterized in that, The bias circuit further includes a first resistor, the first end of which is connected to the power supply voltage, and the second end of which is connected to the first end of the second transistor.

4. The operational amplifier circuit according to claim 2, characterized in that, The first transistor, the second transistor, and the third transistor are triodes.

5. The operational amplifier circuit according to claim 1, characterized in that, The bias circuit includes a fourth transistor and a fourth current unit. The first terminal of the fourth transistor is connected to the power supply voltage, and the control terminal of the fourth transistor is connected to the second terminal of the fourth transistor, the fourth current unit, and the control terminal of the first transistor.

6. The operational amplifier circuit according to claim 5, characterized in that, The bias circuit further includes a second resistor, the first end of which is connected to the power supply voltage, and the second end of which is connected to the first end of the fourth transistor.

7. The operational amplifier circuit according to claim 5, characterized in that, The first transistor and the fourth transistor are MOS transistors.

8. The operational amplifier circuit according to claim 1, characterized in that, The second current unit includes a first current mirror, which is connected to a first terminal of an N-type transistor pair and a second terminal of the first transistor.

9. The operational amplifier circuit according to claim 1, characterized in that, The rail-to-rail input stage also includes a second current mirror and a third current mirror. The two second terminals of the N-type transistor pair are respectively connected to the second current mirror and the third current mirror. The second current mirror and the third current mirror are also respectively connected to the two second terminals of the P-type transistor pair.

10. The operational amplifier circuit according to claim 1, characterized in that, The P-type transistor pair includes a pair of PNP transistors, and the N-type transistor pair includes a pair of NPN transistors.

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