Sensor signal acquisition device and sensor test system

Abstract

The utility model provides a sensor signal acquisition device and a sensor test system, and the sensor signal acquisition device comprises a PCIe communication unit, an FPGA processing unit, and at least one signal channel connected with the FPGA processing unit. The PCIe communication unit is used for establishing connection between the sensor signal acquisition device and an upper computer, the FPGA processing unit is used for receiving configuration data of the upper computer, each signal channel is used for transmitting acquisition signals of a plurality of tested sensors to the FPGA processing unit, and the plurality of tested sensors corresponding to each signal channel are connected in series through an A2B bus. The FPGA processing unit controls the plurality of tested sensors corresponding to each signal channel to transmit acquisition signals to the FPGA processing unit in a switching manner based on the configuration data, the FPGA processing unit converts the acquisition signals into test data, and the test data of the plurality of tested sensors are transmitted to an upper computer through the PCIe communication unit.

Description

Technical Field

[0001] This utility model relates to the field of signal acquisition technology, and in particular to a sensor signal acquisition device and a sensor testing system. Background Technology

[0002] In modern society, vehicles are not only a means of transportation but also a private space where people seek comfort. To make the driving experience more comfortable, quiet, and intelligent, various high-performance sensors are deployed on different mechanical structures of vehicles. For example, the application of high-performance triaxial sensors helps realize active road noise reduction technology. Specifically, triaxial sensors are usually installed at the wheel wells of the vehicle to collect vibration data from the ground. This vibration data is then transmitted to an audio DSP (Digital Signal Processing) chip via an A2B bus (Automotive Audio Bus). The DSP chip calculates audio data with the same frequency but opposite amplitude as the vibration data within a specified time and plays it through the vehicle's amplifier, thereby achieving noise cancellation. It is evident that the low latency and low noise performance of sensors are crucial to the application of noise reduction systems; therefore, functional testing of sensors before they leave the factory is essential. Using real-vehicle testing to verify the various functional indicators of sensors is a relatively straightforward approach. The test results obtained in this way are relatively accurate and more intuitive. However, real-vehicle testing is costly and inefficient. Utility Model Content

[0003] This invention aims to at least partially solve one of the technical problems in related technologies. To this end, this invention proposes a sensor signal acquisition device and a sensor testing system. The sensor testing system is designed to test the relevant functions of sensors. In this testing system, the sensor signal acquisition device establishes an effective connection with the sensor under test by fully simulating the data interaction behavior between the vehicle's DSP chip and the sensor, acquiring the data collected by the sensor, thereby enabling the sensor testing system of this invention to operate smoothly. The sensor signal acquisition device and sensor testing system of this invention have a simple structure and higher testing efficiency, and are intended to replace existing real-vehicle testing methods.

[0004] To achieve the above objectives, this utility model proposes a sensor signal acquisition device, comprising: a PCIe communication unit and an FPGA processing unit, and at least one signal channel connected to the FPGA processing unit; the PCIe communication unit is used to establish a connection between the sensor signal acquisition device and a host computer; the FPGA processing unit is used to receive configuration data from the host computer; each signal channel is used to transmit acquisition signals from multiple sensors under test to the FPGA processing unit; and the multiple sensors under test corresponding to each signal channel are connected in series via an A2B bus; the FPGA processing unit controls the multiple sensors under test corresponding to each signal channel to switchly transmit the acquisition signals to the FPGA processing unit based on the configuration data; the FPGA processing unit converts the acquisition signals into test data and transmits the test data of the multiple sensors under test to the host computer via the PCIe communication unit.

[0005] Based on the above embodiments, the sensor signal acquisition device of this utility model can also have the following embodiments:

[0006] In one possible implementation, each signal channel includes a switching unit; the switching unit is connected to the sensor under test and is used to switch between multiple sensors under test so that the acquisition signal of any one of the sensors under test can be transmitted to the FPGA processing unit through the signal channel.

[0007] In one possible implementation, each signal channel includes an A2B communication unit; the A2B communication unit is connected to the FPGA processing unit and the switching unit respectively, and the A2B communication unit is used to receive I2C data sent by the FPGA processing unit based on the configuration data, and control the switching unit to switch between multiple sensors under test according to the I2C data, so that the acquisition signal of any one of the sensors under test can be transmitted to the FPGA processing unit through the signal channel.

[0008] In one possible implementation, each signal channel includes a signal processing unit; the signal processing unit is connected to the FPGA processing unit and the A2B communication unit respectively, and is used to process the raw signal collected by any one of the sensors under test to obtain the collected signal, and transmit the collected signal to the FPGA processing unit.

[0009] In one possible implementation, the A2B communication unit includes an I2C module and an I2S module; the I2C module is communicatively connected to the FPGA processing unit and is used to receive and store the I2C data; the I2S module is communicatively connected to the sensor under test and is used to receive and transmit the raw signals collected by the sensor under test.

[0010] In one possible implementation, the signal processing unit includes: a first amplification module, a bandpass filter, and a voltage conversion module; the first amplification module is connected to the A2B communication unit and is used to amplify the raw signal acquired by the sensor under test to generate an amplified signal; the bandpass filter is connected to the first amplification module and is used to filter the amplified signal to generate a filtered signal; the voltage conversion module is connected to both the bandpass filter and the FPGA processing unit and is used to convert the filtered signal into the acquired signal according to a preset threshold voltage.

[0011] In one possible implementation, the first amplification module includes: a first operational amplifier, a first resistor, and a second resistor; the non-inverting input of the first operational amplifier is connected to the A2B communication unit for receiving the raw signal acquired by the sensor under test; the inverting input of the first operational amplifier is connected to the first end of the second resistor; the output of the first operational amplifier is connected to the input of the bandpass filter; the first end of the first resistor is connected to the output of the first operational amplifier; the second end of the first resistor is connected to the inverting input of the first operational amplifier; and the second end of the second resistor is grounded.

[0012] In one possible implementation, the voltage conversion module includes: a first diode, a third resistor, and a voltage comparator; a first terminal of the first diode is connected to the output terminal of the bandpass filter; a first terminal of the third resistor is connected to the second terminal of the first diode, and the second terminal of the third resistor is grounded; the non-inverting input terminal of the voltage comparator is connected to the second terminal of the first diode, the inverting input terminal of the voltage comparator is used to input the preset threshold voltage, and the output terminal of the voltage comparator is connected to the FPGA processing unit.

[0013] In one possible implementation, the FPGA processing unit includes: an A2B protocol conversion module and a storage module; the A2B protocol conversion module is used to parse and encapsulate the A2B data frames of the acquired signal to obtain the test data; the storage module is used to store the configuration data of the host computer for the FPGA processing unit.

[0014] As can be seen, the sensor signal acquisition device of this utility model embodiment can realize the batch testing of sensors. Multiple signal channels can be connected to multiple sensors under test through the A2B bus. The switching unit in each signal channel can switch multiple sensors under test to transmit data to the FPGA processing unit under the control of the FPGA processing unit, thereby realizing the batch testing of sensors.

[0015] To achieve the above objectives, this utility model also proposes a sensor testing system, comprising: a sensor under test, a host computer, and a sensor signal acquisition device as described in any of the preceding embodiments; the sensor signal acquisition device receives configuration data from the host computer, and acquires the acquisition signals of the sensor under test in a switching manner according to the configuration data, and parses and encapsulates the acquisition signals into test data of the sensor under test and sends it to the host computer.

[0016] In summary, the sensor signal acquisition device and sensor testing system of this utility model embodiment can realize batch testing of sensors. At the same time, the switching unit also saves the number of signal channels, which helps to reduce the manufacturing cost and size of the sensor signal acquisition device, thereby reducing the implementation cost of the sensor testing system of this utility model embodiment.

[0017] Additional aspects and advantages of this invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of a sensor testing system according to some embodiments of the present invention;

[0019] Figure 2 This is a schematic diagram of the structure of a sensor signal acquisition device according to some embodiments of the present invention;

[0020] Figure 3 This is a schematic diagram of the sensor signal acquisition device and its signal channel according to some embodiments of the present invention;

[0021] Figure 4 This is a schematic diagram of the FPGA processing unit, signal processing unit, and A2B communication unit of the sensor signal acquisition device according to some embodiments of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0023] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this utility model should have the ordinary meaning understood by those skilled in the art to which this utility model pertains. The terms "first," "second," and similar terms used in the embodiments of this utility model do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connection" or "linkage" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0024] As described in the background section, in the field of active noise reduction technology for vehicle road noise, triaxial sensors are typically installed at the wheel wells of vehicles to collect vibration data from the ground. This collected vibration data is transmitted to an audio DSP chip via an A2B bus. It is evident that the sensor's low latency and low noise performance are crucial to the application of the noise reduction system. While real-vehicle testing provides relatively intuitive results for verifying sensor functionality, this method is costly and inefficient, making it unsuitable for large-scale sensor testing.

[0025] Based on the above, this utility model provides a sensor signal acquisition device and a sensor testing system, which can replace the actual vehicle and scene testing methods, realize batch testing of sensors, and thus improve testing efficiency.

[0026] Please see Figures 1 to 4 This is a schematic diagram of the sensor testing system 1000 and the sensor signal acquisition device 200 according to an embodiment of the present invention.

[0027] like Figure 1 As shown, the sensor testing system 1000 includes: a sensor under test, a host computer 100, and a sensor signal acquisition device 200. The sensor signal acquisition device 200 is connected to both the host computer 100 and the sensor under test. The sensor signal acquisition device 200 can connect to multiple sensors under test. The sensor signal acquisition device 200 receives configuration data from the host computer 100, and according to the received configuration data, switches between acquiring the acquisition signals of the sensors under test. It then parses and encapsulates the acquired signals, sequentially acquiring test data from multiple sensors under test. The sensor signal acquisition device 200 then sends this test data from the sensors under test to the host computer for subsequent sensor testing.

[0028] The sensor signal acquisition device 200 of this embodiment may include: a PCIe communication unit 210 and an FPGA processing unit 220, as well as at least one signal channel connected to the FPGA processing unit 220. For example... Figure 2 As shown, the PCIe communication unit 210 is used to establish a connection between the sensor signal acquisition device 200 and the host computer 100, and the FPGA processing unit 220 is used to receive the configuration data from the host computer 100. Each signal channel is used to transmit the acquisition signals of multiple sensors under test to the FPGA processing unit 220, and the multiple sensors under test corresponding to each signal channel are connected in series via an A2B bus.

[0029] The A2B bus is a high-bandwidth, bidirectional digital audio bus designed for next-generation audio and acoustic applications. The A2B protocol is a protocol developed by Analog Devices (ADI). In automotive design, achieving high-fidelity audio traditionally requires numerous expensive and heavy cables. However, A2B transceivers enable the distribution of audio and control data, along with clock and power, through a single low-cost, unshielded twisted-pair cable. The A2B bus daisy-chains multiple remote sensors for different applications, significantly reducing the weight of heavy analog cabling and existing cable harnesses. This contributes to improved vehicle fuel efficiency, reduced overall design costs and complexity, and expands microphone connectivity use cases such as road noise cancellation, in-vehicle communication, and autonomous driving. In practical applications, A2B can transmit I2S / TDM / PDM data, I2C control information, clock, and power using a single two-wire UTP cable. The distance between nodes can reach 15 meters, and the distance along the entire daisy chain can reach 40 meters. A2B can function as its own network, used with embedded subnets, or as an endpoint transmission bus in conjunction with other longer-range protocols.

[0030] The FPGA processing unit 220 of the sensor signal acquisition device 200 of this utility model embodiment controls multiple sensors under test corresponding to each signal channel to switchly transmit the acquired signals to the FPGA processing unit 220 based on the configuration data. The FPGA processing unit 220 converts the acquired signals into test data and transmits the test data of multiple sensors under test to the host computer 100 through the PCIe communication unit 210, thereby completing the test of multiple sensors under test and improving the test efficiency.

[0031] Please see Figure 3 Each signal channel of the sensor signal acquisition device 200 in this embodiment of the present invention includes: a switching unit 250, an A2B communication unit 240, and a signal processing unit 230.

[0032] The switching unit 250 is connected to the sensor under test and is used to switch between multiple sensors under test so that the acquired signal of any one sensor can be transmitted to the FPGA processing unit 220 through its corresponding signal channel. Therefore, the switching unit 250 facilitates batch testing of sensors and also saves on the number of signal channels, helping to reduce the manufacturing cost and size of the sensor signal acquisition device 200. The A2B communication unit 240 is connected to both the FPGA processing unit 220 and the switching unit 250. The A2B communication unit 240 receives I2C data sent by the FPGA processing unit 220 based on the aforementioned configuration data, and then controls the switching unit 250 to switch between multiple sensors under test according to the I2C data, so that the acquired signal of any one sensor can be transmitted to the FPGA processing unit 220 through its corresponding signal channel. The signal processing unit 230 is connected to both the FPGA processing unit 220 and the A2B communication unit 240, and is used to process the raw signal acquired by any one sensor under test to obtain the acquired signal, and then transmit the acquired signal to the FPGA processing unit 220.

[0033] Please see Figure 4 The A2B communication unit 240 includes an I2C module 241 and an I2S module 242. The I2C module 241 is communicatively connected to the FPGA processing unit 220 and is used to receive and store the aforementioned I2C data. The I2S module is communicatively connected to the sensor under test and is used to receive and transmit the raw signals collected by the sensor under test, and send the raw signals collected by each sensor under test to the signal processing unit 230.

[0034] like Figure 4 As shown, the signal processing unit 230 of the sensor signal acquisition device 200 of this utility model embodiment includes: a first amplification module 232, a bandpass filter 231, and a voltage conversion module 233.

[0035] The first amplification module 232 is connected to the A2B communication unit 240 and is used to amplify the raw signal acquired by the sensor under test to generate an amplified signal. The bandpass filter 231 is connected to the first amplification module 232 and is used to filter the amplified signal to generate a filtered signal. The voltage conversion module 233 is connected to both the bandpass filter 231 and the FPGA processing unit 220, and is used to convert the filtered signal into an acquired signal according to a preset threshold voltage VREF. Specifically, the raw signal acquired by the sensor under test is relatively weak and accompanied by noise; therefore, it needs to be amplified by the first amplification module 232 first, and then filtered by the bandpass filter 231. The voltage conversion module 233 converts the filtered signal into an acquired signal that can be processed by the FPGA processing unit 220 according to the preset threshold voltage VREF.

[0036] It should be noted that the cutoff frequencies of the high-frequency band and low-frequency band of the bandpass filter 231 can be set according to actual conditions. As can be seen in the above embodiment, since the original signal acquired by the sensor under test is relatively weak and accompanied by noise, it is necessary to amplify and filter the original signal through the first amplification module 232 and the bandpass filter 231 to obtain a filtered signal. The voltage conversion module 233 converts the filtered signal into an acquisition signal that can be recognized by the FPGA processing unit 220, so that the FPGA processing unit 220 can perform subsequent operations based on the acquisition signal.

[0037] For example, the first amplification module 232 includes: a first operational amplifier OP1, a first resistor R1, and a second resistor R2. The non-inverting input of the first operational amplifier OP1 is connected to the A2B communication unit 240 for receiving the raw signal acquired by the sensor under test. The inverting input of the first operational amplifier OP1 is connected to the first end of the second resistor R2. The output of the first operational amplifier OP1 is connected to the input of the bandpass filter 231. The first end of the first resistor R1 is connected to the output of the first operational amplifier OP1, and the second end of the first resistor R1 is connected to the inverting input of the first operational amplifier OP1. The second end of the second resistor R2 is grounded. The voltage conversion module 233 includes: a first diode D1, a third resistor R3, and a voltage comparator OP2. The first terminal of the first diode D1 is connected to the output terminal of the bandpass filter 231. The first terminal of the third resistor R3 is connected to the second terminal of the first diode D1, and the second terminal of the third resistor R3 is grounded. The non-inverting input terminal of the voltage comparator OP2 is connected to the second terminal of the first diode D1, the inverting input terminal of the voltage comparator OP2 is used to input a preset threshold voltage VREF, and the output terminal of the voltage comparator OP2 is connected to the FPGA processing unit 220. Specifically, the amplification factor of the first amplification module 232 is determined based on the resistance values ​​of the first resistor R1 and the second resistor R2. When the filtered signal output by the bandpass filter 231 is a negative voltage signal, the first diode D1 ensures unidirectional conduction between the bandpass filter 231 and the voltage comparator OP2. The voltage comparator OP2 compares the level of the input signal with its preset threshold voltage VREF and outputs a sampled signal that can be processed by the FPGA processing unit 220 based on the comparison result. For example, when the level of the input signal is higher than the preset threshold voltage, the voltage comparator OP2 outputs a high level, and when the level of the input signal is lower than the threshold voltage, the voltage comparator OP2 outputs a low level.

[0038] like Figure 4As shown, the FPGA processing unit 220 of the sensor signal acquisition device 200 in this embodiment includes an A2B protocol conversion module 221 and a storage module 222. The A2B protocol conversion module 221 is used to parse and encapsulate the A2B data frames of the acquired signal to obtain test data; the storage module 222 is used to store the configuration data of the host computer for the FPGA processing unit 220. In practical applications, to achieve simultaneous sampling and transmission of each frame of data on all system nodes, A2B technology provides determinism and very low latency, less than 0.05ms. The A2B bus has a configurable frame rate of 44.1kHz or 48kHz and a bandwidth of up to 50Mbps. Another key design aspect of A2B technology is its ability to communicate audio and other data simultaneously with GPIO, meaning that terminal devices do not require a separate processor. Having multiple processors in a system increases the complexity of inter-processor communication. Driving the I / O of secondary terminal devices from a master device is a great simplification, reducing NRE, BOM, and long-term maintenance.

[0039] In summary, the sensor signal acquisition device of this embodiment enables batch testing of sensors. Multiple signal channels can be connected to multiple sensors under test via an A2B bus. The switching unit in each signal channel, under the control of the FPGA processing unit, allows multiple sensors under test to switchly transmit data to the FPGA processing unit, thereby achieving batch testing of sensors. The switching unit also saves on the number of signal channels, helping to reduce the manufacturing cost and size of the sensor signal acquisition device, and thus reducing the implementation cost of the sensor testing system of this embodiment.

[0040] Furthermore, although the circuit structure features of this invention are described in a specific combination in the accompanying drawings, this does not require or imply that the structure of this invention must be constructed in that combination, or that all the modules shown must be applied to achieve the desired result.

[0041] It should be understood that the various parts of this utility model can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0042] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this utility model should have the ordinary meaning understood by those skilled in the art to which this utility model pertains. The terms "first," "second," and similar words used in the embodiments of this utility model do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, without excluding other elements or objects. Terms such as "connection" or "linkage" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0043] While the spirit and principles of this invention have been described with reference to several specific embodiments, it should be understood that this invention is not limited to the disclosed specific embodiments, and the division of aspects does not imply that features in these aspects cannot be combined for benefit; such division is merely for ease of description. This invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. The scope of the appended claims is to be interpreted in the broadest sense, thereby encompassing all such modifications and equivalent structures and functions.

Claims

1. A sensor signal acquisition device, connected to a host computer, characterized in that, include: PCIe communication unit and FPGA processing unit, and at least one signal channel connected to the FPGA processing unit; The PCIe communication unit is used to establish a connection between the sensor signal acquisition device and the host computer. The FPGA processing unit is used to receive configuration data from the host computer. Each signal channel is used to transmit multiple acquisition signals from the sensors under test to the FPGA processing unit. Furthermore, the multiple sensors under test corresponding to each signal channel are connected in series via an A2B bus. Based on the configuration data, the FPGA processing unit controls the multiple sensors under test corresponding to each signal channel to switchly transmit the acquisition signals to the FPGA processing unit. The FPGA processing unit converts the acquisition signals into test data and transmits the test data of the multiple sensors under test to the host computer through the PCIe communication unit.

2. The sensor signal acquisition device according to claim 1, characterized in that, Each of the signal channels includes: a switching unit; The switching unit is connected to the sensor under test and is used to switch between multiple sensors under test so that the acquisition signal of any one of the sensors under test can be transmitted to the FPGA processing unit through the signal channel.

3. The sensor signal acquisition device according to claim 2, characterized in that, Each of the signal channels includes: an A2B communication unit; The A2B communication unit is connected to the FPGA processing unit and the switching unit respectively. The A2B communication unit is used to receive I2C data sent by the FPGA processing unit based on the configuration data, and control the switching unit to switch between multiple sensors under test according to the I2C data, so that the acquisition signal of any one of the sensors under test can be transmitted to the FPGA processing unit through the signal channel.

4. The sensor signal acquisition device according to claim 3, characterized in that, Each of the signal channels includes: a signal processing unit; The signal processing unit is connected to the FPGA processing unit and the A2B communication unit respectively, and is used to process the raw signal collected by any of the sensors under test to obtain the collected signal, and transmit the collected signal to the FPGA processing unit.

5. The sensor signal acquisition device according to claim 4, characterized in that, The A2B communication unit includes: an I2C module and an I2S module; The I2C module is communicatively connected to the FPGA processing unit and is used to receive and store the I2C data; The I2S module is communicatively connected to the sensor under test and is used to receive and transmit the raw signals collected by the sensor under test.

6. The sensor signal acquisition device according to claim 5, characterized in that, The signal processing unit includes: a first amplification module, a bandpass filter, and a voltage conversion module; The first amplification module is connected to the A2B communication unit and is used to amplify the raw signal collected by the sensor under test to generate an amplified signal. The bandpass filter is connected to the first amplification module and is used to filter the amplified signal to generate a filtered signal. The voltage conversion module is connected to the bandpass filter and the FPGA processing unit respectively, and is used to convert the filtered signal into the acquired signal according to a preset threshold voltage.

7. The sensor signal acquisition device according to claim 6, characterized in that, The first amplification module includes: a first operational amplifier, a first resistor, and a second resistor; The non-inverting input of the first operational amplifier is connected to the A2B communication unit to receive the raw signal collected by the sensor under test. The inverting input of the first operational amplifier is connected to the first end of the second resistor. The output of the first operational amplifier is connected to the input of the bandpass filter. The first end of the first resistor is connected to the output terminal of the first operational amplifier, and the second end of the first resistor is connected to the inverting input terminal of the first operational amplifier. The second terminal of the second resistor is grounded.

8. The sensor signal acquisition device according to claim 6, characterized in that, The voltage conversion module includes: a first diode, a third resistor, and a voltage comparator; The first terminal of the first diode is connected to the output terminal of the bandpass filter; The first end of the third resistor is connected to the second end of the first diode, and the second end of the third resistor is grounded; The non-inverting input of the voltage comparator is connected to the second terminal of the first diode, the inverting input of the voltage comparator is used to input the preset threshold voltage, and the output of the voltage comparator is connected to the FPGA processing unit.

9. The sensor signal acquisition device according to claim 1, characterized in that, The FPGA processing unit includes: an A2B protocol conversion module and a storage module; The A2B protocol conversion module is used to parse and encapsulate the A2B data frames of the acquired signal to obtain the test data; The storage module is used to store the configuration data of the host computer for the FPGA processing unit.

10. A sensor testing system, characterized in that, include: The sensor under test, the host computer, and the sensor signal acquisition device as described in any one of claims 1 to 9; The sensor signal acquisition device receives configuration data from the host computer, and switches between acquiring the acquisition signals of the sensor under test according to the configuration data, and parses and encapsulates the acquisition signals into test data of the sensor under test and sends it to the host computer.

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