Environmental event structuring device based on adaptive baseline tracking

Abstract

The utility model discloses an environmental event structuring device based on adaptive baseline tracking. The device comprises a voltage follower, an operational amplifier, an integral switching network, an AND gate, a timing pulse generator, an inverter and a reset switch, an input signal is compared with a baseline voltage generated by the integral network through the operational amplifier, and the output of the baseline voltage and a timing pulse are subjected to logical operation in the AND gate to generate a self-adaptive control signal; after phase reversal by the phase inverter, the reset switch is controlled to quickly discharge the integrating capacitor, and the integrating switching network is controlled to switch the integrating time constant, so that closed-loop control is formed, and slow baseline tracking in a quiet period and quick reset response in an event period are realized; the device outputs three analog signals of baseline voltage, peak voltage and pulse width voltage in real time through closed-loop control of a hardware circuit, and original signal transmission load is reduced from the source.

Description

Technical Field

[0001] This utility model relates to the field of IoT sensing layer hardware technology, and in particular to an environmental event structuring hardware device for the front-end acquisition stage of big data applications. It is used to convert continuous analog signals generated by environmental sensors into a combination of event feature signals containing multi-dimensional feature parameters in real time. Specifically, it is an environmental event structuring device based on adaptive baseline tracking. Background Technology

[0002] With the deep integration of the Internet of Things (IoT) and big data technologies, the environmental monitoring field has placed higher demands on the dimensionality, real-time performance, and accuracy of sensor data. In typical big data application scenarios such as smart cities, industrial IoT, and ecological monitoring, various sensors deployed at the front end (such as sound, light, vibration, and gas sensors) continuously generate massive amounts of continuous analog signals. These raw signal streams constitute the source of environmental big data analysis, but they are unstructured, and directly transmitting and processing them faces enormous challenges.

[0003] Currently, there are two main technical approaches to data processing. The first involves digitizing the sensor's analog signals using a high-sampling-rate analog-to-digital converter (ADC) and uploading the massive raw data stream to the cloud or a central server for processing. While this method preserves complete information, it generates extremely high data redundancy, leading to huge consumption of communication bandwidth, cloud storage costs, and computing resources, and placing a heavy preprocessing burden on subsequent data mining. The second approach involves simple local processing at the sensing node, such as using threshold comparison circuits for detection. While this method reduces the amount of data, it cannot adapt to slow baseline shifts in the environment (such as gradual changes in light intensity or temperature), and is prone to false alarms or missed alarms due to baseline drift. More importantly, it only provides a binary "present or absent" judgment, losing multi-dimensional feature information such as the specific amplitude of the event, its accurate duration, and the baseline background at the time of the event. These features are precisely the structured data necessary for advanced data analysis (such as event classification, trend prediction, and causal correlation).

[0004] Therefore, in the IoT sensing layer, to achieve the crucial transformation from "raw data collection" to "feature information generation" and provide a high-value information flow that can be directly utilized by the backend big data analysis platform, the aforementioned problems must be solved at the data source. The front-end device provided by this invention can adaptively track the environmental baseline to filter out slowly varying interference, accurately capture and segment effective transient events, and simultaneously generate a structured event description containing standard features such as baseline, peak value, and pulse width. This completes the initial transformation from data to information at the source, greatly improving data quality and value density. To this end, this invention proposes an environmental event structuring device based on adaptive baseline tracking. Utility Model Content

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide an environmental event structuring device based on adaptive baseline tracking, comprising:

[0006] A voltage follower, whose non-inverting input terminal serves as the device signal input terminal;

[0007] An operational amplifier and a positive feedback resistor network are provided, wherein the non-inverting input of the operational amplifier is connected to the output of the voltage follower, and the positive feedback resistor network is connected between the non-inverting input and the output of the operational amplifier.

[0008] An integral switching network includes an integrating capacitor, a first integrating element, a second integrating element, and a single-pole double-throw analog switch. The integrating capacitor is connected between the inverting input and output of the operational amplifier. The common terminal of the single-pole double-throw analog switch is connected to the inverting input of the operational amplifier. Its first selection terminal is connected to the output of the voltage follower through the first integrating element, and its second selection terminal is connected to the output of the voltage follower through the second integrating element. The integration time constant of the first integrating element is greater than that of the second integrating element.

[0009] An AND gate is configured such that its first input is connected to the output of the operational amplifier, and its output is connected to the control terminal of the single-pole double-throw analog switch. The single-pole double-throw analog switch connects the first selection terminal when the control terminal is high and connects the second selection terminal when the control terminal is low.

[0010] An inverter, wherein the input terminal of the inverter is connected to the output terminal of the AND gate;

[0011] A reset switch is connected between the inverting input and output terminals of the operational amplifier, in parallel with the integrating capacitor, and its control terminal is connected to the output terminal of the inverter.

[0012] A timing pulse generator, the output of which is connected to the second input of the AND gate, outputs a periodic pulse signal with a high-level duration longer than the low-level duration.

[0013] Preferably, the first integrating element is a first integrating resistor, the second integrating element is a second integrating resistor, and the resistance of the first integrating resistor is 5 to 100 times the resistance of the second integrating resistor.

[0014] Preferably, the positive feedback resistor network includes a first feedback resistor and a second feedback resistor; the non-inverting input terminal of the operational amplifier is grounded through the second feedback resistor and connected to its output terminal through the first feedback resistor.

[0015] Preferably, it further includes a peak hold circuit, the peak hold circuit comprising:

[0016] A diode, the anode of which is connected to the output of the voltage follower;

[0017] The first capacitor is connected between the cathode of the diode and ground;

[0018] The first switch is connected in parallel across the first capacitor, and its control terminal is connected to the output terminal of the AND gate.

[0019] Preferably, it further includes a pulse width conversion circuit, the pulse width conversion circuit comprising:

[0020] A constant current source; a second capacitor, wherein the output terminal of the constant current source is connected to one end of the second capacitor and the other end is grounded;

[0021] The second switch is connected in parallel across the second capacitor, and its control terminal is connected to the output terminal of the operational amplifier.

[0022] Preferably, it also includes a baseline voltage follower, the input of which is connected to the inverting input of the operational amplifier for outputting a baseline voltage;

[0023] A peak voltage follower, whose input is connected to the cathode of the diode, is used to output the peak voltage;

[0024] A pulse width voltage follower, whose input is connected to one end of the second capacitor, is used to output a pulse width voltage.

[0025] Preferably, it also includes an event identifier output driver, which includes a pull-up resistor and a buffer; one end of the pull-up resistor is connected to a power supply, and the other end is connected to the output of the operational amplifier and the input of the buffer.

[0026] Preferably, the first integrating element includes a counter, a multiplexer, and multiple integrating resistors with different resistance values, and the second integrating element is a second integrating resistor with a fixed resistance value;

[0027] The clock terminal of the counter is connected to the output terminal of the timing pulse generator, and its output terminal is connected to the address terminal of the multiplexer. The multiple data input terminals of the multiplexer are respectively connected to one end of the multiple integrating resistors with different resistance values. The resistance value of each integrating resistor is greater than the resistance value of the second integrating resistor. The other end of each integrating resistor is connected to the output terminal of the voltage follower. The output terminal of the multiplexer is connected to the first selection terminal of the single-pole double-throw analog switch.

[0028] The beneficial effects of this utility model are: 1. It realizes the hardware mapping from analog signals to feature parameters from the source: Through the adaptive baseline tracking and event triggering mechanism, this device can identify effective events and filter out background changes in real time at the perception layer, and convert massive continuous analog signals into discretely triggered, clearly marked event sequences, thereby greatly reducing data redundancy and transmission load from the source and solving the bandwidth and cost pressure brought by full upload.

[0029] 2. Improved accuracy and response speed of event detection: Utilizing adaptive closed-loop control of "slow tracking and fast reset", this device can smoothly follow the slow changes of the environmental baseline to avoid false alarms; and can also quickly adjust the baseline to respond when an event occurs, effectively capturing transient signals and overcoming the problem of missed or delayed alarms caused by baseline drift interference in the fixed threshold method.

[0030] 3. Outputs directly measurable multi-dimensional event feature simulation signals: While detecting events, this device simultaneously generates and outputs key feature quantities such as baseline voltage, peak voltage, and pulse width voltage of the events, thereby providing a complete structured description of each event covering background, amplitude, and duration. This provides a high-quality, high-value signal source for the backend big data platform to classify events, perform statistical analysis, and train models, solving the problem of feature information loss in traditional methods. Attached Figure Description

[0031] Figure 1 This is a system framework diagram of an environmental event structuring device based on adaptive baseline tracking;

[0032] Figure 2 This is a circuit structure diagram of a specific embodiment of the present invention;

[0033] Figure 3 This is a circuit structure diagram of another specific embodiment of the present invention;

[0034] Figure 4 A circuit diagram of a specific embodiment of this utility model that adds peak detection function;

[0035] Figure 5 A circuit diagram of a specific embodiment of this utility model that adds pulse width conversion function and baseline voltage output.

[0036] Figure Labels

[0037] R1 - First integrating resistor, R2 - Second integrating resistor, R3 - Pull-up resistor, R4 - First feedback resistor, R5 - Second feedback resistor, R6 - Input resistor, Rt1 - First timing resistor, Rt2 - Second timing resistor, R_set - Setting resistor, R1a - First selectable integrating resistor, R1b - Second selectable integrating resistor, R1c - Third selectable integrating resistor, R1d - Fourth selectable integrating resistor; C1 - Integrating capacitor, C2 - First capacitor, C3 - Second capacitor, Ct - External timing capacitor; U1 - Voltage follower Units: U2 - Operational amplifier, U3 - AND gate, U4 - Timing pulse generator, U5 - Inverter, U6 - Baseline voltage follower, U7 - Peak voltage follower, U8 - Pulse width voltage follower, U9 - Buffer, U10 - Counter, U11 - Multiplexer, Vref_G - Reference voltage source; S1 - Single-pole double-throw analog switch, S2 - Reset switch, S3 - First switch, S4 - Second switch; D1 - Diode; M1 - First N-channel MOSFET, M2 - Second N-channel MOSFET; G1 - Constant current source. Detailed Implementation

[0038] The technical solution of this utility model is described in further detail below with reference to the accompanying drawings, but the scope of protection of this utility model is not limited to the following description.

[0039] The features and performance of this utility model will be further described in detail below with reference to the embodiments.

[0040] Example 1

[0041] like Figure 1 As shown, this embodiment provides a basic implementation of an environmental event structuring device based on adaptive baseline tracking, including:

[0042] Voltage follower U1, with its non-inverting input terminal serving as the device signal input terminal;

[0043] An operational amplifier U2 and a positive feedback resistor network are provided. The non-inverting input of the operational amplifier U2 is connected to the output of the voltage follower U1, and the positive feedback resistor network is connected between the non-inverting input and the output of the operational amplifier U2.

[0044] An integral switching network includes an integrating capacitor C1, a first integrating element, a second integrating element, and a single-pole double-throw analog switch S1. The integrating capacitor C1 is connected between the inverting input and output of the operational amplifier U2. The common terminal of the single-pole double-throw analog switch S1 is connected to the inverting input of the operational amplifier U2. Its first selection terminal is connected to the output of the voltage follower U1 through the first integrating element, and its second selection terminal is connected to the output of the voltage follower U1 through the second integrating element. The integration time constant of the first integrating element is greater than that of the second integrating element.

[0045] AND gate U3 has its first input terminal connected to the output terminal of operational amplifier U2, and its output terminal connected to the control terminal of single-pole double-throw analog switch S1; the single-pole double-throw analog switch S1 connects the first selection terminal when the control terminal is high, and connects the second selection terminal when the control terminal is low.

[0046] Inverter U5, whose input is connected to the output of AND gate U3;

[0047] Reset switch S2 is connected between the inverting input terminal and the output terminal of the operational amplifier U2, and is connected in parallel with the integrating capacitor C1. Its control terminal is connected to the output terminal of the inverter U5.

[0048] The timing pulse generator U4 has its output terminal connected to the second input terminal of the AND gate U3. The timing pulse generator U4 outputs a periodic pulse signal with a high-level duration longer than the low-level duration.

[0049] The input signal is buffered by voltage follower U1 and split into two paths: an instantaneous signal is sent to the non-inverting input of operational amplifier U2, and the integral signal is sent to the inverting input via an integral switching network to generate a dynamic baseline voltage. The comparison result output by operational amplifier U2 is logically ANDed with the timing pulse in AND gate U3 to generate an adaptive control signal. This signal directly controls the switching of the time constant of the integral switching network, and simultaneously controls the on / off state of reset switch S2 after being inverted by inverter U5, forming a closed-loop control mechanism of "slow baseline tracking during calm periods and fast reset response during event periods".

[0050] Example 2

[0051] This embodiment provides a specific circuit implementation of the device described in Embodiment 1, and another implementation of the first integrating element in the integrating switching network.

[0052] like Figure 2As shown, the device includes a voltage follower U1, which can be a unity-gain stable TI OPA320 precision operational amplifier. Its non-inverting input is used as the signal input, and its inverting input is directly shorted to the output, thus forming a voltage follower for receiving and buffering input signals with high input impedance.

[0053] The positive feedback resistor network is connected between the non-inverting input and output of the operational amplifier U2.

[0054] Operational amplifier U2 is selected from high-precision, low-offset operational amplifiers suitable for integrator applications (such as TIOPA2188). Its non-inverting input is connected to the output of voltage follower U1.

[0055] To improve anti-interference capability and ensure output level compatibility with subsequent digital logic, the operational amplifier U2 is configured as a comparator with hysteresis through a positive feedback resistor network. Specifically, the output of the voltage follower U1 is connected to the non-inverting input of the operational amplifier U2 via an input resistor R6 (10kΩ); a first feedback resistor R4 (10MΩ) is connected between the output and non-inverting input of the operational amplifier U2, and a second feedback resistor R5 (100kΩ) is connected between the non-inverting input and ground. Thus, the non-inverting input of the operational amplifier U2 receives the output signal from the voltage follower U1 through the input resistor R6, and forms positive feedback through the network of the first and second feedback resistors R4 and R5, generating a hysteresis voltage of approximately 30mV. Its output can stably saturate to the power rail, meeting the requirements of the digital logic level.

[0056] The integral switching network includes an integrating capacitor C1, a first integrating element, a second integrating element, and a single-pole double-throw analog switch S1. Wherein:

[0057] The integrating capacitor C1 is a ceramic capacitor with a capacitance of 1nF, and is connected between the inverting input terminal and the output terminal of the operational amplifier U2.

[0058] The single-pole double-throw analog switch S1 can be an ADI ADG5412 CMOS analog switch. Its common terminal is connected to the inverting input terminal of the operational amplifier U2.

[0059] In this embodiment, the first integrating element and the second integrating element are selected as a first integrating resistor R1 and a second integrating resistor R2, both of which are precision metal film resistors. The resistance of the first integrating resistor R1 is 1MΩ, and the resistance of the second integrating resistor R2 is 20kΩ. The resistance ratio between the two is 50 times, falling within the design range of 5 to 100 times. This resistance ratio range is set based on circuit performance optimization considerations: when the resistance ratio is less than 5 times, the switching effect of the integration time constant is not obvious, and it is impossible to clearly distinguish between "slow tracking" and "fast reset"; when the resistance ratio is greater than 100 times, the integration time constant of the fast reset mode is too small, making it susceptible to noise interference and causing a decrease in baseline tracking stability. Therefore, the range of 5 to 100 times is the preferred range that balances switching effect and stability. One end of the first integrating resistor R1 is connected to the output terminal of the voltage follower U1, and the other end is connected to the first selection terminal of the single-pole double-throw analog switch S1; one end of the second integrating resistor R2 is connected to the output terminal of the voltage follower U1, and the other end is connected to the second selection terminal of the single-pole double-throw analog switch S1.

[0060] It also includes an AND gate U3, a timing pulse generator U4, and an inverter U5. The AND gate U3 can be a single AND gate chip of type SN74LVC1G08, and the inverter U5 can be a single inverter chip of type SN74LVC1G04. The first input terminal of the AND gate U3 is connected to the output terminal of the operational amplifier U2, the second input terminal is connected to the output terminal of the timing pulse generator U4, and its output terminal is connected to the control terminal of the single-pole double-throw analog switch S1. The input terminal of the inverter U5 is connected to the output terminal of the AND gate U3, and its output terminal is connected to the control terminal of the reset switch S2.

[0061] The timing pulse generator U4 can be an NE555 timer. Its trigger pin (TRIG) is interconnected with the threshold pin (THRES) and grounded through an external timing capacitor Ct of 144nF. Its discharge pin (DISCH) is connected to the +3.3V power supply (VCC) through the first timing resistor Rt1 (8kΩ) and to the interconnection node of the trigger pin (TRIG) and the threshold pin (THRES) through the second timing resistor Rt2 (1kΩ). This configures the timing pulse generator to output a periodic pulse signal with a frequency of 1kHz and a duty cycle of 90%, where the high level duration is approximately 900μs and the low level duration is approximately 100μs.

[0062] The reset switch S2 is an N-channel MOSFET (such as the 2N7002). Its drain is connected to the inverting input of operational amplifier U2, its source is connected to the output of operational amplifier U2, and its gate (control terminal) is connected to the output of inverter U5. When the reset switch S2 is turned on, the integrating capacitor C1 is rapidly discharged, achieving a rapid reset of the baseline voltage.

[0063] The event identifier output driver includes a 10kΩ pull-up resistor R3 and an SN74LVC1G17 buffer U9. One end of the pull-up resistor R3 is connected to the +3.3V power supply (VCC), and the other end is connected to the output of the operational amplifier U2 and the input of the buffer U9.

[0064] In this device, all active devices (including voltage follower U1, operational amplifier U2, AND gate U3, timing pulse generator U4, inverter U5, and buffer U9) are powered by a single +3.3V power supply, and the grounding terminals of all devices are connected to the system ground.

[0065] Based on the above connection relationship, the specific working process of this device is as follows:

[0066] During the quiet period when there are no events, operational amplifier U2 outputs a high level. At this time, timing pulse generator U4 outputs a high duty cycle pulse (high level 900μs, low level 100μs). During the high level of timing pulse generator U4, AND gate U3 outputs a high level adaptive control signal, controlling single-pole double-throw analog switch S1 to connect the large resistance resistor, namely the first integrating resistor R1 (1MΩ). The large integration time constant allows the baseline voltage to slowly and smoothly track the slow changes of the input signal. During the brief window of low level of timing pulse generator U4, AND gate U3 outputs a low level, and the device briefly switches to the small resistance integration path (the path where the second integrating resistor R2 is located), realizing baseline fine-tuning. At the same time, the high level signal is inverted to a low level by inverter U5, keeping reset switch S2 off.

[0067] When a rapid negative event occurs in the input signal (such as a sudden drop in signal value) and its value is lower than the difference between the baseline voltage and the hysteresis voltage, the output of operational amplifier U2 flips to a low level. At this time, the low-level output of operational amplifier U2 dominates the logic operation of AND gate U3. Throughout the entire output cycle of timing pulse generator U4, AND gate U3 outputs a low-level adaptive control signal. This signal synchronously triggers two actions: first, it controls the single-pole double-throw analog switch S1 to switch to a small resistance value, namely the second integrating resistor R2 (20kΩ), significantly reducing the integration time constant and enabling the baseline voltage to change rapidly; second, after being inverted to a high level by inverter U5, it drives the reset switch S2 to conduct, rapidly discharging the integrating capacitor C1, causing the baseline voltage to drop rapidly to a low level. After the event ends, the baseline voltage first quickly tracks to the current input signal level within the brief on-window of the second integrating resistor R2, and then resumes the slow and stable tracking dominated by the first integrating resistor R1. The level transition of the operational amplifier U2 output serves as an event indicator, and is amplified by pull-up resistor R3 and buffer U9 before being output.

[0068] In another implementation, such as Figure 3As shown, the resistance parameters of the integral switching network can also be dynamically configured through digital logic. Specifically, in this embodiment, the first integral element includes a counter U10, a multiplexer U11, and multiple integral resistors with different resistance values; the second integral element still uses the second integral resistor R2 (20kΩ), one end of which is connected to the output terminal of the voltage follower U1, and the other end is connected to the second selection terminal of the single-pole double-throw analog switch S1.

[0069] Counter U10 is a 4-bit binary counter, which can be a 74HC161 type. Its clock terminal CLK is connected to the output terminal of the timing pulse generator U4 to receive a 1kHz timing pulse. The four output terminals Q0, Q1, Q2, and Q3 of counter U10 are connected to the four address input terminals A0, A1, A2, and A3 of multiplexer U11, respectively, forming a 4-bit address bus.

[0070] The U11 multiplexer is a 16-to-1 analog multiplexer, which can be of the ADG5416 type. It has sixteen data input terminals IN0 to IN15, one output terminal Y, four address input terminals A0 to A3, and power supply pins VCC and GND.

[0071] Four of the sixteen data input terminals, IN0, IN1, IN2, and IN3, are connected to a common node via integrating resistors with resistances of 500kΩ, 1MΩ, 2MΩ, and 5MΩ (first optional integrating resistor R1a, second optional integrating resistor R1b, third optional integrating resistor R1c, and fourth optional integrating resistor R1d), respectively. This common node is connected to the output terminal of the voltage follower U1.

[0072] The remaining twelve data input terminals IN4 to IN15 are each connected to system ground through a 10MΩ high-resistance resistor to reduce noise interference. Specifically, each data input terminal is connected to one end of a 10MΩ resistor, and the other ends of the twelve resistors are connected to system ground (GND).

[0073] The output terminal Y of the multiplexer U11 is connected to the first selection terminal of the single-pole double-throw analog switch S1, forming a 4-level programmable integration network of the first integrating element (here, "programmable" means that the switching logic is preset in the hardware design stage by the number of counter bits, the selection of multiplexer and the resistor connection method. It is an automatic polling of a hardware-fixed sequence, which does not require software or external control signal intervention).

[0074] The power supply pin VCC of counter U10 and multiplexer U11 are both connected to a +3.3V power supply, and their ground pin GND is both connected to system ground.

[0075] Its core workflow is the same as the basic implementation, the difference being the switching mechanism of the integrating resistor, which needs special explanation: During the quiet period (operational amplifier U2 outputs a high level), the output of AND gate U3 is modulated by a timing pulse—during the high level, single-pole double-throw analog switch S1 connects the first selection terminal, at which time the four integrating resistors (R1a~R1d) polled by multiplexer U11 are connected to the integrating circuit, achieving fine baseline tracking; during the low level, the second selection terminal (i.e., the second integrating resistor R2) is briefly connected, with minimal impact. During the event period (operational amplifier U2 outputs a low level), AND gate U3 continuously outputs a low level, forcing single-pole double-throw analog switch S1 to lock at the second selection terminal (i.e., the second integrating resistor R2), the first selection terminal is physically disconnected, and the polling of multiplexer U11 is completely isolated from the integrating circuit, ensuring that the baseline reset path is dominated only by the fixed small-value second integrating resistor R2, unaffected by polling interference. This design strictly ensures that the multi-level adjustment only acts on the quiet period tracking, and the event period reset path is independent and reliable. The output of the timing pulse generator U4, in addition to being sent to the AND gate U3, also serves as the clock for the counter U10. The counter U10 cyclically counts, driving the multiplexer U11 to periodically poll between IN0 and IN3, causing the first integrating element to dynamically switch between four resistance values: 500kΩ, 1MΩ, 2MΩ, and 5MΩ, forming four integration time constants: the large resistance value (5MΩ) ensures high stability and slow tracking during quiet periods; the small resistance value (500kΩ) improves the initial response speed of events; and the intermediate range (1MΩ / 2MΩ) balances noise suppression and tracking accuracy. When IN4 to IN15 are selected, the integration circuit is approximately open because the input terminals are grounded through a 10MΩ resistor; this state is only used to suppress noise from unused ports. This implementation extends the adaptive adjustment of the integration time to multiple levels, providing a more flexible baseline tracking strategy.

[0076] This embodiment provides a specific implementation method for fixed resistance and dynamic configuration of the device through specific component selection and parameter setting: In the fixed resistance scheme, two-level control is achieved by switching between the first integrating resistor R1 and the second integrating resistor R2 through a single-pole double-throw analog switch S1, which is simple and reliable; In the programmable scheme, the first integrating element is composed of a counter, a multiplexer and multiple (four in this embodiment) integrating resistors to form a multi-level (four in this embodiment) programmable network, which realizes fine adaptive adjustment of the integration time constant.

[0077] Example 3

[0078] Based on any implementation of Example 2, this example further adds peak detection and hold functions.

[0079] like Figure 4As shown, the device also includes a diode D1, specifically a BAT54 type Schottky diode with low leakage current and low forward voltage drop. Its typical forward voltage drop is 0.2V to 0.3V (far lower than the 0.7V of ordinary silicon diodes), which can improve the detection accuracy of peak voltage and reduce signal attenuation. Its anode is connected to the output terminal of voltage follower U1.

[0080] The first capacitor C2 is a 1μF tantalum capacitor connected between the cathode of diode D1 and ground.

[0081] The first switch S3 uses the same type of MOSFET (2N7002) as the reset switch S2, and is connected in parallel across the first capacitor C2. Its gate (control terminal) is connected to the output terminal of the AND gate U3.

[0082] The peak voltage follower U7 uses a TI OPA320 operational amplifier with high input impedance. Its non-inverting input is connected to the cathode of diode D1, and its inverting input is directly shorted to the output, thus forming a voltage follower for outputting a stable peak voltage.

[0083] Based on the above connection relationship, the peak detection circuit operates synchronously while the circuit in Embodiment 2 is working. During the signal rise phase in the quiet period, diode D1 is turned on, charging the first capacitor C2; when a negative event (signal drop) occurs in the input signal, diode D1 is turned off, and the charge on the first capacitor C2 is maintained, thereby latching the background peak voltage before the event occurs. The process of the first capacitor C2 maintaining the background peak voltage is strictly synchronized with the event occurrence period: when the event occurs, AND gate U3 outputs a low-level adaptive control signal, the first switch S3 is turned off, and the background peak voltage stored on the first capacitor C2 is maintained; when the event ends, AND gate U3 outputs a high-level adaptive control signal, the first switch S3 is turned on, the first capacitor C2 is discharged and reset, preparing for the next peak detection. Peak voltage follower U7 is used to read and output the peak voltage held on the first capacitor C2 with high impedance.

[0084] This embodiment integrates a reset-synchronized peak detection and hold circuit based on adaptive baseline tracking. Its core lies in synchronizing the reset control of the peak hold capacitor (i.e., the first capacitor C2) with the core adaptive control signal, ensuring strict timing consistency between the background peak sampling window and the event trigger and baseline reset windows. In negative event detection mode, this circuit latches the peak value of the background signal before the event occurs (output by the peak voltage follower U7), providing crucial background level parameters for event analysis. This parameter, combined with the baseline voltage generated internally, can accurately calculate the relative change in the event's magnitude (e.g., the signal drop ratio). This design significantly expands the dimensionality of the output event characteristic signal without adding an extra sampling window, enabling the output information to simultaneously include both the event background level and dynamic change characteristics.

[0085] Example 4

[0086] Based on Example 3, this example further adds pulse width conversion function and baseline voltage output interface.

[0087] like Figure 5 As shown, the device further includes:

[0088] The constant current source G1 is used to provide a constant charging current of approximately 100μA. It includes: a reference voltage source Vref_G (an ADR5040 2.5V precision voltage reference chip can be selected), a setting resistor R_set with a resistance of 25kΩ, and a current mirror circuit consisting of a first N-channel MOSFET M1 and a second N-channel MOSFET M2 (both model 2N7002) with matched parameters.

[0089] The specific connection method of the current mirror is as follows: the positive output terminal of the reference voltage source Vref_G is connected to one end of the setting resistor R_set, and the other end of the setting resistor R_set is connected to the shorting point between the drain and gate of the first N-channel MOS transistor M1; the sources of the first N-channel MOS transistor M1 and the second N-channel MOS transistor M2 are both grounded; the gate of the second N-channel MOS transistor M2 is connected to the shorting point, and the drain is connected to the second capacitor C3 as a constant current output terminal.

[0090] The reference current I_ref flowing through the first N-channel MOSFET M1 is approximately determined by the ratio of the reference voltage to the set resistor: I_ref≈Vref_G / R_set. In this embodiment, Vref_G=2.5V and R_set=25kΩ, so the reference current is approximately 100μA. This current is replicated by a current mirror and then stably output from the drain of the second N-channel MOSFET M2. The first N-channel MOSFET M1 and the second N-channel MOSFET M2 are made of the same model and from the same batch to ensure that the threshold voltage and transconductance parameters are matched, achieving high-precision current mirroring.

[0091] The second capacitor C3 is a 0.1μF ceramic capacitor. The output terminal of the constant current source G1 is connected to one end of the second capacitor C3, and the other end of the second capacitor C3 is grounded.

[0092] The second switch S4 is a MOSFET (2N7002) of the same type as the reset switch S2, which is connected in parallel across the second capacitor C3, and its gate (control terminal) is connected to the output terminal of the operational amplifier U2.

[0093] The baseline voltage follower U6 uses a TI OPA320 operational amplifier. Its non-inverting input is connected to the inverting input of operational amplifier U2 (i.e., the connection point between the integrating capacitor C1 and the common terminal of the single-pole double-throw analog switch S1). Its inverting input is directly shorted to the output, thus forming a voltage follower used to output the tracked baseline voltage.

[0094] The pulse width voltage follower U8 uses a TI OPA320 operational amplifier. Its non-inverting input is connected to one end of the second capacitor C3, and its inverting input is directly shorted to the output, thus forming a voltage follower used to output a voltage proportional to the pulse width of the event.

[0095] Based on the above connection, during the period when the event occurs and the operational amplifier U2 output is low, the second switch S4 is turned off (because the control terminal is low). At this time, the constant current output by the constant current source G1 begins to linearly charge the second capacitor C3. The voltage across the second capacitor C3 increases linearly with time, and its voltage value is proportional to the duration of the event. When the event ends, the output of the operational amplifier U2 returns to a high level, the second switch S4 turns on (because the control terminal is high), and the second capacitor C3 is quickly discharged back to zero, stopping the charging process. Therefore, the voltage value of the second capacitor C3 at the end of charging directly reflects the pulse width of the event. The pulse width voltage follower U8 buffers and outputs this pulse width voltage. At the same time, the baseline voltage follower U6 buffers and outputs the real-time baseline voltage at the inverting input of the operational amplifier U2. Thus, the device provides three key output voltages: the baseline voltage output by the baseline voltage follower U6, the peak voltage output by the peak voltage follower U7, and the pulse width voltage output by the pulse width voltage follower U8.

[0096] This embodiment adds a pulse-width to voltage conversion circuit directly controlled by the event identifier signal and is equipped with a complete voltage follower output interface. Its function is to use the duration of the event identifier signal (operational amplifier U2 low level) to control the charging process of the capacitor by the constant current source, thereby linearly converting the abstract time width into a precisely measurable voltage value. This successfully solves the technical challenge of conveniently and accurately quantifying and outputting the event duration. Combining the baseline voltage and peak voltage outputs, a device is constructed that can synchronously and completely output the full-dimensional characteristic parameters of an event, including baseline, peak, and pulse width, greatly enhancing the device's ability to characterize and analyze environmental events.

[0097] The above description is merely a preferred embodiment of this utility model. It should be understood that this utility model is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of this utility model should be protected within the scope of the appended claims.

Claims

1. A structured environmental event device based on adaptive baseline tracking, characterized in that, include: The voltage follower (U1) has its non-inverting input terminal as the device signal input terminal; An operational amplifier (U2) and a positive feedback resistor network are provided. The non-inverting input of the operational amplifier (U2) is connected to the output of the voltage follower (U1), and the positive feedback resistor network is connected between the non-inverting input and the output of the operational amplifier (U2). An integral switching network includes an integrating capacitor (C1), a first integrating element, a second integrating element, and a single-pole double-throw analog switch (S1). The integrating capacitor (C1) is connected between the inverting input and output of the operational amplifier (U2). The common terminal of the single-pole double-throw analog switch (S1) is connected to the inverting input of the operational amplifier (U2). Its first selection terminal is connected to the output of the voltage follower (U1) through the first integrating element, and its second selection terminal is connected to the output of the voltage follower (U1) through the second integrating element. The integration time constant of the first integrating element is greater than that of the second integrating element. AND gate (U3), whose first input terminal is connected to the output terminal of operational amplifier (U2), and whose output terminal is connected to the control terminal of single-pole double-throw analog switch (S1). The single-pole double-throw analog switch (S1) turns on the first selection terminal when the control terminal is high level, and turns on the second selection terminal when the control terminal is low level. Inverter (U5), the input of which is connected to the output of AND gate (U3); A reset switch (S2) is connected between the inverting input and output terminals of the operational amplifier (U2), in parallel with the integrating capacitor (C1), and its control terminal is connected to the output terminal of the inverter (U5). A timing pulse generator (U4) is connected to the second input of the AND gate (U3). The timing pulse generator (U4) outputs a periodic pulse signal with a high-level duration longer than the low-level duration.

2. The environmental event structuring device based on adaptive baseline tracking according to claim 1, characterized in that, The first integrating element is a first integrating resistor (R1), and the second integrating element is a second integrating resistor (R2). The resistance of the first integrating resistor (R1) is 5 to 100 times the resistance of the second integrating resistor (R2).

3. The environmental event structuring device based on adaptive baseline tracking according to claim 1, characterized in that, The positive feedback resistor network includes a first feedback resistor (R4) and a second feedback resistor (R5); the non-inverting input terminal of the operational amplifier (U2) is grounded through the second feedback resistor (R5) and connected to its output terminal through the first feedback resistor (R4).

4. The environmental event structuring device based on adaptive baseline tracking according to claim 1, characterized in that, It also includes a peak hold circuit, the peak hold circuit comprising: A diode (D1) has its anode connected to the output terminal of the voltage follower (U1); The first capacitor (C2) is connected between the cathode of the diode (D1) and ground; The first switch (S3) is connected in parallel across the first capacitor (C2), and its control terminal is connected to the output terminal of the AND gate (U3).

5. The environmental event structuring device based on adaptive baseline tracking according to claim 4, characterized in that, It also includes a pulse width conversion circuit, the pulse width conversion circuit comprising: Constant current source (G1); The second capacitor (C3) is connected to one end of the output terminal of the constant current source (G1), and the other end is grounded. The second switch (S4) is connected in parallel across the second capacitor (C3), and its control terminal is connected to the output terminal of the operational amplifier (U2).

6. The environmental event structuring device based on adaptive baseline tracking according to claim 5, characterized in that, Also includes: A baseline voltage follower (U6) is connected to the inverting input of the operational amplifier (U2) to output the baseline voltage; A peak voltage follower (U7) is connected to the cathode of the diode (D1) at its input terminal and is used to output the peak voltage; The pulse width voltage follower (U8) has its input connected to one end of the second capacitor (C3) and is used to output the pulse width voltage.

7. The environmental event structuring device based on adaptive baseline tracking according to claim 1, characterized in that, It also includes an event identifier output driver, which includes a pull-up resistor (R3) and a buffer (U9). One end of the pull-up resistor (R3) is connected to the power supply, and the other end is connected to the output of the operational amplifier (U2) and the input of the buffer (U9).

8. The environmental event structuring device based on adaptive baseline tracking according to claim 1, characterized in that, The first integrating element includes a counter (U10), a multiplexer (U11), and multiple integrating resistors with different resistance values. The second integrating element is a second integrating resistor (R2) with a fixed resistance value. The clock terminal of the counter (U10) is connected to the output terminal of the timing pulse generator (U4), and its output terminal is connected to the address terminal of the multiplexer (U11). The multiple data input terminals of the multiplexer (U11) are respectively connected to one end of the multiple integrating resistors with different resistance values. The resistance value of each integrating resistor is greater than the resistance value of the second integrating resistor (R2). The other end of each integrating resistor is connected to the output terminal of the voltage follower (U1). The output terminal of the multiplexer (U11) is connected to the first selection terminal of the single-pole double-throw analog switch (S1).

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