Pulse machine output voltage sampling circuit and pulse machine

Abstract

The utility model relates to a pulse machine output voltage sampling circuit and a pulse machine, a positive / negative square wave signal output by the pulse machine and a bus voltage are scaled down by a differentiator, the scaled-down signal enters an integrator, and a square wave is integrated and converted into a linearly changing DC voltage. The integrator reset switch clears capacitor charges at the end of the sampling period to ensure that starting points of the next period are consistent, and after the amplitude of integral output is adjusted through the voltage divider, the integral output is buffered to the DSP through the voltage follower to be subjected to AD conversion. Through combination of the differentiator and the integrator, independent integration and direct current conversion of positive and negative square waves are realized so as to realize separation of positive and negative voltages. The integrating circuit suppresses high-frequency signals in the integrating process, the sampling signal-to-noise ratio is increased, and the anti-interference capacity of the circuit is higher. The output direct current signal is more stable, the complexity of a DSP algorithm is reduced, the DSP design is simplified, meanwhile, the operational amplifier and discrete elements are adopted, implementation and maintenance are easy, and low-cost, high-reliability and high-precision direct current signal output is achieved.

Description

Technical Field

[0001] This utility model relates to the fields of power electronics and electronic information, and in particular to a pulse generator output voltage sampling circuit and a pulse generator. Background Technology

[0002] The output voltage of a pulse generator is typically a square wave signal containing both positive and negative voltages. Due to the rapid switching characteristics of square waves, direct analog-to-digital (AD) conversion via a DSP presents the following problems: the large dynamic range of the signal and the alternation of positive and negative voltages result in a large amplitude span, exceeding the DSP's input range; it is also sensitive to high-frequency noise, as the high-frequency components of the square wave easily introduce interference, reducing sampling accuracy; a DC component also exists, and since square waves lack a fixed DC reference, direct quantization is difficult. Existing technologies often employ complex filtering or time-division sampling schemes, which suffer from circuit redundancy and slow response speeds. Utility Model Content

[0003] The technical problem this invention aims to solve is that the large dynamic range of the signal, coupled with the alternation of positive and negative voltages, results in a large amplitude span exceeding the input range of the DSP; furthermore, it is highly sensitive to high-frequency noise, with the high-frequency components of the square wave easily introducing interference and reducing sampling accuracy; DC components also exist, and the square wave lacks a fixed DC reference, making direct quantization difficult. To address these shortcomings of the prior art, this invention provides a pulse generator output voltage sampling circuit and a pulse generator.

[0004] To solve the above-mentioned technical problems, the technical solution adopted by this utility model is as follows:

[0005] A pulse generator output voltage sampling circuit is constructed, comprising a differential circuit that receives positive and negative square wave signals and a bus voltage signal from the pulse generator, and an integrator circuit connected to the differential circuit. The differential circuit proportionally reduces the input signal to a differential signal output. The integrator circuit converts the differential signal into a linearly changing DC signal. The integrator circuit is connected to a voltage divider circuit that adjusts the amplitude of the DC signal. The voltage divider circuit is connected to a follower circuit, and the other end of the follower circuit is connected to a conversion circuit. The conversion circuit outputs a signal to a DSP.

[0006] Preferably, the integrator circuit is further connected to an integrator reset switch, which periodically resets the integrator.

[0007] Preferably, the integrator reset switch consists of a MOSFET and a current-limiting resistor to synchronize the control signal with the sampling period.

[0008] Preferably, the conversion circuit is connected to a protection circuit, which consists of diodes to protect the output signal.

[0009] Preferably, the differential circuit includes a first differential amplifier, and a plurality of resistors and a plurality of capacitors connected to the first differential amplifier.

[0010] Preferably, the integrator circuit includes a second differential amplifier, which is connected to the output terminal of the differential circuit through multiple series resistors. Multiple parallel resistors are connected between the negative terminal of the second differential amplifier and the output terminal, and an integrator reset switch is connected between the negative terminal and the output terminal.

[0011] Preferably, the voltage divider circuit includes a plurality of series-connected resistors connected to the output of the second differential amplifier, and the follower circuit includes a third differential amplifier, as well as resistors and capacitors connected to the third differential amplifier.

[0012] A pulse generator is constructed, which contains a pulse generator output voltage sampling circuit as described above, and the output voltage of the pulse generator is acquired through the sampling circuit.

[0013] The beneficial effects of this invention are as follows: The positive / negative square wave signals output by the pulse generator and the bus voltage are proportionally reduced by a differential circuit. The reduced signals then enter an integrator, where the square waves are integrated and converted into a linearly changing DC voltage. The integrator reset switch clears the capacitor charge at the end of the sampling period, ensuring a consistent start point for the next period. The integrated output, after amplitude adjustment by a voltage divider, is buffered by a voltage follower before being sent to the DSP for AD conversion. By combining the differential and integrator, independent integration and DC-DC conversion of the positive and negative square waves are achieved, thus separating the positive and negative voltages. The integrating circuit suppresses high-frequency signals during integration, improving the sampling signal-to-noise ratio and enhancing the circuit's anti-interference capability. The output DC signal is more stable, reducing the complexity of the DSP algorithm and simplifying DSP design. Furthermore, the use of operational amplifiers and discrete components makes implementation and maintenance easy, achieving low cost and high reliability. Therefore, high-precision DC signal output is achieved through positive and negative voltage separation, integration conversion, and signal conditioning.

[0014] The difference between the positive and negative square waves and the bus voltage is extracted by a differential circuit, converted into a linear DC signal by an integrator, and prevented from saturating by a reset switch. The signal is then conditioned by a voltage divider and voltage follower before being output to the DSP. This circuit solves the problem of direct acquisition of square wave signals and has advantages such as simple structure, strong anti-interference, and low cost, making it suitable for voltage monitoring systems in power electronic equipment. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the utility model will be further described below in conjunction with the accompanying drawings and embodiments. The drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a functional block diagram of the sampling circuit of a preferred embodiment of the present invention;

[0017] Figure 2 The circuit diagram is a preferred embodiment of the sampling circuit of this utility model. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, a clear and complete description will be provided below in conjunction with the technical solutions in the embodiments of this utility model. Obviously, the described embodiments are some, but not all, embodiments of this utility model. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0019] A preferred embodiment of the present invention provides a pulse generator output voltage sampling circuit; such as... Figure 1 As shown, the voltage sampling circuit includes a differential circuit 20. The differential circuit receives the input signal 10 and proportionally reduces the voltage of the input signal and the square wave voltage signal on the output side. The other end of the differential circuit 20 is connected to an integrator circuit 30, which converts the square wave signal into a voltage signal that increases linearly with time integration. The other end of the integrator circuit 30 is connected to a voltage divider circuit 40, which prevents the output voltage from deviating from the expected value, thus preventing overload of subsequent circuits. The other end of the voltage divider circuit 40 is connected to a follower circuit 50, which prevents interference to the signal source, thereby increasing the driving capability. The other end of the follower circuit 50 is connected to a conversion circuit 60, which performs AD conversion on the signal to obtain the output signal 70 on the output side. The output signal is a digital voltage signal. By using the integrator circuit to separately acquire the bus voltage and positive output of the input signal, as well as the bus voltage and negative output, the positive and negative voltages are separated, and the square waves of the positive and negative voltages are converted into DC voltages, which is beneficial for the DSP to directly acquire the output voltage.

[0020] Specifically, such as Figure 1As shown, the integrator circuit 30 is also connected to an integrator reset switch 90. The integrator reset switch resets the state of the integrator circuit, thereby resolving output saturation, eliminating error accumulation and periodic operation, and ensuring that the integrator circuit operates within a controllable range. The conversion circuit is also connected to a protection circuit 80, which protects the output signal from excessively high output voltage or current, thus protecting the circuit.

[0021] Furthermore, such as Figure 2 As shown, the differential circuit 20 includes a first differential amplifier U403A. The positive terminal of pin 3 of the first differential amplifier is connected to one end of the input signal through resistors R422 and R421 connected in series. The positive terminal of pin 3 is also connected to a 2V 5A power supply through resistors R425 and C412 connected in parallel. The negative terminal of pin 2 is connected to the other end of the input signal through resistors R415 and R416 connected in series. The negative terminal of pin 2 is also connected to the output terminal of the first differential amplifier through resistors R413 and C411 connected in parallel. Pin 8 is connected to a 5V power supply, and pin 4 is grounded and connected to a 5V power supply through capacitor C415. The differential circuit 20 is used to proportionally reduce the difference between the bus voltage and the output side square wave signal, suppressing common-mode interference. Resistors 415 and 416, along with resistors 422 and 421, form a proportional network. The differential gain can be calculated based on the resistor values, thereby reducing the amplitude of the input signal. Capacitors 412 and 415 can filter out high-frequency noise in the circuit.

[0022] Furthermore, such as Figure 2As shown, the integrator circuit 30 includes a second differential amplifier U5A. The positive terminal of pin 3 of the second differential amplifier is connected to a 2V 5A power supply. The negative terminal of pin 2 is connected to the output terminal of the differential circuit 20 through resistors R35 (35th), R37 (37th), and R39 (39th) connected in series. Capacitors C32 (32nd), C33 (33rd), and C34 (34th) are connected in parallel between the negative terminal of pin 2 and the output terminal of pin 1. The integrator circuit converts the square wave signal into a linear rising / falling ramp signal. The integration time constant can be calculated using the resistors and capacitors, and it must be greater than 10% of the square wave period to ensure linear integration. Meanwhile, in order to periodically reset the integrator circuit, the integrator circuit 30 is also connected to an integrator reset switch 90. The integrator reset switch includes a first MOSFET Q1 and a second MOSFET Q2 connected in series, which are respectively connected to the negative terminal and the output terminal of the second differential amplifier. A sixty-sixth resistor R66 is connected between the first MOSFET and the second MOSFET. The first MOSFET and the second MOSFET of the reset switch can be selected as low on-resistance MOSFETs to control the reset time in the microsecond range. At the same time, the integrator capacitor charge is periodically reset to prevent output saturation.

[0023] Furthermore, such as Figure 2 As shown, the voltage divider circuit 40 includes resistors R34 (34th), R36 (36th), and R38 (38th) connected in series and grounded. The integrated voltage amplitude is adjusted through the resistor network to match the DSP's input range. The follower circuit 50 includes a third differential amplifier U403B. The positive terminal of pin 5 of the third differential amplifier is connected to resistor R36 (36th), and the negative terminal of pin 6 is connected to the output terminal of pin 7 through resistor R40 (40th). The output terminal of pin 7 is grounded through resistor R418 (418th) and capacitor C413 (413th) connected in series. The other end of resistor R418 is the output signal, thereby reducing output impedance and enhancing drive capability. A low-bias current operational amplifier can be used for the third differential amplifier to avoid signal attenuation. The other end of resistor R418 is connected to a clamping protection circuit composed of diodes to protect the circuit.

[0024] In operation, the circuit of this application reduces the positive / negative square wave signals output by the pulse generator and the bus voltage proportionally after differential conversion. The reduced signals then enter the integrator, where the square waves are integrated and converted into a linearly varying DC voltage. The integrator reset switch clears the capacitor charge at the end of the sampling period, ensuring a consistent start point for the next period. The integrated output, after amplitude adjustment by a voltage divider, is buffered by a voltage follower before being sent to the DSP for AD conversion. By combining the differential and integrator, independent integration and DC-DC conversion of the positive and negative square waves are achieved, thus separating the positive and negative voltages. The integrating circuit suppresses high-frequency signals during integration, improving the sampling signal-to-noise ratio and enhancing the circuit's anti-interference capability. The output DC signal is more stable, reducing the complexity of the DSP algorithm and simplifying DSP design. Furthermore, the use of operational amplifiers and discrete components makes implementation and maintenance easy, achieving low cost and high reliability.

[0025] A preferred embodiment of the present invention provides a pulse generator, which includes an output voltage sampling circuit for acquiring the output voltage. The specific output voltage sampling circuit is the same as described above and will not be repeated here.

[0026] It should be understood that this utility model has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of this utility model. Furthermore, under the teachings of this utility model, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of this utility model. Therefore, this utility model is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of this utility model.

Claims

1. A pulse generator output voltage sampling circuit, comprising a differential circuit, wherein the differential circuit receives positive and negative square wave signals and a bus voltage signal from the pulse generator, and an integrator circuit connected to the differential circuit, characterized in that: The differential circuit reduces the input signal to a differential signal output proportionally. The integrator circuit converts the differential signal into a linearly changing DC signal. The integrator circuit is connected to a voltage divider circuit, which adjusts the amplitude of the DC signal. The voltage divider circuit is connected to a follower circuit, and the other end of the follower circuit is connected to a conversion circuit. The conversion circuit outputs a signal to the DSP.

2. The sampling circuit according to claim 1, characterized in that: The integrator circuit is also connected to an integrator reset switch, which periodically resets the integrator.

3. The sampling circuit according to claim 2, characterized in that: The integrator reset switch consists of a MOSFET and a current-limiting resistor to synchronize the control signal with the sampling period.

4. The sampling circuit according to claim 1, characterized in that: The conversion circuit is connected to a protection circuit, which consists of diodes to protect the output signal.

5. The sampling circuit according to claim 1, characterized in that: The differential circuit includes a first differential amplifier, and a plurality of resistors and a plurality of capacitors connected to the first differential amplifier.

6. The sampling circuit according to claim 5, characterized in that: The integrator circuit includes a second differential amplifier, which is connected to the output of the differential circuit through multiple series resistors. Multiple parallel resistors are connected between the negative terminal of the second differential amplifier and the output terminal. An integrator reset switch is connected between the negative terminal and the output terminal.

7. The sampling circuit according to claim 6, characterized in that: The voltage divider circuit includes multiple series-connected resistors connected to the output of the second differential amplifier, and the follower circuit includes a third differential amplifier, as well as resistors and capacitors connected to the third differential amplifier.

8. A pulse generator, characterized in that: The pulse generator contains a pulse generator output voltage sampling circuit as described in any one of claims 1-7, and the output voltage of the pulse generator is acquired through the sampling circuit.

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