Chip stacking structure, circuit board and electronic equipment

Abstract

The utility model discloses a chip stack structure, circuit board and electronic equipment, including first capacitor and component, the first capacitor includes at least two first bonding pad that are arranged at interval, the component is connected with signal line, the signal line passes through the two first bonding pad between, and the signal line passes through the first bonding pad between the first bonding pad and the second bonding pad between the first bonding pad and the second bonding pad. And the signal lines and the first bonding pads are arranged at intervals. The chip stacking structure provided by the utility model can reduce the routing redundancy during the design of the circuit board and improve the integration level of stacking, and is beneficial to the realization of the miniaturization design of the circuit board.

Description

Technical Field

[0001] This utility model relates to the field of circuit board technology, specifically to a chip stacking structure, a circuit board, and an electronic device. Background Technology

[0002] A circuit board (PCB) is a printed board on a general-purpose substrate with interconnections and printed components formed according to a predetermined design. Circuit boards are known as the mother of electronic products and are irreplaceable in electronic products.

[0003] In existing circuit board stacking designs, for some peripheral devices on chip ICs, especially filter capacitors with small capacitance values, in order to reduce the return current area and achieve optimal signal integrity, peripheral devices usually need to be stacked close to the corresponding functional pins of the chip IC.

[0004] However, for some large-package capacitors, when the capacitor stack is placed close to the functional pins, it will create a bottleneck for the fan-out routing of other functional pins. For example, it may prevent the fan-out routing on the same layer, and important signal lines may require three-dimensional grounding isolation.

[0005] Regarding the challenges of routing large-package capacitor stacks, existing technologies primarily offer two solutions: ① Replacing the large-package capacitors with miniaturized ones, which increases the overall device cost; ② Placing the large-package filter capacitors away from the IC chip, which sacrifices signal integrity, increases return current area, and reduces stack integration. Furthermore, to ensure signal integrity, additional filter capacitors are often required, further increasing costs. Utility Model Content

[0006] This utility model aims to at least partially solve one of the technical problems in the related art.

[0007] Therefore, this utility model embodiment proposes a chip stacking structure, which can reduce trace redundancy in circuit board design and improve the integration of stacking, which is conducive to realizing the miniaturization design of circuit boards.

[0008] This utility model embodiment also proposes a circuit board including the above-described chip stacking structure.

[0009] The chip stacking structure of this utility model embodiment includes:

[0010] A first capacitor, the first capacitor comprising at least two spaced-apart first pads;

[0011] The component is connected to a signal line that passes between two first pads and is spaced apart from each first pad.

[0012] In some embodiments, the width of the signal line in the direction opposite to the two first pads is 0.15 mm to 0.25 mm.

[0013] In some embodiments, the component is an inductor, a second capacitor, or a resistor.

[0014] In some embodiments, the first capacitor includes at least two solder feet, each solder foot being connected to one of the two first pads, and in the opposite direction of the two first pads, the width of each solder foot is smaller than the width of the first pad to which it is connected.

[0015] In some embodiments, the width of the solder foot is 0.25 mm to 1 mm.

[0016] In some embodiments, the first capacitor includes two design pads, the first pad being formed by reducing the width of the design pads, and the ratio of the reduced width dimension of the design pads to the width dimension of the design pads is 10% to 15%.

[0017] In some embodiments, the first capacitor includes a capacitor line, and the extension direction of the signal line is consistent with the extension direction of the capacitor line.

[0018] In some embodiments, a third capacitor is included, the third capacitor including at least two second pads disposed between two adjacent signal lines and spaced apart in the extension direction of the signal lines.

[0019] The circuit board of this utility model embodiment includes a substrate and a chip stacking structure as described in any of the above embodiments, wherein the chip stacking structure is disposed on the substrate.

[0020] The electronic device of this utility model embodiment includes the circuit board as described in any of the above embodiments.

[0021] Beneficial effects: The chip stacking structure, circuit board and electronic device of this utility model can reduce the redundancy of the wiring in the circuit board design and improve the integration of the stack, which is conducive to realizing the miniaturization design of the circuit board.

[0022] Secondly, the design of the signal line passing between the two first pads allows the filter capacitor to be placed close to the component pins, which reduces the distance between the filter capacitor and the component pins. This reduces the signal return area and ensures signal integrity and power supply integrity. It also reduces the number of capacitors used, thus reducing costs.

[0023] In addition, by passing the signal lines of the components between the two first pads of the first capacitor, the first capacitor can be placed close to the pins of the components. This allows the first capacitor to be closer to the pins of the components and shortens the overall length of the signal lines, which can also reduce return impedance and improve overall performance. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the overall structure of the chip stacking structure according to an embodiment of the present invention.

[0025] Figure 2 This is a schematic diagram comparing the arrangement of the design pads and solder feet in this embodiment of the present invention with the arrangement of the first pads and solder feet.

[0026] Figure 3 This is a schematic diagram of the circuit board according to an embodiment of the present invention.

[0027] Figure label:

[0028] 100-Chip stacking structure;

[0029] 1-First capacitor; 11-First pad; 12-Capacitor line; 13-Solder lead; 14-Design pad;

[0030] 2-Components; 21-Signal lines;

[0031] 3-Third capacitor; 31-Second pad;

[0032] 200-Substrate. Detailed Implementation

[0033] The embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0034] like Figure 1 As shown, the chip stacking structure 100 of this embodiment includes a first capacitor 1 and components 2.

[0035] The first capacitor 1 includes at least two spaced-apart first pads 11. For example, as shown... Figure 1 As shown, the first capacitor 1 can be a filter capacitor, and the first capacitor 1 may consist of only two first pads 11, which can be arranged at intervals in the left-right direction. In some other embodiments, the first capacitor 1 may also include three, four, five, or other numbers of first pads 11.

[0036] Component 2 is connected to a signal line 21, which passes between two first pads 11 and is spaced apart from each first pad 11. For example, component 2 can be a peripheral device on a circuit board, and specifically, component 2 can be an inductor, a second capacitor different from the first capacitor 1 mentioned above, a resistor, etc.

[0037] like Figure 1 As shown, taking component 2 as an inductor as an example, component 2 can be roughly rectangular in structure, signal line 21 can be roughly extended along the front-to-back direction, and the rear end of signal line 21 can be connected to component 2.

[0038] It should be noted that, since the two first pads 11 are arranged at intervals, a gap space is formed between the two first pads 11. The signal line 21 of component 2 can be laid in the gap space between the two first pads 11, and the left and right sides of the signal line 21 can be spaced apart from the two first pads 11 respectively.

[0039] The chip stacking structure 100 of this utility model embodiment can reduce the redundancy of traces in circuit board design and improve the integration of stacking, which is conducive to realizing the miniaturization design of circuit boards.

[0040] Secondly, the design of the signal line 21 passing between the two first pads 11 allows the filter capacitor to be placed close to the pins of the component, which reduces the distance between the filter capacitor and the pins of the component 2. This reduces the signal return area and ensures signal integrity and power supply integrity. It also reduces the number of capacitors used, thus reducing costs.

[0041] In addition, by passing the signal line 21 of component 2 between the two first pads of the first capacitor, the first capacitor can be placed close to the pin of component 2. This allows the first capacitor to be closer to the pin of component 2 and shortens the overall length of the signal line 21, which can also reduce the return impedance and improve the overall performance.

[0042] In some embodiments, the width of the signal line 21 in the opposite direction of the two first pads 11 is 0.15 mm to 0.25 mm. For example, as... Figure 1 As shown, the width of signal line 21 can be M1, specifically 0.15mm, 0.16mm, 0.17mm, 0.18mm, 0.19mm, 0.2mm, 0.21mm, 0.22mm, 0.23mm, 0.24mm, 0.25mm, etc. This allows the width of signal line 21 to be limited within a reasonable range, ensuring both effective signal communication and isolation from the first pad 11.

[0043] In some embodiments, the first capacitor 1 includes at least two solder feet 13, which are respectively connected to two first pads 11, and in the opposite direction of the two first pads 11, the width of each solder foot 13 is smaller than the width of the first pad 11 to which the solder foot 13 is connected.

[0044] For example, such as Figure 2 As shown, the cross-sections of both the solder foot 13 and the first pad 11 are generally rectangular. The width of the solder foot 13 can be the dimension in the left-right direction, specifically dimension M2. The width of the first pad 11 can be the dimension in the left-right direction, specifically dimension M3. The dimension M2 of each solder foot 13 is smaller than the dimension M3 of the first pad 11 connected to it, thus ensuring a sufficient connection between the solder foot 13 and the corresponding first pad 11.

[0045] In some other embodiments, the first capacitor 1 may also include three, four, five, or other numbers of solder feet 13.

[0046] In some embodiments, the width of the solder foot 13 is 0.25 mm to 1 mm. For example, as... Figure 2 As shown, the width of the solder foot 13 can be M2, and M2 can specifically be 0.25mm, 0.35mm, 0.4mm, 0.5mm, 0.6mm, 0.7mm, 0.8mm, 0.9mm, 1mm, etc.

[0047] In some embodiments, the first capacitor 1 includes two design pads 14, the first pad 11 being formed by reducing the width of the design pads 14, and the ratio of the reduced width dimension of the design pads 14 to the width dimension of the design pads 14 is 10% to 15%.

[0048] For example, such as Figure 2 As shown, the design pad 14 can be a pad of the commonly used size for existing filter capacitors. When the first capacitor 1 is installed using the size of the design pad 14, the spacing between the two design pads 14 in the left-right direction is relatively narrow, as shown in the figure. Figure 2 As shown in (a), at this time, the signal line 21 of component 2 cannot pass between the two design pads 14 and be installed.

[0049] Given the above, the width of the designed pad 14 needs to be reduced, such as... Figure 2 As shown, a portion of the right side of the left-side design pad 14 and a portion of the left side of the right-side design pad 14 can be removed. After removal, the two design pads 14 constitute two first pads 11, and the spacing between the two first pads 11 meets the installation requirements for arranging the signal line 21.

[0050] It should be noted that, as Figure 2 As shown, the reduced width dimension of each designed pad 14 can be dimension M4, and the ratio of dimension M4 to the aforementioned dimension M3 can be 10% to 15%, specifically, this ratio can be 10%, 11%, 12%, 13%, 14%, 15%, etc. Within this range of reduced dimension ratios, on the one hand, the connection structure strength of the pads is guaranteed, i.e., the soldering reliability is avoided due to the reduction of the pads, and on the other hand, the design requirement of increasing the spacing between the two pads is fully met, thereby satisfying the assembly requirements for arranging the signal lines 21.

[0051] In some embodiments, the first capacitor 1 includes a capacitor line 12, and the extension direction of the signal line 21 is consistent with the extension direction of the capacitor line 12. For example, as Figure 1 As shown, both capacitor line 12 and signal line 21 can be arranged to extend in the front-to-back direction, and capacitor line 12 can be arranged parallel to signal line 21, thus ensuring a good isolation effect between the two lines.

[0052] In some embodiments, the chip stack structure 100 includes a third capacitor 3, the third capacitor 3 including at least two second pads 31, the two second pads 31 being disposed between two adjacent signal lines 21, and the two second pads 31 being spaced apart in the extension direction of the signal lines 21.

[0053] For example, such as Figure 1 As shown, four components 2 can be provided, and the four components 2 can be arranged at intervals in the left-right direction, and the signal lines 21 of each component 2 can be arranged to extend in the front-back direction. The third capacitor 3 can be placed between the signal lines 21 of the two components 2 on the left, and the two second pads 31 of the third capacitor 3 can be arranged at intervals in the front-back direction. Thus, the filtering effect can be enhanced by adding the third capacitor 3.

[0054] In some other embodiments, the third capacitor 3 may also include three, four, or other numbers of second pads 31.

[0055] In some embodiments, such as Figure 1 As shown, there can be two first capacitors 1, four components 2, and two third capacitors 3. Both first capacitors 1 can be 10µF capacitors, and both third capacitors 3 can be 2.2µF capacitors. The signal line 21 of the leftmost component 2 can be arranged between the two first pads 11 of the leftmost first capacitor 1, and the signal line 21 of the rightmost component 2 can be arranged between the two first pads 11 of the rightmost first capacitor 1.

[0056] The third capacitor 3 on the left can be placed between the signal lines 21 of the two components 2 on the left, and the third capacitor 3 on the right can be placed between the signal lines 21 of the two components 2 on the right.

[0057] The circuit board of this utility model embodiment is described below.

[0058] The circuit board of this utility model embodiment includes a substrate 200 and a chip stacking structure 100. The chip stacking structure 100 can be the chip stacking structure 100 described in any of the above embodiments, and the chip stacking structure 100 is disposed on the substrate 200.

[0059] The following describes an electronic device according to an embodiment of the present invention.

[0060] The electronic device of this embodiment includes a circuit board, which can be the circuit board described in any of the above embodiments. The electronic device can be a mobile phone, tablet computer, etc. Of course, it can also be other electronic devices that require the installation of a circuit board.

[0061] Although the above embodiments have been shown and described, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Any changes, modifications, substitutions and variations made to the above embodiments by those skilled in the art are within the protection scope of the present invention.

Claims

1. A chip stacking structure, characterized in that, include: A first capacitor, the first capacitor comprising at least two spaced-apart first pads; The component is connected to a signal line that passes between two first pads and is spaced apart from each first pad.

2. The chip stacking structure according to claim 1, characterized in that, The width of the signal line in the opposite direction between the two first pads is 0.15 mm to 0.25 mm.

3. The chip stacking structure according to claim 1, characterized in that, The components are inductors, second capacitors, or resistors.

4. The chip stacking structure according to claim 1, characterized in that, The first capacitor includes at least two solder feet, each solder foot being connected to one of the two first pads, and in the opposite direction of the two first pads, the width of each solder foot is smaller than the width of the first pad to which it is connected.

5. The chip stacking structure according to claim 4, characterized in that, The width of the solder foot is 0.25 mm to 1 mm.

6. The chip stacking structure according to claim 1, characterized in that, The first capacitor includes two design pads, which are formed by reducing the width of the design pads, and the ratio of the reduced width dimension of the design pads to the width dimension of the design pads is 10% to 15%.

7. The chip stacking structure according to claim 1, characterized in that, The first capacitor includes a capacitor line, and the extension direction of the signal line is consistent with the extension direction of the capacitor line.

8. The chip stacking structure according to any one of claims 1-7, characterized in that, The third capacitor includes at least two second pads, which are disposed between two adjacent signal lines and are spaced apart in the extension direction of the signal lines.

9. A circuit board, characterized in that, It includes a substrate and a chip stack structure as described in any one of claims 1-8, wherein the chip stack structure is disposed on the substrate.

10. An electronic device, characterized in that, Includes the circuit board as described in claim 9 above.

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