Shift register, gate drive circuit and display device

Abstract

The utility model provides a shift register, a gate drive circuit and a display device, and belongs to the technical field of display. The shift register comprises a first input sub-circuit, an output sub-circuit, a first pull-down control sub-circuit, a second pull-down control sub-circuit, a first pull-down sub-circuit, a second pull-down sub-circuit, a first auxiliary sub-circuit and a second auxiliary sub-circuit, the first auxiliary sub-circuit is configured to pull down the potential of the first pull-down node through the first power supply voltage when the second power supply voltage is a working level signal and the first power supply voltage is a non-working level signal; and the second auxiliary sub-circuit is configured to pull down the potential of the second pull-down node through the second power supply voltage when the first power supply voltage is a working level signal and the second power supply voltage is a non-working level.

Description

Shift register, gate drive circuit and display device Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a shift register, a gate driving circuit, and a display device. Background Technology

[0002] With the continuous development of display technology, the development of displays in recent years has gradually shown a trend towards high integration and low cost. One very important technology is the mass production realization of GOA (Gate Driver on Array) technology. GOA technology integrates the gate switching circuit of TFT (Thin Film Transistor) onto the array substrate of the display panel to form a scanning drive for the display panel, thus eliminating the need for the gate driver integrated circuit. This not only reduces product costs in terms of both material costs and manufacturing processes, but also allows for a symmetrical and aesthetically pleasing design with narrow bezels. Furthermore, eliminating the gate-direction bonding process is beneficial for improving production capacity and yield. This gate switching circuit integrated onto the array substrate using GOA technology is also called a GOA circuit or a shift register circuit. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art, and to provide a shift register, a gate driving circuit and a display device.

[0004] This disclosure provides a shift register, which includes: a first input sub-circuit, an output sub-circuit, a first pull-down control sub-circuit, a second pull-down control sub-circuit, a first pull-down sub-circuit, and a second pull-down sub-circuit;

[0005] The first input sub-circuit is configured to precharge the pull-up node via a first scan signal in response to the first input signal;

[0006] The output sub-circuit is configured to output a clock signal through a signal output terminal in response to the potential of the pull-up node;

[0007] The first pull-down control sub-circuit is configured to respond to a first power supply voltage and control the potential of the first pull-down node by the first power supply voltage;

[0008] The second pull-down control sub-circuit is configured to respond to a second power supply voltage and control the potential of the second pull-down node via the second power supply voltage;

[0009] The first pull-down sub-circuit, in response to the potential of the pull-up node, pulls down the first pull-down node;

[0010] The second pull-down sub-circuit, in response to the potential of the pull-up node, pulls down the second pull-down node; wherein,

[0011] The shift register further includes: a first auxiliary sub-circuit and a second auxiliary sub-circuit;

[0012] The first auxiliary sub-circuit is configured to pull down the potential of the first pull-down node by the first power supply voltage when the second power supply voltage is a working level signal and the first power supply voltage is a non-working level signal.

[0013] The second auxiliary sub-circuit is configured to pull down the potential of the second pull-down node by the second power supply voltage when the first power supply voltage is a working level signal and the second power supply voltage is a non-working level.

[0014] Specifically, the first auxiliary sub-circuit is configured to, in response to the second power supply voltage, pull down the potential of the first pull-down node by the first power supply voltage when the second power supply voltage is a working level signal and the first power supply voltage is a non-working level signal;

[0015] The second auxiliary sub-circuit is specifically configured to, in response to the first power supply voltage, pull down the potential of the second pull-down node by the second power supply voltage when the first power supply voltage is a working level signal and the second power supply voltage is a non-working level signal.

[0016] Both the first auxiliary sub-circuit and the second auxiliary sub-circuit include a seventeenth transistor;

[0017] In the first auxiliary sub-circuit, the first terminal of the seventeenth transistor is connected to the first power supply voltage terminal, the second terminal is connected to the first pull-down node, and the control terminal is connected to the second power supply voltage terminal.

[0018] In the first auxiliary sub-circuit, the first terminal of the seventeenth transistor is connected to the second power supply voltage terminal, the second terminal is connected to the second pull-down node, and the control terminal is connected to the first power supply voltage terminal.

[0019] Specifically, the first auxiliary sub-circuit is configured to, in response to the potential of the second pull-down node, pull down the potential of the first pull-down node by the first power supply voltage when the second power supply voltage is a working level signal and the first power supply voltage is a non-working level signal;

[0020] The second auxiliary sub-circuit is specifically configured to, in response to the first pull-down node, pull down the potential of the second pull-down node by the second power supply voltage when the first power supply voltage is a working level signal and the second power supply voltage is a non-working level signal.

[0021] Both the first auxiliary sub-circuit and the second auxiliary sub-circuit include a seventeenth transistor;

[0022] In the first auxiliary sub-circuit, the first terminal of the seventeenth transistor is connected to the first power supply voltage terminal, the second terminal is connected to the first pull-down node, and the control terminal is connected to the second pull-down node;

[0023] In the first auxiliary sub-circuit, the first terminal of the seventeenth transistor is connected to the second power supply voltage terminal, the second terminal is connected to the second pull-down node, and the control terminal is connected to the first pull-down node.

[0024] The shift register further includes a global reset sub-circuit, configured to globally reset the output of the pull-up node and the signal output terminal via a non-working level signal in response to a global reset signal.

[0025] The global reset sub-circuit includes a fourth transistor and a seventh transistor;

[0026] The first terminal of the fourth transistor is connected to the pull-up node, the second terminal is connected to the non-working level signal terminal, and the control terminal is connected to the global reset signal terminal.

[0027] The first terminal of the seventh transistor is connected to the signal output terminal, the second terminal is connected to the non-operating level signal terminal, and the control terminal is connected to the global reset signal terminal.

[0028] The shift register further includes a pull-up reset sub-circuit, configured to reset the output of the pull-up node by a non-working level signal in response to the pull-up reset signal.

[0029] The pull-up reset sub-circuit includes a second transistor, the first terminal of which is connected to the pull-up node, the second terminal of which is connected to a non-working level signal terminal, and the control terminal of which is connected to the pull-up reset signal terminal.

[0030] Wherein, the first input signal is multiplexed as the first scan signal; the first input sub-circuit includes a first transistor;

[0031] The first electrode and the control electrode of the first transistor are connected to the first input signal terminal, and the second electrode is connected to the pull-up node.

[0032] The shift register further includes a second input sub-circuit configured to precharge the pull-up node via a second scan signal in response to a second input signal.

[0033] The second input sub-circuit includes a second transistor;

[0034] The first terminal of the second transistor is connected to the pull-up node, the second terminal is connected to the second scan signal terminal, and the control terminal is connected to the second input signal terminal.

[0035] The first input sub-circuit includes a first transistor;

[0036] The first terminal of the first transistor is connected to the first scan signal terminal, the second terminal is connected to the pull-up node, and the control terminal is connected to the first input signal terminal.

[0037] The shift register further includes two first noise reduction sub-circuits and two second noise reduction sub-circuits;

[0038] One of the two first noise reduction sub-circuits is configured to respond to the potential of the first pull-down node and perform noise reduction on the output of the pull-up node through a non-working level signal; the other is configured to respond to the potential of the second pull-down node and perform noise reduction on the output of the pull-up node through a non-working level signal.

[0039] One of the two second noise reduction sub-circuits is configured to respond to the potential of the first pull-down node and reduce the noise of the output of the signal output terminal by a non-working level signal; the other is configured to respond to the potential of the second pull-down node and reduce the noise of the output of the signal output terminal by a non-working level signal.

[0040] Both of the first noise reduction sub-circuits include a tenth transistor;

[0041] In one of the first noise reduction sub-circuits, the first terminal of the tenth transistor is connected to the pull-up node, the second terminal is connected to the non-working voltage terminal, and the control terminal is connected to the first pull-down node; in the other first noise reduction sub-circuit, the first terminal of the tenth transistor is connected to the pull-up node, the second terminal is connected to the non-working voltage terminal, and the control terminal is connected to the second pull-down node.

[0042] Both of the second noise reduction sub-circuits include an eleventh transistor;

[0043] In one of the second noise reduction sub-circuits, the first terminal of the eleventh transistor is connected to the signal output terminal, the second terminal is connected to the non-working voltage terminal, and the control terminal is connected to the first pull-down node; in the other second noise reduction sub-circuit, the first terminal of the eleventh transistor is connected to the pull-up node, the second terminal is connected to the non-working voltage terminal, and the control terminal is connected to the signal output terminal.

[0044] The shift register further includes a cascaded sub-circuit configured to output a clock signal through the cascaded signal terminal in response to the potential of the pull-up node.

[0045] The cascaded sub-circuit includes a thirteenth transistor;

[0046] The first terminal of the thirteenth transistor is connected to the clock signal terminal, the second terminal is connected to the cascade signal terminal, and the control terminal is connected to the pull-up node.

[0047] The shift register further includes two third noise reduction sub-circuits;

[0048] One of the two third noise reduction sub-circuits is configured to reduce noise at the output of the cascaded signal terminal by a non-working level signal in response to the control of the first pull-down node; the other is configured to reduce noise at the output of the cascaded signal terminal by a non-working level signal in response to the control of the second pull-down node.

[0049] The first pull-down control sub-circuit and the second pull-down control sub-circuit both include a fifth transistor and a ninth transistor;

[0050] For the first pull-down control sub-circuit, the first terminal of the fifth transistor is connected to the first terminal of the ninth transistor, the control terminal of the ninth transistor, and the first power supply voltage terminal, and the second terminal is connected to the first pull-down node;

[0051] For the second pull-down control sub-circuit, the first terminal of the fifth transistor is connected to the first terminal of the ninth transistor, the control terminal of the ninth transistor, and the second power supply voltage terminal, and the second terminal is connected to the second pull-down node.

[0052] The first pull-down circuit and the second pull-down circuit each include a sixth transistor and an eighth transistor;

[0053] For the first pull-down sub-circuit, the first terminal of the sixth transistor is connected to the first pull-down node, the second terminal is connected to the non-working level signal terminal, and the control terminal is connected to the pull-up node; the first terminal of the eighth transistor is connected to the control terminal of the fifth transistor and the first terminal of the ninth transistor, the second terminal is connected to the non-working level signal terminal, and the control terminal is connected to the pull-up node;

[0054] For the second pull-down sub-circuit, the first terminal of the sixth transistor is connected to the second pull-down node, the second terminal is connected to the non-working level signal terminal, and the control terminal is connected to the pull-up node; the first terminal of the eighth transistor is connected to the control terminal of the fifth transistor and the first terminal of the ninth transistor, the second terminal is connected to the non-working level signal terminal, and the control terminal is connected to the pull-up node.

[0055] Both the first pull-down control sub-circuit and the second pull-down control sub-circuit include a fifth transistor;

[0056] For the first pull-down control sub-circuit, the first terminal and control terminal of the fifth transistor are connected to the first power supply voltage terminal, and the second terminal is connected to the first pull-down node;

[0057] In the first pull-down control sub-circuit, the first terminal and the control terminal of the fifth transistor are connected to the second power supply voltage terminal, and the second terminal is connected to the second pull-down node.

[0058] Both the first pull-down sub-circuit and the second pull-down sub-circuit include a sixth transistor;

[0059] The first terminal of the sixth transistor is connected to the first pull-down node, the second terminal is connected to the non-working level signal terminal, and the control terminal is connected to the pull-up node;

[0060] The first terminal of the sixth transistor is connected to the second pull-down node, the second terminal is connected to the non-working level signal terminal, and the control terminal is connected to the pull-up node.

[0061] This disclosure provides a gate driving circuit that includes a plurality of cascaded shift registers, wherein the shift registers are any of the shift registers described above.

[0062] This disclosure provides a display device including a plurality of intersecting gate lines and a plurality of data lines, a pixel unit disposed at the intersection of the gate lines and the data lines, and a gate driving circuit for providing gate driving signals to the gate lines, the gate driving circuit including the gate driving circuit described above. Attached Figure Description

[0063] Figure 1 is a circuit diagram of an exemplary shift register.

[0064] Figure 2a is the timing diagram of the shift register shown in Figure 1.

[0065] Figure 2b shows the potential simulation diagram of the first and second pull-down nodes when the VDDO and VDDE high and low level signals switch.

[0066] Figure 3 is a circuit diagram of a first exemplary shift register according to an embodiment of this disclosure.

[0067] Figure 4 is a circuit diagram of a second exemplary shift register according to an embodiment of this disclosure.

[0068] Figure 5 is a circuit diagram of a third exemplary shift register according to an embodiment of this disclosure.

[0069] Figure 6 is a circuit diagram of a fourth exemplary shift register according to an embodiment of this disclosure.

[0070] Figure 7 is a circuit diagram of a fifth exemplary shift register according to an embodiment of this disclosure.

[0071] Figure 8 is a circuit diagram of a sixth exemplary shift register according to an embodiment of this disclosure.

[0072] Figure 9 is a circuit diagram of a seventh exemplary shift register according to an embodiment of this disclosure.

[0073] Figure 10 is a circuit diagram of an eighth exemplary shift register according to an embodiment of this disclosure.

[0074] Figure 11 is a circuit diagram of a ninth exemplary shift register according to an embodiment of this disclosure.

[0075] Figure 12 is a circuit diagram of a tenth exemplary shift register according to an embodiment of the present disclosure.

[0076] Figure 13 is a circuit diagram of an eleventh exemplary shift register according to an embodiment of the present disclosure.

[0077] Figure 14 is a circuit diagram of a twelfth exemplary shift register according to an embodiment of the present disclosure.

[0078] Figure 15 is a circuit diagram of the thirteenth exemplary shift register according to an embodiment of the present disclosure.

[0079] Figure 16 is a circuit diagram of the fourteenth exemplary shift register according to an embodiment of the present disclosure.

[0080] Figure 17 is a circuit diagram of the fifteenth exemplary shift register according to an embodiment of the present disclosure.

[0081] Figure 18 is a circuit diagram of the sixteenth exemplary shift register according to an embodiment of the present disclosure. Detailed Implementation

[0082] To enable those skilled in the art to better understand the technical solution of this utility model, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0083] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0084] Figure 1 is a circuit diagram of an exemplary shift register. As shown in Figure 1, the shift register includes an input sub-circuit 1, an output sub-circuit 3, a pull-up reset sub-circuit 2, a global reset sub-circuit 6, two pull-down control sub-circuits 41 / 42, two pull-down sub-circuits 51 / 52, two first noise reduction sub-circuits 71 / 72, and two second noise reduction sub-circuits 81 / 82. For ease of description, the two pull-down control sub-circuits 41 / 42 are referred to as the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42, respectively, and the two pull-down sub-circuits 51 / 52 are referred to as the first pull-down circuit 51 and the second pull-down circuit 52, respectively. The first pull-down control sub-circuit 41 and the first pull-down circuit 51 are connected, and the connection node between them is called the first pull-down node PD1; the second pull-down control sub-circuit 42 and the second pull-down circuit 52 are connected, and the connection node between them is called the second pull-down node PD2.

[0085] Referring again to Figure 1, input sub-circuit 1 is configured to respond to an input signal and pre-charge the pull-up node PU via the input signal. Output sub-circuit 3 is configured to output a clock signal through the signal output terminal G(N) in response to the potential of the pull-up node PU. Pull-up reset sub-circuit 2 is configured to reset the pull-up node PU via a low-level signal under the control of the pull-up reset signal. Global reset sub-circuit 6 is configured to reset the pull-up node PU and the signal output terminal G(N) via a low-level signal in response to a global reset signal. Output sub-circuit 3 is configured to output a clock signal through the signal output terminal G(N) in response to the potential of the pull-up node PU. First pull-down control sub-circuit 41 is configured to respond to a first power supply voltage signal and control the potential of the first pull-down node PD1 via the first power supply voltage signal. Second pull-down control sub-circuit 42 is configured to respond to a second power supply voltage signal and control the potential of the second pull-down node PD2 via the second power supply voltage signal. The first pull-down sub-circuit 51 is configured to respond to the potential of the pull-up node PU by pulling down the potential of the first pull-down node PD1 with a low-level signal. The second pull-down sub-circuit 52 is configured to respond to the potential of the pull-up node PU by pulling down the potential of the second pull-down node PD2 with a low-level signal. One of the two first noise reduction sub-circuits 71 responds to the potential of the first pull-down node PD1 by performing noise reduction on the output of the pull-up node PU with a low-level signal, and the other 72 responds to the potential of the second pull-down node PD2 by performing noise reduction on the output of the pull-up node PU with a low-level signal. One of the two second noise reduction sub-circuits 81 responds to the potential of the first pull-down node PD1 by performing noise reduction on the output of the signal output terminal G(N) with a low-level signal, and the other 82 responds to the potential of the second pull-down node PD2 by performing noise reduction on the output of the signal output terminal G(N) with a low-level signal.

[0086] Specifically, continuing with reference to 1, the input sub-circuit 1 includes a first transistor M1, the pull-up reset sub-circuit 2 includes a second transistor M2, the output sub-circuit 3 includes a third transistor M3 and a storage capacitor C1, the global reset sub-circuit 6 includes a fourth transistor M4 and a seventh transistor M7, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 both include a fifth transistor and a ninth transistor, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 both include a sixth transistor and an eighth transistor, each first noise reduction sub-circuit includes a tenth transistor, and each second noise reduction sub-circuit includes an eleventh transistor. For ease of description, the fifth and ninth transistors in the first pull-down control sub-circuit 41 are represented by M5A and M9A, respectively; the fifth and ninth transistors in the second pull-down sub-circuit 52 are represented by M5B and M9B, respectively; the sixth and eighth transistors in the first pull-down sub-circuit 51 are represented by M6A and M8A, respectively; the sixth and eighth transistors in the second pull-down sub-circuit 52 are represented by M6B and M8B, respectively; the tenth transistors in the two first noise reduction sub-circuits are represented by M10A and M10B, respectively; and the eleventh transistors in the two second noise reduction sub-circuits are represented by M11A and M11B, respectively.

[0087] In this configuration, the source and gate of M1 are connected to the signal input terminal, and the drain of M1 is connected to the pull-up node PU. The source of M2 is connected to the pull-up node PU, the drain of M2 is connected to the low-level signal terminal VGL, and the gate of M2 is connected to the pull-up reset signal terminal. The source of M3 is connected to the clock signal terminal CLK, the drain of M3 is connected to the signal output terminal G(N), and the gate of M3 is connected to the pull-up node PU. The first terminal of C1 is connected to the pull-up node PU, and the second terminal of C1 is connected to the signal output terminal G(N). The source of M4 is connected to the pull-up node PU, the drain of M4 is connected to the low-level signal terminal VGL, and the gate of M4 is connected to the global reset signal terminal. The source of M7 is connected to the signal output terminal G(N), the drain of M7 is connected to the low-level signal terminal VGL, and the gate of M7 is connected to the global reset signal terminal. The source of M5A is connected to the first power supply voltage terminal VDDO, the drain of M5A is connected to the first pull-down node PD1, and the gate of M5A is connected to the drain of M9A. The source and gate of M9A are both connected to the first power supply voltage terminal VDDO. The source of M5B is connected to the second power supply voltage terminal VDDE, the drain of M5B is connected to the second pull-down node PD2, and the gate of M5B is connected to the drain of M9B. The source and gate of M9B are both connected to the second power supply voltage terminal VDDE. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M8A is connected to the drain of M9A and the gate of M5A, the drain of M8A is connected to the low-level signal terminal VGL, and the gate of M8A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU. The source of M8B is connected to the drain of M9B and the gate of M5B. The drain of M8B is connected to the low-level signal terminal VGL, and the gate of M8B is connected to the pull-up node PU. The source of M10A is connected to the pull-up node PU, the drain of M10A is connected to the low-level signal terminal VGL, and the gate of M10A is connected to the first pull-down node PD1. The source of M10B is connected to the pull-up node PU, the drain of M10B is connected to the low-level signal terminal VGL, and the gate of M10B is connected to the second pull-down node PD2. The source of M11A is connected to the signal output terminal G(N), the drain of M11A is connected to the low-level signal terminal VGL, and the gate of M11A is connected to the first pull-down node PD1. The source of M11B is connected to the signal output terminal G(N), the drain of M11B is connected to the low-level signal terminal VGL, and the gate of M11B is connected to the second pull-down node PD2.

[0088] It should be noted that in this embodiment, the input sub-circuit 1 only responds to the input signal and pre-charges the pull-up node PU through the input signal. In practical applications, the input sub-circuit 1 can also respond to the input signal and pre-charge the pull-up node PU through an independent first signal. Correspondingly, the source of M1 in the input sub-circuit 1 may not be connected to its gate. For example, the source of M1 can be connected to the first signal terminal, the drain of M1 can be connected to the pull-up node PU, and the gate of M1 can be connected to the signal input terminal. In this case, a high-level signal is written to the signal input terminal, M1 is turned on, and the high-level signal written to the first signal terminal pre-charges the pull-up node PU. In this embodiment, only the example of the source and gate of M1 being connected together is used for illustration, but it should be understood that this does not constitute a limitation on the scope of protection of this embodiment.

[0089] When the shift registers in the embodiments of this disclosure are applied to the gate drive circuit, except for the first-stage shift register, the signal input terminal of the Nth-stage shift register is connected to the signal output terminal G(N-1) of the (N-1)th-stage shift register; except for the last-stage shift register, the pull-up reset signal terminal of the Nth-stage shift register is connected to the signal output terminal G(N+1) of the (N+1)th-stage shift register. N≥2, and N is an integer.

[0090] Figure 2a is the timing diagram of the shift register shown in Figure 1. As shown in Figure 2, when the gate drive circuit is working, when G(N-1) is a high-level signal and the signals input to G(N+1) and the global reset signal terminal are low-level signals, M1 is turned on and M2 is turned off. The pull-up node PU starts charging. When the pull-up node PU is a high-level signal, M6A, M6B, M8A and M8B are turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to low-level signals to ensure that the pull-up node PU remains a high-level signal for normal output. However, during the blanking time between T1 and T3, at time T2, when the first power supply voltage terminal VDDO and the second power supply voltage terminal VDDE switch between high and low level signals, the first power supply voltage of the first power supply voltage terminal VDDO switches from a low level signal to a high level signal, and the second power supply voltage of the second power supply voltage terminal VDDE switches from a high level signal to a low level signal. M5A and M9A are turned on, the first pull-down node PD1 rises to a high potential, M5A and M9A are turned off, and the second pull-down node PD2 is floating. Alternatively, when the first power supply voltage of the first power supply voltage terminal VDDO switches from a high level signal to a low level signal, and the second power supply voltage of the second power supply voltage terminal VDDE switches from a low level signal to a high level signal, M5B and M9B are turned on, the second pull-down node PD2 rises to a high potential, M5A and M9A are turned off, and the first pull-down node PD1 is floating. During the time period T2 to T4, one of the first pull-down node PD1 and the second pull-down node PD2 is a high-level signal, while the other is in a floating state. The voltage of the pull-down node signal in the floating state cannot be pulled down quickly, and the voltage remains high, as shown in Figure 2b. With both the first pull-down node PD1 and the second pull-down node PD2 operating at high potentials simultaneously, the pull-up node PU is continuously discharged through M10, causing PU to be continuously pulled low. This results in no output from the gate drive circuit for this row, leading to black lines or screen flickering.

[0091] To address the aforementioned issues, this embodiment adds a first auxiliary sub-circuit and a second auxiliary sub-circuit to the shift register described above. The first auxiliary sub-circuit is configured to pull down the potential of the first pull-down node through the first power supply voltage when the second power supply voltage is a high-level signal and the first power supply voltage is a low-level signal; the second auxiliary sub-circuit is configured to pull down the potential of the second pull-down node through the second power supply voltage when the first power supply voltage is a high-level signal and the second power supply voltage is a low-level signal.

[0092] Since the second power supply voltage is a high-level signal, the second pull-down node is also a high-level signal. At this time, the first auxiliary sub-circuit pulls the first pull-down sub-circuit down to a low-level signal. In this way, before the pull-up node is charged, it can be ensured that the first pull-down node and the second pull-down node are not simultaneously at a high-level signal, which helps to improve the charging capability of the pull-up node.

[0093] Next, the technical solutions of the embodiments of this disclosure will be described in detail with reference to specific examples.

[0094] First Example: Figure 3 is a circuit diagram of a shift register according to a first example of the present disclosure. As shown in Figure 3, the shift register includes a first input sub-circuit 11, a pull-up reset sub-circuit 2, an output sub-circuit 3, a global reset sub-circuit 6, a first pull-down control sub-circuit 41, a second pull-down control sub-circuit 42, a first pull-down sub-circuit 51, a second pull-down sub-circuit 52, a first auxiliary sub-circuit 91, and a second auxiliary sub-circuit 92. The first input sub-circuit 11 is configured to pre-charge the pull-up node PU in response to a first input signal. The output sub-circuit 3 is configured to output a clock signal through the signal output terminal G(N) in response to the potential of the pull-up node PU. The pull-up reset sub-circuit 2 is configured to reset the output of the pull-up node through a low-level signal in response to a pull-up reset signal. The global reset sub-circuit 6 is configured to globally reset the output of the pull-up node PU and the signal output terminal G(N) through a low-level signal in response to a global reset signal. The first pull-down control sub-circuit 41 is configured to respond to a first power supply voltage and control the potential of the first pull-down node PD1 via the first power supply voltage. The second pull-down control sub-circuit 42 is configured to respond to a second power supply voltage and control the potential of the second pull-down node PD2 via the second power supply voltage. The first pull-down sub-circuit 51 is configured to respond to the potential of the pull-up node and pull down the potential of the first pull-down node PD1 via a low-level signal. The second pull-down sub-circuit 52 is configured to respond to the potential of the pull-up node and pull down the potential of the second pull-down node PD2 via a low-level signal. The first auxiliary sub-circuit 91 is specifically configured to, when the second power supply voltage is a high-level signal and the first power supply voltage is a low-level signal, respond to the second power supply voltage and pull down the potential of the first pull-down node PD1 via the first power supply voltage. The second auxiliary sub-circuit 92 is specifically configured to, when the first power supply voltage is a high-level signal and the second power supply voltage is a low-level signal, respond to the first power supply voltage and pull down the potential of the second pull-down node PD2 via the second power supply voltage.

[0095] In this example, by adding a first auxiliary sub-circuit 91 and a second auxiliary sub-circuit 92, when the second pull-down control sub-circuit 42 is working, that is, when the second power supply voltage changes from a low-level signal to a high-level signal and the first power supply voltage changes from a high-level signal to a low-level signal, before the pull-up node is charged, the first auxiliary sub-circuit 91 is controlled to work by the second power supply voltage, and the first pull-down node PD1 is pulled down by the first power supply voltage, so that the potentials of the first pull-down node PD1 and the second pull-down node PD2 no longer appear at a high level at the same time. Only the potentials of the second pull-down node PD2 and the pull-up node PU compete, which helps to improve the charging capability of the pull-up node. Similarly, when the first pull-down control sub-circuit 41 is working—that is, when the first power supply voltage changes from a low-level signal to a high-level signal and the second power supply voltage changes from a high-level signal to a low-level signal—the second auxiliary sub-circuit 92 is controlled by the first power supply voltage to pull down the second pull-down node PD2, so that the potentials of the first pull-down node PD1 and the second pull-down node PD2 no longer simultaneously reach a high level. Only the potentials of the first pull-down node PD1 and the pull-up node PU compete, which helps to improve the charging capability of the pull-up node. In addition, in this example, the first auxiliary sub-circuit 91 is controlled by the second power supply voltage, and the second auxiliary sub-circuit 92 is controlled by the first power supply voltage. That is, for the entire shift register, the control signal is not increased by adding the first auxiliary sub-circuit 91 and the second auxiliary sub-circuit 92, so the control of this shift register is relatively simple.

[0096] Referring again to Figure 3, when the shift register in this embodiment is applied to the gate drive circuit, except for the first-stage shift register, the first input signal terminal of the Nth-stage shift register is connected to the signal output terminal G(N-1) of the (N-1)th-stage shift register; except for the last-stage shift register, the pull-up reset signal terminal of the Nth-stage shift register is connected to the signal output terminal G(N+1) of the (N+1)th-stage shift register. N ≥ 2, and N is an integer.

[0097] In some examples, continuing to refer to Figure 3, both the first auxiliary sub-circuit 91 and the second auxiliary sub-circuit 92 include a seventeenth transistor. For ease of description, the seventeenth transistor in the first auxiliary sub-circuit 91 is denoted as M17A, and the seventeenth transistor in the second auxiliary sub-circuit 92 is denoted as M17B. The source of M17A is connected to the first power supply voltage terminal VDDO, the drain of M17A is connected to the first pull-down node PD1, and the gate of M17A is connected to the second power supply voltage terminal VDDE. The source of M17B is connected to the second power supply voltage terminal VDDE, the drain of M17B is connected to the second pull-down node PD2, and the gate of M17B is connected to the first power supply voltage terminal VDDO.

[0098] Specifically, the first power supply voltage terminal VDDO is used to introduce the first power supply voltage, and the second power supply voltage terminal VDDE is used to introduce the second power supply voltage. When the second power supply voltage at the second power supply voltage terminal VDDE changes from low to high, the first power supply voltage at the first power supply voltage terminal VDDO changes from high to low. At this time, since the second power supply voltage is a high-level signal, M17A is turned on, and the first power supply voltage is low, pulling the potential of the first pull-down node PD1 low. Similarly, when the first power supply voltage at the first power supply voltage terminal VDDO changes from low to high, the second power supply voltage at the second power supply voltage terminal VDDE changes from high to low. At this time, since the first power supply voltage is a high-level signal, M17B is turned on, and the second power supply voltage is low, pulling the potential of the second pull-down node PD2 low. This example effectively avoids the competition between the pull-up node and the first pull-down node PD1 / second pull-down node PD2.

[0099] In some examples, continuing to refer to Figure 3, the global reset sub-circuit 6 includes a fourth transistor M4 and a seventh transistor M7; the source of M4 is connected to the pull-up node PU, the drain of M4 is connected to the low-level signal terminal VGL, and the gate of M4 is connected to the global reset signal terminal STV0. The source of M7 is connected to the signal output terminal G(N), the drain of M7 is connected to the low-level signal terminal VGL, and the gate of M7 is connected to the global reset signal terminal STV0.

[0100] Specifically, during the global reset phase, the global reset signal written to the global reset signal terminal STV0 is a high-level signal, and both the fourth transistor M4 and the seventh transistor M7 are turned on. At this time, the low-level signal written to the low-level signal terminal VGL resets the pull-up node PU through the fourth transistor M4 and resets the signal output terminal G(N) through the seventh transistor M7.

[0101] In some examples, continuing to refer to Figure 3, the shift register further includes two first noise reduction sub-circuits 71 / 72 and two second noise reduction sub-circuits 81 / 82. One of the two first noise reduction sub-circuits 71 / 72 (71) responds to the potential of the first pull-down node PD1 by reducing the noise of the output of the pull-up node PU by a low-level signal, and the other (72) responds to the potential of the second pull-down node PD2 by reducing the noise of the output of the pull-up node PU by a low-level signal. One of the two second noise reduction sub-circuits 81 / 82 (81) responds to the potential of the first pull-down node PD1 by reducing the noise of the output of the signal output terminal G(N) by a low-level signal, and the other (82) responds to the potential of the second pull-down node PD2 by reducing the noise of the output of the signal output terminal G(N) by a low-level signal.

[0102] Each of the two first noise reduction sub-circuits 71 / 72 includes a tenth transistor, and each of the two second noise reduction sub-circuits 81 / 82 includes an eleventh transistor. The tenth transistors in the two first noise reduction sub-circuits 71 / 72 are denoted as M10A and M10B, respectively; the eleventh transistors in the two second noise reduction sub-circuits 81 / 82 are denoted as M11A and M11B, respectively. The source of M10A is connected to the pull-up node PU, the drain of M10A is connected to the low-level signal terminal VGL, and the gate of M10A is connected to the first pull-down node PD1. The source of M10B is connected to the pull-up node PU, the drain of M10B is connected to the low-level signal terminal VGL, and the gate of M10B is connected to the second pull-down node PD2. The source of M11A is connected to the signal output terminal G(N), the drain of M11A is connected to the low-level signal terminal VGL, and the gate of M11A is connected to the first pull-down node PD1. The source of M11B is connected to the signal output terminal G(N), the drain of M11B is connected to the low-level signal terminal VGL, and the gate of M11B is connected to the second pull-down node PD2.

[0103] Specifically, during the output noise reduction stage, when the potential of the first pull-down node PD1 is high, M10A and M11A are turned on, and the low-level signal written to the low-level signal terminal VGL pulls down the potential of the pull-up node PU and the signal output terminal G(N). When the potential of the second pull-down node PD2 is high, M10B and M11B are turned on, and the low-level signal written to the low-level signal terminal VGL pulls down the potential of the pull-up node PU and the signal output terminal G(N).

[0104] In some examples, the first input sub-circuit 11 includes a first transistor M1; the second input sub-circuit 12 includes a second transistor M2; wherein the source and gate of M1 are connected to the first input signal terminal G(N-1), the drain of M1 is connected to the pull-up node PU, the source of M2 is connected to the pull-up node PU, the drain of M2 is connected to the low-level signal terminal VGL, and the gate of M2 is connected to the pull-up reset signal terminal G(N+1).

[0105] Specifically, during the input phase, the first input signal written to the first input signal terminal G(N-1) is a high-level signal, and M1 is turned on. At this time, the pull-up node PU is pre-charged through the high-level signal. During the pull-up reset phase, the pull-up reset signal written to the pull-up reset signal terminal G(N+1) is a high-level signal, and M2 is turned on. At this time, the pull-up node PU is discharged through the low-level signal, thereby realizing the reset of the pull-up node PU.

[0106] In some examples, the output sub-circuit 3 includes a third transistor M3 and a storage capacitor C1; wherein, the source of M3 is connected to the clock signal terminal CLK, the drain of M3 is connected to the signal output terminal G(N), and the gate of M3 is connected to the pull-up node PU; the first end of C1 is connected to the pull-up node PU, and the second end of C1 is connected to the signal output terminal G(N).

[0107] Specifically, during the output phase, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M3 is fully turned on, and the clock signal written by the clock signal terminal CLK is a high-level signal during this phase. At this time, the signal output terminal G(N) outputs a high-level signal.

[0108] In some examples, both the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 include a fifth transistor and a ninth transistor. For ease of description, the fifth and ninth transistors in the first pull-down control subcircuit 41 are represented as M5A and M9A, respectively, and the fifth and ninth transistors in the second pull-down subcircuit 52 are represented as M5B and M9B, respectively. The source of M5A is connected to the first power supply voltage terminal VDDO, the drain of M5A is connected to the first pull-down node PD1, the gate of M5A is connected to the drain of M9A, and the source and gate of M9A are connected to the second power supply voltage terminal VDDE. The source of M5B is connected to the second power supply voltage terminal VDDE, the drain of M5B is connected to the second pull-down node PD2, the gate of M5B is connected to the drain of M9B, and the source and gate of M9B are connected to the second power supply voltage terminal VDDE.

[0109] Specifically, when the first power supply voltage terminal VDDO is written with the first power supply voltage, both M5A and M9A are turned on, and the potential of the first pull-down node PD1 is pulled high by the first power supply voltage, i.e., it is at a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, both MB5 and M9B are turned on, and the potential of the second pull-down node PD2 is pulled high by the second power supply voltage, i.e., it is at a high potential. It should be noted that the first power supply voltage and the second power supply voltage can be the same power supply voltage. In this embodiment of the disclosure, only the example of the first power supply voltage and the second power supply voltage being the same power supply voltage is described.

[0110] In some examples, both the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 include a sixth transistor and an eighth transistor. For ease of description, the sixth and eighth transistors in the first pull-down sub-circuit 51 are denoted as M6A and M8A, respectively, and the sixth and eighth transistors in the second pull-down sub-circuit 52 are denoted as M6B and M8B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M8A is connected to the drain of M9A and the gate of M5A, the drain of M8A is connected to the low-level signal terminal VGL, and the gate of M8A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU. The source of M8B is connected to the drain of M9B and the gate of M5B. The drain of M8B is connected to the low-level signal terminal VGL, and the gate of M8B is connected to the pull-up node PU.

[0111] Specifically, when the potential of the pull-up node PU is high, M6A and M6B / M8A / M8B are turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to low, ensuring that the pull-up node PU remains high for normal output.

[0112] The second example: Figure 4 is a circuit diagram of the shift register of the second example of the present disclosure; as shown in Figure 4, the structure of the shift register of this example is roughly the same as that of the first example, the only difference is that the specific structure of the first pull-down control sub-circuit 41, the second pull-down control sub-circuit 42, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 is different from that of the first example.

[0113] Specifically, in this example, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 include a fifth transistor. For ease of description, the fifth transistors in the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 are represented by M5A and M5B, respectively. The gate and source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0114] Specifically, when the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power supply voltage, i.e., a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power supply voltage, i.e., a high potential.

[0115] In this example, both the first pull-down circuit 51 and the second pull-down circuit 52 include a sixth transistor. For ease of description, the sixth transistors in the first pull-down circuit 51 and the second pull-down circuit 52 are represented by M6A and M6B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0116] Specifically, when the potential of the pull-up node PU is high, M6A and M6B are turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to low level, ensuring that the pull-up node PU remains high and outputs normally.

[0117] The other structures of the shift register in this example are the same as those in the first example, so they will not be repeated here.

[0118] The third example: Figure 5 is a circuit diagram of the shift register of the third example of the present disclosure; as shown in Figure 5, the structure of the shift register in this example is roughly the same as that in the first example, except that the shift register adds a cascaded sub-circuit 111 on the basis of the shift register in the first example. The cascaded output sub-circuit 3 is configured to output the clock signal through the cascaded signal terminal in response to the potential of the pull-up node PU.

[0119] In some examples, the cascaded sub-circuit 111 includes a thirteenth transistor M13, the source of which is connected to the clock signal terminal CLK, the drain of which is connected to the cascaded signal terminal output_C(N), and the gate of which is connected to the pull-up node PU.

[0120] Specifically, during the output phase, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M13 is fully turned on, and the clock signal written by the clock signal terminal CLK is a high-level signal during this phase. At this time, the cascade signal terminal output_C(N) outputs a high-level signal.

[0121] When the shift registers in the embodiments of this disclosure are applied to the gate drive circuit, except for the first-stage shift register, the first input signal terminal of the Nth-stage shift register is connected to the cascade signal terminal output_C(N-1) of the (N-1)th shift register; except for the last-stage shift register, the pull-up reset signal terminal of the Nth-stage shift register is connected to the cascade signal terminal output_C(N+1) of the (N+1)th shift register. N≥2, and N is an integer.

[0122] In some examples, continuing to refer to Figure 5, the shift register includes not only the structure described above, but also two third noise reduction sub-circuits. One of the third noise reduction sub-circuits is configured to pull down the output of the cascaded signal terminal by a low-level signal in response to the potential of the first pull-down node PD1. The other third noise reduction sub-circuit is configured to pull down the output of the cascaded signal terminal by a low-level signal in response to the potential of the second pull-down node PD2.

[0123] Referring again to Figure 5, both third noise reduction sub-circuits may include a twelfth transistor, denoted as M12A and M12B respectively. The source of M12A is connected to the cascaded signal terminal, the drain of M12A is connected to the low-level signal terminal VGL, and the gate of M12A is connected to the first pull-down node PD1. The source of M12B is connected to the cascaded signal terminal, the drain of M12B is connected to the low-level signal terminal VGL, and the gate of M12B is connected to the second pull-down node PD2.

[0124] Specifically, during the output noise reduction stage, when the first pull-down node PD1 is a high-level signal, M12A is turned on, and the low-level signal written to the low-level signal terminal VGL is output through the pull-down cascade signal terminal of M12A. When the second pull-down node PD2 is a high-level signal, M12B is turned on, and the low-level signal written to the low-level signal terminal VGL is output through the pull-down cascade signal terminal of M12B.

[0125] Referring again to Figure 5, the shift register in this example may further include a first discharge circuit 101 and a second discharge circuit 102; the first discharge circuit 101 is configured to discharge a first pull-down node PD1 with a low-level signal in response to a first input signal. The second discharge circuit 102 is configured to discharge a second pull-down node PD2 with a low-level signal in response to the first input signal.

[0126] Specifically, when the first input signal is written with a high-level signal, the first input sub-circuit 11 operates to pre-charge the pull-up node PU. At this time, the first pull-down node PD1 is discharged through the first discharge circuit 101, and the second pull-down node PD2 is discharged through the second discharge circuit 102, thereby avoiding potential competition between the first pull-down node PD1 and the second pull-down node PD2 and the pull-up node PU.

[0127] Both the first discharge circuit 101 and the second discharge circuit 102 may include a sixteenth transistor. For ease of description, the sixteenth transistor in the first discharge circuit 101 is denoted as M16A, and the sixteenth transistor in the second discharge circuit 102 is denoted as M16B. The source of M16A is connected to the first pull-down node PD1, the drain of M16A is connected to a low-level signal terminal, and the gate of M16A is connected to the first input signal terminal. The source of M16B is connected to the second pull-down node PD2, the drain of M16B is connected to a low-level signal terminal, and the gate of M16B is connected to the first input signal terminal.

[0128] During the input phase, the first input signal written to the first input signal terminal is a high-level signal. Both M16A and M16B are turned on. The low-level signal written through the low-level signal terminal VGL pulls down the potential of the first pull-down node PD1 and the second pull-down node PD2.

[0129] The other structures of the shift register in this example are the same as those in the first example, so they will not be repeated here.

[0130] Fourth example: Figure 6 is a circuit diagram of the shift register of the fourth example of the present disclosure; as shown in Figure 6, the structure of the shift register of this example is roughly the same as that of the third example, the only difference is that the specific structure of the first pull-down control sub-circuit 41, the second pull-down control sub-circuit 42, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 is different from that of the third example.

[0131] Specifically, in this example, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 include a fifth transistor. For ease of description, the fifth transistors in the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 are represented by M5A and M5B, respectively. The gate and source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0132] Specifically, when the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power supply voltage, i.e., a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power supply voltage, i.e., a high potential.

[0133] In this example, both the first pull-down circuit 51 and the second pull-down circuit 52 include a sixth transistor. For ease of description, the sixth transistors in the first pull-down circuit 51 and the second pull-down circuit 52 are represented by M6A and M6B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0134] Specifically, when the potential of the pull-up node PU is high, M6A and M6B are turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to low level, ensuring that the pull-up node PU remains high and outputs normally.

[0135] The other structures of the shift register in this example are the same as those in the first example, so they will not be repeated here.

[0136] Fifth Example: Figure 7 is a circuit diagram of the shift register of the fifth example of the present disclosure. As shown in Figure 7, the structure of the shift register in this example is roughly the same as that in the first example, except that the shift register can perform bidirectional scanning. The first input sub-circuit 11 and the pull-up reset sub-circuit 2 are different from those in the first example. In this example, since the shift register can perform bidirectional scanning, during forward scanning, the first input sub-circuit 11 is used for pre-charging of the pull-up node PU, and the pull-up reset sub-circuit 2 is used for resetting the pull-up node PU. During reverse scanning, the first input sub-circuit 11 is used for resetting the pull-up node PU, and the pull-up reset sub-circuit 2 is used for pre-charging of the pull-up node PU. Therefore, for ease of understanding, the first input sub-circuit 11 in the above example will still be referred to as the first input sub-circuit 11, and the pull-up reset sub-circuit 2 will be referred to as the second input sub-circuit 12. Since the first input sub-circuit 11 and the second input sub-circuit 12 are the main components used to support the shift register to achieve bidirectional scanning, the connection relationship between the first input sub-circuit 11 and the second input sub-circuit 12 and the first input sub-circuit 11 and the pull-up reset sub-circuit 2 is different.

[0137] Referring again to Figure 7, specifically, the first input sub-circuit 11 is configured to pre-charge the pull-up node PU via a first scan signal in response to a first input signal. The second input sub-circuit 12 is configured to pre-charge the pull-up node PU via a second scan signal in response to a second input signal.

[0138] In some examples, the first input sub-circuit 11 includes a first transistor M1; the second input sub-circuit 12 includes a second transistor M2; wherein the source of M1 is connected to the first scan signal terminal VDS, the drain of M1 is connected to the pull-up node PU, and the gate of M1 is connected to the first signal input terminal. The source of M2 is connected to the second scan signal terminal VSD, the drain of M2 is connected to the pull-up node PU, and the gate of M2 is connected to the second signal input terminal.

[0139] Specifically, during the forward scan, in the input phase, the first input signal written to the first input signal terminal is a high-level signal, M1 is enabled, and the first scan signal written to the first scan signal terminal VDS is a high-level signal. At this time, the pull-up node PU is pre-charged through the first scan signal. In the pull-up reset phase, the second input signal written to the second input signal terminal is a high-level signal, M2 is enabled, and the second scan signal written to the second scan signal terminal VSD is a low-level signal. At this time, the pull-up node PU is discharged through the second scan signal, thereby resetting the pull-up node PU.

[0140] During reverse scanning, in the input phase, the second input signal written to the second input signal terminal is a high-level signal, M2 is enabled, and the second scan signal written to the second scan signal terminal VSD is a high-level signal. At this time, the pull-up node PU is pre-charged through the second scan signal. In the pull-up reset phase, the first input signal written to the first input signal terminal is a high-level signal, M1 is enabled, and the first scan signal written to the first scan signal terminal VDS is a low-level signal. At this time, the pull-up node PU is discharged through the first scan signal, thereby resetting the pull-up node PU.

[0141] The other structures of the shift register in this example are the same as those in the first example, so they will not be repeated here.

[0142] Sixth Example: Figure 8 is a circuit diagram of the shift register of the sixth example of the present disclosure; as shown in Figure 8, the structure of the shift register of this example is roughly the same as that of the fifth example, the only difference being that the specific structures of the first pull-down control sub-circuit 41, the second pull-down control sub-circuit 42, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 are different from those of the fifth example.

[0143] Specifically, in this example, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 include a fifth transistor. For ease of description, the fifth transistors in the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 are represented by M5A and M5B, respectively. The gate and source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0144] Specifically, when the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power supply voltage, i.e., a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power supply voltage, i.e., a high potential.

[0145] In this example, both the first pull-down circuit 51 and the second pull-down circuit 52 include a sixth transistor. For ease of description, the sixth transistors in the first pull-down circuit 51 and the second pull-down circuit 52 are represented by M6A and M6B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0146] Specifically, when the potential of the pull-up node PU is high, M6A and M6B are turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to low level, ensuring that the pull-up node PU remains high and outputs normally.

[0147] The other structures of the shift register in this example are the same as those in the fifth example, so they will not be repeated here.

[0148] Seventh Example: Figure 9 is a circuit diagram of a shift register of the seventh example of the present disclosure; as shown in Figure 9, the structure of the shift register of this example is roughly the same as that of the fifth example, except that the shift register adds a cascaded sub-circuit 111 on the basis of the shift register of the fifth example. The cascaded output sub-circuit 3 is configured to output the clock signal through the cascaded signal terminal in response to the potential of the pull-up node PU.

[0149] In some examples, the cascaded sub-circuit 111 includes a thirteenth transistor M13, the source of which is connected to the clock signal terminal CLK, the drain of which is connected to the cascaded signal terminal output_C(N), and the gate of which is connected to the pull-up node PU.

[0150] Specifically, during the output phase, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M13 is fully turned on, and the clock signal written by the clock signal terminal CLK is a high-level signal during this phase. At this time, the cascade signal terminal output_C(N) outputs a high-level signal.

[0151] When the shift registers in the embodiments of this disclosure are applied to the gate drive circuit, except for the first-stage shift register, the first input signal terminal of the Nth-stage shift register is connected to the cascade signal terminal output_C(N-1) of the (N-1)th shift register; except for the last-stage shift register, the second input signal terminal of the Nth-stage shift register is connected to the cascade signal terminal output_C(N+1) of the (N+1)th shift register. N≥2, and N is an integer.

[0152] In some examples, the shift register includes not only the structure described above, but also two third noise reduction sub-circuits. One of the third noise reduction sub-circuits is configured to pull down the output of the cascaded signal terminal by a low-level signal in response to the potential of the first pull-down node PD1. The other third noise reduction sub-circuit is configured to pull down the output of the cascaded signal terminal by a low-level signal in response to the potential of the second pull-down node PD2.

[0153] Referring again to Figure 5, both third noise reduction sub-circuits may include a twelfth transistor, denoted as M12A and M12B respectively. The source of M12A is connected to the cascaded signal terminal, the drain of M12A is connected to the low-level signal terminal VGL, and the gate of M12A is connected to the first pull-down node PD1. The source of M12B is connected to the cascaded signal terminal, the drain of M12B is connected to the low-level signal terminal VGL, and the gate of M12B is connected to the second pull-down node PD2.

[0154] Specifically, during the output noise reduction stage, when the first pull-down node PD1 is a high-level signal, M12A is turned on, and the low-level signal written to the low-level signal terminal VGL is output through the pull-down cascade signal terminal of M12A. When the second pull-down node PD2 is a high-level signal, M12B is turned on, and the low-level signal written to the low-level signal terminal VGL is output through the pull-down cascade signal terminal of M12B.

[0155] The other structures of the shift register in this example are the same as those in the fifth example, so they will not be repeated here.

[0156] Eighth Example: Figure 10 is a circuit diagram of the shift register of the eighth example of the present disclosure; as shown in Figure 10, the structure of the shift register of this example is roughly the same as that of the seventh example, the only difference being that the specific structures of the first pull-down control sub-circuit 41, the second pull-down control sub-circuit 42, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 are different from those of the seventh example.

[0157] Specifically, in this example, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 include a fifth transistor. For ease of description, the fifth transistors in the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 are represented by M5A and M5B, respectively. The gate and source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0158] Specifically, when the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power supply voltage, i.e., a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power supply voltage, i.e., a high potential.

[0159] In this example, both the first pull-down circuit 51 and the second pull-down circuit 52 include a sixth transistor. For ease of description, the sixth transistors in the first pull-down circuit 51 and the second pull-down circuit 52 are represented by M6A and M6B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0160] Specifically, when the potential of the pull-up node PU is high, M6A and M6B are turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to low level, ensuring that the pull-up node PU remains high and outputs normally.

[0161] The other structures of the shift register in this example are the same as those in the seventh example, so they will not be repeated here.

[0162] Ninth Example: Figure 11 is a circuit diagram of a shift register according to a ninth example of the present disclosure. As shown in Figure 11, the shift register includes a first input sub-circuit 11, a pull-up reset sub-circuit 2, an output sub-circuit 3, a first pull-down control sub-circuit 41, a second pull-down control sub-circuit 42, a first pull-down sub-circuit 51, a second pull-down sub-circuit 52, a first auxiliary sub-circuit 91, and a second auxiliary sub-circuit 92. The first input sub-circuit 11 is configured to pre-charge the pull-up node PU in response to a first input signal. The output sub-circuit 3 is configured to output a clock signal through a signal output terminal in response to the potential of the pull-up node PU. The pull-up reset sub-circuit 2 is configured to reset the output of the pull-up node PU through a low-level signal in response to a pull-up reset signal. The first pull-down control sub-circuit 41 is configured to control the potential of the first pull-down node PD1 in response to a first power supply voltage. The second pull-down control sub-circuit 42 is configured to respond to the second power supply voltage and control the potential of the second pull-down node PD2 via the second power supply voltage. The first pull-down sub-circuit 51 is configured to respond to the potential of the pull-up node PU and pull down the potential of the first pull-down node PD1 via a low-level signal. The second pull-down sub-circuit 52 is configured to respond to the potential of the pull-up node PU and pull down the potential of the second pull-down node PD2 via a low-level signal. The first auxiliary sub-circuit 91 is configured to respond to the potential of the second pull-down node PD2 being high and, when the second power supply voltage is high, pull down the potential of the first pull-down node PD1 via the first power supply voltage. The second auxiliary sub-circuit 92 is configured to respond to the first pull-down node PD1 being high and, when the first power supply voltage is high, pull down the potential of the second pull-down node PD2 via the second power supply voltage.

[0163] In this example, by adding a first auxiliary sub-circuit 91 and a second auxiliary sub-circuit 92, when the second pull-down control sub-circuit 42 is working, that is, when the second power supply voltage changes from a low-level signal to a high-level signal and the first power supply voltage changes from a high-level signal to a low-level signal, before the pull-up node PU is charged (except for the first-stage shift register), the first auxiliary sub-circuit 91 is controlled to work by the potential of the second pull-down node PD2, and the first pull-down node PD1 is pulled down by a low-level signal, so that the potentials of the first pull-down node PD1 and the second pull-down node PD2 no longer appear at the same high level. Only the potentials of the second pull-down node PD2 and the pull-up node PU compete, which helps to improve the charging capability of the pull-up node PU. Similarly, when the first pull-down control sub-circuit 41 is working, that is, when the first power supply voltage is converted from a low-level signal to a high-level signal and the second power supply voltage is converted from a high-level signal to a low-level signal, before the pull-up node PU is charged, the second auxiliary sub-circuit 92 is controlled by the first pull-down node PD1 to pull down the second pull-down node PD2 by a low-level signal, so that the potentials of the first pull-down node PD1 and the second pull-down node PD2 no longer appear at the same high level. Only the potentials of the first pull-down node PD1 and the pull-up node PU compete, which helps to improve the charging capability of the pull-up node PU.

[0164] Referring again to Figure 11, when the shift register in this embodiment is applied to the gate drive circuit, except for the first-stage shift register, the first input signal terminal of the Nth-stage shift register is connected to the signal output terminal G(N-1) of the (N-1)th-stage shift register; except for the last-stage shift register, the pull-up reset signal terminal of the Nth-stage shift register is connected to the signal output terminal G(N+1) of the (N+1)th-stage shift register. N ≥ 2, and N is an integer. The first input signal terminal of the first-stage shift register and the second input signal terminal of the last-stage shift register are connected to the frame enable signal. In this example, the first auxiliary sub-circuit 91 and the second auxiliary sub-circuit 92 are controlled by the frame enable signal. That is, for the gate drive circuit, there is no increase in control signal due to the addition of the first auxiliary sub-circuit 91 and the second auxiliary sub-circuit 92. Therefore, the control of this shift register is relatively simple.

[0165] In some examples, continuing to refer to Figure 11, both the first auxiliary sub-circuit 91 and the second auxiliary sub-circuit 92 include a seventeenth transistor. For ease of description, the seventeenth transistor in the first auxiliary sub-circuit 91 is denoted as M17A, and the seventeenth transistor in the second auxiliary sub-circuit 92 is denoted as M17B. The source of M17A is connected to the first power supply voltage terminal VDDO, the drain of M17A is connected to the first pull-down node PD1, and the gate of M17A is connected to the second pull-down node PD2. The source of M17B is connected to the second power supply voltage terminal VDDE, the drain of M17B is connected to the second pull-down node, and the gate of M17B is connected to the first pull-down node PD1.

[0166] Specifically, the first power supply voltage terminal VDDO is used to introduce the first power supply voltage, and the second power supply voltage terminal VDDE is used to introduce the second power supply voltage. When the second power supply voltage at the second power supply voltage terminal VDDE changes from low to high, and the first power supply voltage at the first power supply voltage terminal VDDO changes from high to low, and the second pull-down node PD2 is a high-level signal, M17A is turned on. At this time, the first power supply voltage is low, pulling the potential of the first pull-down node PD1 low. Similarly, when the first power supply voltage at the first power supply voltage terminal VDDO changes from low to high, and the second power supply voltage at the second power supply voltage terminal VDDE changes from high to low, and the first pull-down node PD1 is a high-level signal, M17B is turned on. At this time, the second power supply voltage is low, pulling the potential of the second pull-down node PD2 low. This example can effectively avoid the competition between the pull-up node PU and the first / second pull-down nodes PD1 and PD2.

[0167] In some examples, continuing to refer to FIG11, the shift register of this disclosure embodiment further includes a global reset sub-circuit 6, which is configured to globally reset the output of the pull-up node and the signal output terminal by a low-level signal in response to a global reset signal.

[0168] The global reset sub-circuit 6 includes a fourth transistor M4 and a seventh transistor M7. The source of M4 is connected to the pull-up node PU, the drain of M4 is connected to the low-level signal terminal VGL, and the gate of M4 is connected to the global reset signal terminal STV0. The source of M7 is connected to the signal output terminal G(N), the drain of M7 is connected to the low-level signal terminal VGL, and the gate of M7 is connected to the global reset signal terminal STV0.

[0169] Specifically, during the global reset phase, the global reset signal written to the global reset signal terminal STV0 is a high-level signal, and both the fourth transistor M4 and the seventh transistor M7 are turned on. At this time, the low-level signal written to the low-level signal terminal VGL resets the pull-up node PU through the fourth transistor M4 and resets the signal output terminal G(N) through the seventh transistor M7.

[0170] In some examples, continuing to refer to Figure 11, the shift register further includes two first noise reduction sub-circuits 71 / 72 and two second noise reduction sub-circuits 81 / 82. One of the two first noise reduction sub-circuits 71 / 72 (71) responds to the potential of the first pull-down node PD1 by reducing the noise of the output of the pull-up node PU by a low-level signal, and the other (72) responds to the potential of the second pull-down node PD2 by reducing the noise of the output of the pull-up node PU by a low-level signal. One of the two second noise reduction sub-circuits 81 / 82 (81) responds to the potential of the first pull-down node PD1 by reducing the noise of the output of the signal output terminal G(N) by a low-level signal, and the other (82) responds to the potential of the second pull-down node PD2 by reducing the noise of the output of the signal output terminal G(N) by a low-level signal.

[0171] Each of the two first noise reduction sub-circuits 71 / 72 includes a tenth transistor, and each of the two second noise reduction sub-circuits 81 / 82 includes an eleventh transistor. The tenth transistors in the two first noise reduction sub-circuits are denoted as M10A and M10B, respectively; the eleventh transistors in the two second noise reduction sub-circuits are denoted as M11A and M11B, respectively. The source of M10A is connected to the pull-up node PU, the drain of M10A is connected to the low-level signal terminal VGL, and the gate of M10A is connected to the first pull-down node PD1. The source of M10B is connected to the pull-up node PU, the drain of M10B is connected to the low-level signal terminal VGL, and the gate of M10B is connected to the second pull-down node PD2. The source of M11A is connected to the signal output terminal G(N), the drain of M11A is connected to the low-level signal terminal VGL, and the gate of M11A is connected to the first pull-down node PD1. The source of M11B is connected to the signal output terminal G(N), the drain of M11B is connected to the low-level signal terminal VGL, and the gate of M11B is connected to the second pull-down node PD2.

[0172] Specifically, during the output noise reduction stage, when the potential of the first pull-down node PD1 is high, M10A and M11A are turned on, and the low-level signal written to the low-level signal terminal VGL pulls down the potential of the pull-up node PU and the signal output terminal G(N). When the potential of the second pull-down node PD2 is high, M10B and M11B are turned on, and the low-level signal written to the low-level signal terminal VGL pulls down the potential of the pull-up node PU and the signal output terminal G(N).

[0173] In some examples, the first input sub-circuit 11 includes a first transistor M1; the second input sub-circuit 12 includes a second transistor M2; wherein the source and gate of M1 are connected to the first input signal terminal, the drain of M1 is connected to the pull-up node PU, the source of M2 is connected to the pull-up node PU, the drain of M2 is connected to the low-level signal terminal VGL, and the gate of M2 is connected to the pull-up reset signal terminal.

[0174] Specifically, during the input phase, the first input signal written to the first input signal terminal is a high-level signal, and M1 is turned on. At this time, the pull-up node PU is pre-charged through the high-level signal. During the pull-up reset phase, the pull-up reset signal written to the pull-up reset signal terminal is a high-level signal, and M2 is turned on. At this time, the pull-up node PU is discharged through the low-level signal, thereby realizing the reset of the pull-up node PU.

[0175] In some examples, the output sub-circuit 3 includes a third transistor M3 and a storage capacitor C1; wherein, the source of M3 is connected to the clock signal terminal CLK, the drain of M3 is connected to the signal output terminal G(N), and the gate of M3 is connected to the pull-up node PU; the first end of C1 is connected to the pull-up node PU, and the second end of C1 is connected to the signal output terminal G(N).

[0176] Specifically, during the output phase, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M3 is fully turned on, and the clock signal written by the clock signal terminal CLK is a high-level signal during this phase. At this time, the signal output terminal G(N) outputs a high-level signal.

[0177] In some examples, both the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 include a fifth transistor and a ninth transistor. For ease of description, the fifth and ninth transistors in the first pull-down control subcircuit 41 are represented as M5A and M9A, respectively, and the fifth and ninth transistors in the second pull-down subcircuit 52 are represented as M5B and M9B, respectively. The source of M5A is connected to the first power supply voltage terminal VDDO, the drain of M5A is connected to the first pull-down node PD1, the gate of M5A is connected to the drain of M9A, and the source and gate of M9A are connected to the second power supply voltage terminal VDDE. The source of M5B is connected to the second power supply voltage terminal VDDE, the drain of M5B is connected to the second pull-down node PD2, the gate of M5B is connected to the drain of M9B, and the source and gate of M9B are connected to the second power supply voltage terminal VDDE.

[0178] Specifically, when the first power supply voltage terminal VDDO is written with the first power supply voltage, both M5A and M9A are turned on, and the potential of the first pull-down node PD1 is pulled high by the first power supply voltage, i.e., it is at a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, both MB5 and M9B are turned on, and the potential of the second pull-down node PD2 is pulled high by the second power supply voltage, i.e., it is at a high potential. It should be noted that the first power supply voltage and the second power supply voltage can be the same power supply voltage. In this embodiment of the disclosure, only the example of the first power supply voltage and the second power supply voltage being the same power supply voltage is described.

[0179] In some examples, both the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 include a sixth transistor and an eighth transistor; for ease of description, the sixth and eighth transistors in the first pull-down sub-circuit 51 are denoted as M6A and M8A, respectively, and the sixth and eighth transistors in the second pull-down sub-circuit 52 are denoted as M6B and M8B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M8A is connected to the drain of M9A and the gate of M5A, the drain of M8A is connected to the low-level signal terminal VGL, and the gate of M8A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU. The source of M8B is connected to the drain of M9B and the gate of M5B. The drain of M8B is connected to the low-level signal terminal VGL, and the gate of M8B is connected to the pull-up node PU.

[0180] Specifically, when the potential of the pull-up node PU is high, M6A, M6B, M8A and M8B are turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to low, ensuring that the pull-up node PU remains high and outputs normally.

[0181] Tenth Example: Figure 12 is a circuit diagram of the shift register of the tenth example of the present disclosure; as shown in Figure 12, the structure of the shift register of this example is roughly the same as that of the ninth example, the only difference being that the specific structures of the first pull-down control sub-circuit 41, the second pull-down control sub-circuit 42, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 are different from those of the ninth example.

[0182] Specifically, in this example, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 include a fifth transistor. For ease of description, the fifth transistors in the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 are represented by M5A and M5B, respectively. The gate and source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0183] Specifically, when the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power supply voltage, i.e., a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power supply voltage, i.e., a high potential.

[0184] In this example, both the first pull-down circuit 51 and the second pull-down circuit 52 include a sixth transistor. For ease of description, the sixth transistors in the first pull-down circuit 51 and the second pull-down circuit 52 are represented by M6A and M6B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0185] Specifically, when the potential of the pull-up node PU is high, M6A and M6B are turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to low level, ensuring that the pull-up node PU remains high and outputs normally.

[0186] The other structures of the shift register in this example are the same as those in the ninth example, so they will not be repeated here.

[0187] Eleventh Example: Figure 13 is a circuit diagram of the shift register of the eleventh example of the present disclosure; as shown in Figure 13, the structure of the shift register in this example is roughly the same as that in the ninth example, except that the shift register adds a cascaded sub-circuit 111 on the basis of the shift register in the ninth example. The cascaded output sub-circuit 3 is configured to output the clock signal through the cascaded signal terminal in response to the potential of the pull-up node PU.

[0188] In some examples, the cascaded sub-circuit 111 includes a thirteenth transistor M13, the source of which is connected to the clock signal terminal CLK, the drain of which is connected to the cascaded signal terminal output_C(N), and the gate of which is connected to the pull-up node PU.

[0189] Specifically, during the output phase, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M13 is fully turned on, and the clock signal written by the clock signal terminal CLK is a high-level signal during this phase. At this time, the cascade signal terminal output_C(N) outputs a high-level signal.

[0190] When the shift registers in the embodiments of this disclosure are applied to the gate drive circuit, except for the first-stage shift register, the first input signal terminal of the Nth-stage shift register is connected to the cascade signal terminal output_C(N-1) of the (N-1)th shift register; except for the last-stage shift register, the pull-up reset signal terminal of the Nth-stage shift register is connected to the cascade signal terminal output_C(N+1) of the (N+1)th shift register. N≥2, and N is an integer.

[0191] In some examples, continuing to refer to Figure 13, the shift register includes not only the structure described above, but also two third noise reduction sub-circuits. One of the third noise reduction sub-circuits is configured to pull down the output of the cascaded signal terminal by a low-level signal in response to the potential of the first pull-down node PD1. The other third noise reduction sub-circuit is configured to pull down the output of the cascaded signal terminal by a low-level signal in response to the potential of the second pull-down node PD2.

[0192] Referring again to Figure 13, both third noise reduction sub-circuits may include a twelfth transistor, denoted as M12A and M12B respectively. The source of M12A is connected to the cascaded signal terminal, the drain of M12A is connected to the low-level signal terminal VGL, and the gate of M12A is connected to the first pull-down node PD1. The source of M12B is connected to the cascaded signal terminal, the drain of M12B is connected to the low-level signal terminal VGL, and the gate of M12B is connected to the second pull-down node PD2.

[0193] Specifically, during the output noise reduction stage, when the first pull-down node PD1 is a high-level signal, M12A is turned on, and the low-level signal written to the low-level signal terminal VGL is output through the pull-down cascade signal terminal of M12A. When the second pull-down node PD2 is a high-level signal, M12B is turned on, and the low-level signal written to the low-level signal terminal VGL is output through the pull-down cascade signal terminal of M12B.

[0194] Referring again to Figure 13, the shift register in this example may further include a first discharge circuit 101 and a second discharge circuit 102; the first discharge circuit 101 is configured to discharge a first pull-down node PD1 via a low-level signal in response to a first input signal. The second discharge circuit 102 is configured to discharge a second pull-down node PD2 via a low-level signal in response to the first input signal.

[0195] Specifically, when the first input signal is written with a high-level signal, the first input sub-circuit 11 operates to pre-charge the pull-up node PU. At this time, the first pull-down node PD1 is discharged through the first discharge circuit 101, and the second pull-down node PD2 is discharged through the second discharge circuit 102, thereby avoiding potential competition between the first pull-down node PD1 and the second pull-down node PD2 and the pull-up node PU.

[0196] Both the first discharge circuit 101 and the second discharge circuit 102 may include a sixteenth transistor. For ease of description, the sixteenth transistor in the first discharge circuit 101 is denoted as M16A, and the sixteenth transistor in the second discharge circuit 102 is denoted as M16B. The source of M16A is connected to the first pull-down node PD1, the drain of M16A is connected to a low-level signal terminal, and the gate of M16A is connected to the first input signal terminal. The source of M16B is connected to the second pull-down node PD2, the drain of M16B is connected to a low-level signal terminal, and the gate of M16B is connected to the first input signal terminal.

[0197] During the input phase, the first input signal written to the first input signal terminal is a high-level signal. Both M16A and M16B are turned on. The low-level signal written through the low-level signal terminal VGL pulls down the potential of the first pull-down node PD1 and the second pull-down node PD2.

[0198] The other structures of the shift register in this example are the same as those in the ninth example, so they will not be repeated here.

[0199] Twelfth Example: Figure 14 is a circuit diagram of the shift register of the twelfth example of the present disclosure; as shown in Figure 14, the structure of the shift register of this example is roughly the same as that of the eleventh example, the only difference being that the specific structures of the first pull-down control sub-circuit 41, the second pull-down control sub-circuit 42, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 are different from those of the eleventh example.

[0200] Specifically, in this example, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 include a fifth transistor. For ease of description, the fifth transistors in the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 are represented by M5A and M5B, respectively. The gate and source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0201] Specifically, when the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power supply voltage, i.e., a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power supply voltage, i.e., a high potential.

[0202] In this example, both the first pull-down circuit 51 and the second pull-down circuit 52 include a sixth transistor. For ease of description, the sixth transistors in the first pull-down circuit 51 and the second pull-down circuit 52 are represented by M6A and M6B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0203] Specifically, when the potential of the pull-up node PU is high, M6A and M6B are turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to low level, ensuring that the pull-up node PU remains high and outputs normally.

[0204] The other structures of the shift register in this example are the same as those in the eleventh example, so they will not be repeated here.

[0205] Thirteenth Example: Figure 15 is a circuit diagram of the shift register of the thirteenth example of the present disclosure. As shown in Figure 15, the structure of the shift register in this example is roughly the same as that in the ninth example, except that the shift register can perform bidirectional scanning. The first input sub-circuit 11 and the pull-up reset sub-circuit 2 are different from those in the ninth example. In this example, since the shift register can perform bidirectional scanning, during forward scanning, the first input sub-circuit 11 is used for pre-charging of the pull-up node PU, and the pull-up reset sub-circuit 2 is used for resetting the pull-up node PU. During reverse scanning, the first input sub-circuit 11 is used for resetting the pull-up node PU, and the pull-up reset sub-circuit 2 is used for pre-charging of the pull-up node PU. Therefore, for ease of understanding, the first input sub-circuit 11 in the above example will still be referred to as the first input sub-circuit 11, and the pull-up reset sub-circuit 2 will be referred to as the second input sub-circuit 12. Since the first input sub-circuit 11 and the second input sub-circuit 12 are the main components used to support the shift register to achieve bidirectional scanning, the connection relationship between the first input sub-circuit 11 and the second input sub-circuit 12 and the first input sub-circuit 11 and the pull-up reset sub-circuit 2 is different.

[0206] Referring again to Figure 15, specifically, the first input sub-circuit 11 is configured to pre-charge the pull-up node PU via a first scan signal in response to a first input signal. The second input sub-circuit 12 is configured to pre-charge the pull-up node PU via a second scan signal in response to a second input signal.

[0207] In some examples, the first input sub-circuit 11 includes a first transistor M1; the second input sub-circuit 12 includes a second transistor M2; wherein the source of M1 is connected to the first scan signal terminal VDS, the drain of M1 is connected to the pull-up node PU, and the gate of M1 is connected to the first signal input terminal. The source of M2 is connected to the second scan signal terminal VSD, the drain of M2 is connected to the pull-up node PU, and the gate of M2 is connected to the second signal input terminal.

[0208] Specifically, during the forward scan, in the input phase, the first input signal written to the first input signal terminal is a high-level signal, M1 is enabled, and the first scan signal written to the first scan signal terminal VDS is a high-level signal. At this time, the pull-up node PU is pre-charged through the first scan signal. In the pull-up reset phase, the second input signal written to the second input signal terminal is a high-level signal, M2 is enabled, and the second scan signal written to the second scan signal terminal VSD is a low-level signal. At this time, the pull-up node PU is discharged through the second scan signal, thereby resetting the pull-up node PU.

[0209] During reverse scanning, in the input phase, the second input signal written to the second input signal terminal is a high-level signal, M2 is enabled, and the second scan signal written to the second scan signal terminal VSD is a high-level signal. At this time, the pull-up node PU is pre-charged through the second scan signal. In the pull-up reset phase, the first input signal written to the first input signal terminal is a high-level signal, M1 is enabled, and the first scan signal written to the first scan signal terminal VDS is a low-level signal. At this time, the pull-up node PU is discharged through the first scan signal, thereby resetting the pull-up node PU.

[0210] The other structures of the shift register in this example are the same as those in the ninth example, so they will not be repeated here.

[0211] Fourteenth Example: Figure 16 is a circuit diagram of the shift register of the fourteenth example of the present disclosure; as shown in Figure 16, the structure of the shift register of this example is roughly the same as that of the thirteenth example, the only difference being that the specific structures of the first pull-down control sub-circuit 41, the second pull-down control sub-circuit 42, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 are different from those of the thirteenth example.

[0212] Specifically, in this example, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 include a fifth transistor. For ease of description, the fifth transistors in the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 are represented by M5A and M5B, respectively. The gate and source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0213] Specifically, when the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power supply voltage, i.e., a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power supply voltage, i.e., a high potential.

[0214] In this example, both the first pull-down circuit 51 and the second pull-down circuit 52 include a sixth transistor. For ease of description, the sixth transistors in the first pull-down circuit 51 and the second pull-down circuit 52 are represented by M6A and M6B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0215] Specifically, when the potential of the pull-up node PU is high, M6A and M6B are turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to low level, ensuring that the pull-up node PU remains high and outputs normally.

[0216] The other structures of the shift register in this example are the same as those in the thirteenth example, so they will not be repeated here.

[0217] Fifteenth Example: Figure 17 is a circuit diagram of the shift register of the fifteenth example of the present disclosure; as shown in Figure 17, the structure of the shift register of this example is roughly the same as that of the fourteenth example, except that the shift register adds a cascaded sub-circuit 111 on the basis of the shift register of the fourteenth example. The cascaded output sub-circuit 3 is configured to output the clock signal through the cascaded signal terminal in response to the potential of the pull-up node PU.

[0218] In some examples, the cascaded sub-circuit 111 includes a thirteenth transistor M13, the source of which is connected to the clock signal terminal CLK, the drain of which is connected to the cascaded signal terminal output_C(N), and the gate of which is connected to the pull-up node PU.

[0219] Specifically, during the output phase, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M13 is fully turned on, and the clock signal written by the clock signal terminal CLK is a high-level signal during this phase. At this time, the cascade signal terminal output_C(N) outputs a high-level signal.

[0220] When the shift registers in the embodiments of this disclosure are applied to the gate drive circuit, except for the first-stage shift register, the first input signal terminal of the Nth-stage shift register is connected to the cascade signal terminal output_C(N-1) of the (N-1)th shift register; except for the last-stage shift register, the second input signal terminal of the Nth-stage shift register is connected to the cascade signal terminal output_C(N+1) of the (N+1)th shift register. N≥2, and N is an integer.

[0221] In some examples, the shift register includes not only the structure described above, but also two third noise reduction sub-circuits. One of the third noise reduction sub-circuits is configured to pull down the output of the cascaded signal terminal by a low-level signal in response to the potential of the first pull-down node PD1. The other third noise reduction sub-circuit is configured to pull down the output of the cascaded signal terminal by a low-level signal in response to the potential of the second pull-down node PD2.

[0222] Referring again to Figure 17, both third noise reduction sub-circuits may include a twelfth transistor, denoted as M12A and M12B respectively. The source of M12A is connected to the cascaded signal terminal, the drain of M12A is connected to the low-level signal terminal VGL, and the gate of M12A is connected to the first pull-down node PD1. The source of M12B is connected to the cascaded signal terminal, the drain of M12B is connected to the low-level signal terminal VGL, and the gate of M12B is connected to the second pull-down node PD2.

[0223] Specifically, during the output noise reduction stage, when the first pull-down node PD1 is a high-level signal, M12A is turned on, and the low-level signal written to the low-level signal terminal VGL is output through the pull-down cascade signal terminal of M12A. When the second pull-down node PD2 is a high-level signal, M12B is turned on, and the low-level signal written to the low-level signal terminal VGL is output through the pull-down cascade signal terminal of M12B.

[0224] The other structures of the shift register in this example are the same as those in the fourteenth example, so they will not be repeated here.

[0225] Sixteenth Example: Figure 18 is a circuit diagram of the shift register of the sixteenth example of the present disclosure; as shown in Figure 18, the structure of the shift register of this example is roughly the same as that of the fifteenth example, the only difference being that the specific structures of the first pull-down control sub-circuit 41, the second pull-down control sub-circuit 42, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 are different from those of the fifteenth example.

[0226] Specifically, in this example, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 include a fifth transistor. For ease of description, the fifth transistors in the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 are represented by M5A and M5B, respectively. The gate and source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0227] Specifically, when the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power supply voltage, i.e., a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power supply voltage, i.e., a high potential.

[0228] In this example, both the first pull-down circuit 51 and the second pull-down circuit 52 include a sixth transistor. For ease of description, the sixth transistors in the first pull-down circuit 51 and the second pull-down circuit 52 are represented by M6A and M6B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0229] Specifically, when the potential of the pull-up node PU is high, M6A and M6B are turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to low level, ensuring that the pull-up node PU remains high and outputs normally.

[0230] The other structures of the shift register in this example are the same as those in the fifteenth example, so they will not be repeated here.

[0231] This disclosure also provides a display device, which includes a plurality of gate lines and a plurality of data lines arranged in a cross configuration, a pixel unit disposed at the intersection of the gate lines and the data lines, and a gate driving circuit that provides gate driving signals for the gate lines, wherein the gate driving circuit includes any of the gate driving circuits described above.

[0232] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of this utility model, and the utility model is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of this utility model, and these modifications and improvements are also considered to be within the protection scope of this utility model.

Claims

1. A shift register, comprising: First input sub-circuit, output sub-circuit, first pull-down control sub-circuit, second pull-down control sub-circuit, first pull-down sub-circuit, and second pull-down sub-circuit; The first input sub-circuit is configured to pre-charge the pull-up node via a first scan signal in response to a first input signal; the output sub-circuit is configured to output a clock signal via a signal output terminal in response to the potential of the pull-up node; the first pull-down control sub-circuit is configured to control the potential of the first pull-down node via a first power supply voltage in response to the first power supply voltage. The second pull-down control sub-circuit is configured to respond to a second power supply voltage and control the potential of the second pull-down node via the second power supply voltage; the first pull-down sub-circuit is configured to pull down the first pull-down node in response to the potential of the pull-up node. The second pull-down sub-circuit, in response to the potential of the pull-up node, pulls down the second pull-down node; wherein, the shift register further includes: a first auxiliary sub-circuit and a second auxiliary sub-circuit; the first auxiliary sub-circuit is configured to pull down the potential of the first pull-down node through the first power supply voltage when the second power supply voltage is a working level signal and when the first power supply voltage is a non-working level signal; the second auxiliary sub-circuit is configured to pull down the potential of the second pull-down node through the second power supply voltage when the first power supply voltage is a working level signal and the second power supply voltage is a non-working level signal.

2. The shift register according to claim 1, wherein, The first auxiliary sub-circuit is specifically configured to, in response to the second power supply voltage, pull down the potential of the first pull-down node through the first power supply voltage when the second power supply voltage is a working level signal and the first power supply voltage is a non-working level signal; the second auxiliary sub-circuit is specifically configured to, in response to the first power supply voltage, pull down the potential of the second pull-down node through the second power supply voltage when the first power supply voltage is a working level signal and the second power supply voltage is a non-working level signal.

3. The shift register according to claim 2, wherein, Both the first auxiliary sub-circuit and the second auxiliary sub-circuit include a seventeenth transistor; the first terminal of the seventeenth transistor in the first auxiliary sub-circuit is connected to the first power supply voltage terminal, the second terminal is connected to the first pull-down node, and the control terminal is connected to the second power supply voltage terminal; the first terminal of the seventeenth transistor in the first auxiliary sub-circuit is connected to the second power supply voltage terminal, the second terminal is connected to the second pull-down node, and the control terminal is connected to the first power supply voltage terminal.

4. The shift register according to claim 1, wherein, The first auxiliary sub-circuit is specifically configured to, in response to the potential of the second pull-down node, pull down the potential of the first pull-down node through the first power supply voltage when the second power supply voltage is a working level signal and the first power supply voltage is a non-working level signal; the second auxiliary sub-circuit is specifically configured to, in response to the potential of the first pull-down node, pull down the potential of the second pull-down node through the second power supply voltage when the first power supply voltage is a working level signal and the second power supply voltage is a non-working level signal.

5. The shift register according to claim 4, wherein, Both the first auxiliary sub-circuit and the second auxiliary sub-circuit include a seventeenth transistor; the first terminal of the seventeenth transistor in the first auxiliary sub-circuit is connected to the first power supply voltage terminal, the second terminal is connected to the first pull-down node, and the control terminal is connected to the second pull-down node; In the first auxiliary sub-circuit, the first terminal of the seventeenth transistor is connected to the second power supply voltage terminal, the second terminal is connected to the second pull-down node, and the control terminal is connected to the first pull-down node.

6. The shift register according to any one of claims 1-5, wherein, It also includes a global reset sub-circuit, configured to globally reset the output of the pull-up node and the signal output terminal via a non-operating level signal in response to a global reset signal.

7. The shift register according to claim 6, wherein, The global reset sub-circuit includes a fourth transistor and a seventh transistor; the first terminal of the fourth transistor is connected to the pull-up node, the second terminal is connected to the non-working level signal terminal, and the control terminal is connected to the global reset signal terminal; the first terminal of the seventh transistor is connected to the signal output terminal, the second terminal is connected to the non-working level signal terminal, and the control terminal is connected to the global reset signal terminal.

8. The shift register according to any one of claims 1-5, wherein, It also includes a pull-up reset sub-circuit, configured to reset the output of the pull-up node by a non-operating level signal in response to a pull-up reset signal.

9. The shift register according to claim 8, wherein, The pull-up reset sub-circuit includes a second transistor, the first terminal of which is connected to the pull-up node, the second terminal of which is connected to a non-working level signal terminal, and the control terminal of which is connected to the pull-up reset signal terminal.

10. The shift register according to claim 8, wherein, The first input signal is multiplexed into the first scan signal; the first input sub-circuit includes a first transistor; the first electrode and the control electrode of the first transistor are connected to the first input signal terminal, and the second electrode is connected to the pull-up node.

11. The shift register according to any one of claims 1-5, wherein, It also includes a second input sub-circuit configured to precharge the pull-up node via a second scan signal in response to a second input signal.

12. The shift register according to claim 11, wherein, The second input sub-circuit includes a second transistor; the first terminal of the second transistor is connected to the pull-up node, the second terminal is connected to the second scan signal terminal, and the control terminal is connected to the second input signal terminal.

13. The shift register according to claim 11, wherein, The first input sub-circuit includes a first transistor; the first terminal of the first transistor is connected to the first scan signal terminal, the second terminal is connected to the pull-up node, and the control terminal is connected to the first input signal terminal.

14. The shift register according to any one of claims 1-5, wherein, It also includes two first noise reduction sub-circuits and two second noise reduction sub-circuits; one of the two first noise reduction sub-circuits is configured to respond to the potential of the first pull-down node and reduce the noise of the output of the pull-up node by a non-working level signal, and the other is configured to respond to the potential of the second pull-down node and reduce the noise of the output of the pull-up node by a non-working level signal. One of the two second noise reduction sub-circuits is configured to respond to the potential of the first pull-down node and reduce the noise of the output of the signal output terminal by a non-working level signal; the other is configured to respond to the potential of the second pull-down node and reduce the noise of the output of the signal output terminal by a non-working level signal.

15. The shift register according to claim 14, wherein, Both of the first noise reduction sub-circuits include a tenth transistor; In one of the first noise reduction sub-circuits, the first terminal of the tenth transistor is connected to the pull-up node, the second terminal is connected to the non-working voltage terminal, and the control terminal is connected to the first pull-down node; in the other first noise reduction sub-circuit, the first terminal of the tenth transistor is connected to the pull-up node, the second terminal is connected to the non-working voltage terminal, and the control terminal is connected to the second pull-down node.

16. The shift register according to claim 14, wherein, Both of the second noise reduction sub-circuits include an eleventh transistor; In one of the second noise reduction sub-circuits, the first terminal of the eleventh transistor is connected to the signal output terminal, the second terminal is connected to the non-working voltage terminal, and the control terminal is connected to the first pull-down node; in the other second noise reduction sub-circuit, the first terminal of the eleventh transistor is connected to the pull-up node, the second terminal is connected to the non-working voltage terminal, and the control terminal is connected to the signal output terminal.

17. The shift register according to any one of claims 1-5, wherein, It also includes cascaded sub-circuits configured to output a clock signal through the cascaded signal terminal in response to the potential of the pull-up node.

18. The shift register according to claim 17, wherein, The cascaded sub-circuit includes a thirteenth transistor; the first terminal of the thirteenth transistor is connected to the clock signal terminal, the second terminal is connected to the cascade signal terminal, and the control terminal is connected to the pull-up node.

19. The shift register according to claim 17, wherein, It also includes two third noise reduction sub-circuits; one of the two third noise reduction sub-circuits is configured to reduce the noise of the output of the cascaded signal terminal by a non-working level signal in response to the control of the first pull-down node. The other is configured to, in response to the control of the second pull-down node, reduce noise at the output of the cascaded signal terminal by a non-operating level signal.

20. The shift register according to any one of claims 1-5, wherein, Both the first pull-down control sub-circuit and the second pull-down control sub-circuit include a fifth transistor and a ninth transistor; for the first pull-down control sub-circuit, the first terminal of the fifth transistor is connected to the first terminal of the ninth transistor, the control terminal of the ninth transistor and the first power supply voltage terminal, and the second terminal is connected to the first pull-down node; For the second pull-down control sub-circuit, the first terminal of the fifth transistor is connected to the first terminal of the ninth transistor, the control terminal of the ninth transistor, and the second power supply voltage terminal, and the second terminal is connected to the second pull-down node.

21. The shift register according to claim 20, wherein, Both the first pull-down sub-circuit and the second pull-down sub-circuit include a sixth transistor and an eighth transistor; for the first pull-down sub-circuit, the first terminal of the sixth transistor is connected to the first pull-down node, the second terminal is connected to the non-working level signal terminal, and the control terminal is connected to the pull-up node; the first terminal of the eighth transistor is connected to the control terminal of the fifth transistor and the first terminal of the ninth transistor, the second terminal is connected to the non-working level signal terminal, and the control terminal is connected to the pull-up node; For the second pull-down sub-circuit, the first terminal of the sixth transistor is connected to the second pull-down node, the second terminal is connected to the non-working level signal terminal, and the control terminal is connected to the pull-up node; the first terminal of the eighth transistor is connected to the control terminal of the fifth transistor and the first terminal of the ninth transistor, the second terminal is connected to the non-working level signal terminal, and the control terminal is connected to the pull-up node.

22. The shift register according to any one of claims 1-5, wherein, Both the first pull-down control sub-circuit and the second pull-down control sub-circuit include a fifth transistor; for the first pull-down control sub-circuit, the first terminal and the control terminal of the fifth transistor are connected to the first power supply voltage terminal, and the second terminal is connected to the first pull-down node; for the first pull-down control sub-circuit, the first terminal and the control terminal of the fifth transistor are connected to the second power supply voltage terminal, and the second terminal is connected to the second pull-down node.

23. The shift register according to any one of claims 1-5, wherein, Both the first pull-down sub-circuit and the second pull-down sub-circuit include a sixth transistor; the first terminal of the sixth transistor is connected to the first pull-down node, the second terminal is connected to the non-working level signal terminal, and the control terminal is connected to the pull-up node; the first terminal of the sixth transistor is connected to the second pull-down node, the second terminal is connected to the non-working level signal terminal, and the control terminal is connected to the pull-up node.

24. A gate drive circuit comprising a plurality of cascaded shift registers, wherein the shift registers are any one of claims 1-23.

25. A display device comprising a plurality of gate lines and a plurality of data lines arranged in a cross configuration, pixel units disposed at the intersection of the gate lines and the data lines, and a gate driving circuit for providing gate driving signals to the gate lines, the gate driving circuit comprising the gate driving circuit of claim 24.

Images