PCB compatible with millimeter wave and high-speed digital signals

Abstract

The utility model relates to the technical field of communication, in particular to a PCB compatible with millimeter wave and high-speed digital signals. The PCB sequentially comprises a first daughter board which comprises a first core board and a second core board which are laminated; the first metal shielding hole is formed in the first daughter board and penetrates through the first daughter board; an intermediate plate including at least one metal layer; the second daughter board comprises a third core board and a fourth core board which are laminated; the second metal shielding hole is formed in the second sub-board and penetrates through the second sub-board; the first daughter board comprises a first signal line used for transmitting radio frequency signals and a second signal line used for transmitting digital signals. Or, the first daughter board comprises a first signal line used for transmitting the radio frequency signal, and the second daughter board comprises a second signal line used for transmitting the digital signal; the PCB further comprises a conductive through hole penetrating through the first daughter board, the intermediate board and the second daughter board. The intermediate plate comprises a third signal line, and the conductive through hole is connected with the third signal line.

Description

PCB board compatible with millimeter wave and high-speed digital signals Technical Field

[0001] This utility model relates to the field of communication technology, and in particular to a PCB board compatible with millimeter wave and high-speed digital signals. Background Technology

[0002] Millimeter wave technology offers greater bandwidth and lower latency compared to sub-6GHz bands, enabling higher data transmission rates and more flexible deployment in 5G communications. However, current PCBs (Printed Circuit Boards) employing millimeter wave technology face the following challenges:

[0003] 1. Due to the high signal sensitivity of millimeter-wave bands (above 20 GHz), the requirements for impedance and shielding are more stringent. Therefore, independently designed millimeter-wave circuit boards are typically used, connected to the base station motherboard (including power modules, digital modules, etc.) via connectors. This design approach increases system complexity and cost.

[0004] 2. Millimeter-wave signals have extremely high requirements for impedance and shielding during transmission and use coplanar waveguide striplines for signal transmission. To reduce transmission loss, the stripline width should be as wide as possible while meeting impedance matching requirements. Generally, the stripline is placed on the second metal layer, and a first-order blind via leads from the second metal layer to the top metal layer. The first-order blind via is a type of drilling process in PCB manufacturing, connecting the top and second metal layers through a single laser drilling operation. In existing first-order blind via processes, the aspect ratio (the ratio between the thickness of the blind via penetrating the PCB surface and the diameter of the blind via) is limited, and the dielectric thickness between the top and second metal layers is generally within 4 mils, resulting in a limited diameter for the first-order blind via. This, in turn, limits the stripline width that can match the diameter of the first-order blind via, increasing conductor loss and manufacturing tolerances. While the second-order laser blind via process can increase the stripline width, it is a blind via structure that achieves multi-layer connections through two laser drilling processes in PCB manufacturing. However, second-order laser blind holes require the use of laser technology to fabricate blind holes between the third metal layer and the top metal layer, which is complex, costly, and has limited improvement effect.

[0005] 3. Shielding vias need to span both the upper and lower reference planes of the stripline, thus obstructing the metal layer space below the stripline, wasting routing space, and increasing design and manufacturing complexity. Furthermore, other routing cannot be placed within the metal layer space below the stripline, resulting in asymmetrical distribution of metal routing on the PCB, high PCB warpage, increased manufacturing difficulty, and low yield. For example, Figure 1 shows a prior art PCB with 10 metal layers, including metal layers LB1-LB10 and dielectric layers MB1-MB9 between the metal layers. The stripline can be placed on the second metal layer LB2 or the third metal layer LB3. When the stripline is placed on the third metal layer LB3, its reference layers are the top metal layer LB1 and the fifth metal layer LB5, and a second-order blind via VB2 is used to connect the stripline and the top metal layer LB1. In this case, multiple conductive vias VB3 that run through the entire PCB board are needed as shielding vias for the stripline. This results in the entire metal layer below the fifth metal layer LB5 being divided by multiple conductive vias VB3, making it impossible to place traces in these layers (as shown in the area outlined by the dashed line in Figure 1). When the stripline is placed on the second metal layer LB2, its reference layers are the top metal layer LB1 and the third metal layer LB3, and a first-order blind via VB1 is used to connect the stripline and the top metal layer LB1. In this case, multiple second-order blind vias VB2 can be used as shielding vias, but this exacerbates the fourth problem described below.

[0006] 4. Multilayer PCBs involve multiple lamination processes, often more than four, making the process complex. This not only increases production costs but also reduces production efficiency.

[0007] In summary, existing design solutions suffer from complex processes, high losses, and high costs, which limit the optimized development of millimeter-wave base stations. A simpler and more efficient solution is urgently needed. Summary of the Invention

[0008] The purpose of this invention is to provide a PCB board compatible with millimeter wave and high-speed digital signals, and to solve the problems of complex PCB board manufacturing process, high loss and high cost.

[0009] An embodiment of this utility model discloses a PCB board compatible with millimeter wave and high-speed digital signals, comprising, in sequence:

[0010] The first sub-board includes a first core board and a second core board that are pressed together; both the first core board and the second core board include two metal layers; wherein, a first metal shielding hole is disposed in the first sub-board and penetrates through the first sub-board;

[0011] Intermediate plate, including at least one metal layer;

[0012] The second sub-board includes a laminated third core board and a fourth core board; both the third core board and the fourth core board include two metal layers; wherein, a second metal shielding hole is disposed in the second sub-board and penetrates through the second sub-board;

[0013] Wherein, the first sub-board includes a first signal line for transmitting radio frequency signals and a second signal line for transmitting digital signals; or, the first sub-board includes a first signal line for transmitting radio frequency signals and the second sub-board includes a second signal line for transmitting digital signals.

[0014] The PCB board further includes: a conductive via penetrating the first sub-board, the intermediate board, and the second sub-board; the intermediate board includes a third signal line, and the conductive via is connected to the third signal line.

[0015] The main differences and effects of this utility model embodiment compared with the prior art are as follows:

[0016] In this invention, the PCB sequentially comprises: a first sub-board, an intermediate board, and a second sub-board. The first and second sub-boards may include two or more core boards. During fabrication, the two sub-boards can be individually laminated first, and holes are prepared in each sub-board before they are laminated with the intermediate board. This reduces the number of lamination processes and lowers production costs by requiring only two lamination steps.

[0017] The first sub-board has a first metal shielding hole. Because the first metal shielding hole is located on the first sub-board and does not pass through the intermediate board or the second sub-board, it is implemented as a through-hole within the sub-board. This eliminates the need to allocate wiring space in the intermediate board and the second sub-board, improving the routing freedom in the intermediate board and the overall design flexibility and space utilization. Similarly, the second sub-board has a second metal shielding hole. Because the second metal shielding hole is located on the second sub-board and does not pass through the intermediate board or the first sub-board, it can serve as a shielding hole for the second sub-board. The shielding hole is implemented as a through-hole within the sub-board, eliminating the need to allocate wiring space in the intermediate board and the first sub-board. This improves the routing freedom in the intermediate board and the overall design flexibility and space utilization.

[0018] Because the routing of the first and second daughter boards is free, the first daughter board may include a first signal line for transmitting radio frequency signals and a second signal line for transmitting digital signals; or, the first daughter board may include a first signal line for transmitting radio frequency signals and the second daughter board may include a second signal line for transmitting digital signals, thereby enabling millimeter-wave routing and high-speed digital signal routing to be compatible on a single PCB board.

[0019] The first metal shielding hole and the second metal shielding hole are located on the first sub-board and the second sub-board, respectively, which increases the symmetry of the first sub-board and the second sub-board and reduces the board warpage.

[0020] The intermediate board includes at least one metal layer; the intermediate board includes a third signal line, and the PCB board also includes conductive vias penetrating the first sub-board, the intermediate board, and the second sub-board; the conductive vias connect to the third signal line, allowing the third signal line to be easily led out to the outer layer of the PCB board. This allows for the provision of a third signal line independent of millimeter-wave, high-speed digital signals on the intermediate board, providing more wiring channels for complex circuit designs and improving space utilization.

[0021] In some embodiments, the second metal layer of the first sub-board includes a first radio frequency (RF) signal line, which is led out to the first metal layer through a first conductive blind via. Because the first metal layer and the second metal layer are located on opposite sides of the same core board, the dielectric thickness between the first metal layer and the second metal layer can be relatively large, and the linewidth of the first RF signal line (strip line) can be relatively wide. The first conductive blind via can be fabricated using a mechanical drilling process, reducing the processing difficulty.

[0022] Furthermore, the conductive vias also penetrate the first and second sub-boards, and can be connected to signal lines (including the first signal line, the second signal line, or other signal lines) in the first and second sub-boards through the conductive vias.

[0023] The intermediate plate includes at least two metal layers, or the intermediate plate includes at least one fifth core plate, the fifth core plate including at least two metal layers; multiple of the at least two metal layers each include the third signal line; the intermediate plate also includes a first conductive through-hole, the through-hole penetrating the intermediate plate and respectively connecting to the third signal lines located in different metal layers, so as to conduct the third signal lines located in different metal layers. The first conductive through-hole can conveniently conduct the third signal lines in different metal layers. Attached Figure Description

[0024] Figure 1 shows a schematic diagram of the structure of a PCB board according to the prior art.

[0025] Figure 2 shows a schematic diagram of the structure of a PCB board according to an embodiment of this application.

[0026] Figure 3A shows a schematic diagram of the structure of the first sub-board according to an embodiment of this application.

[0027] Figure 3B shows a schematic diagram of the structure of a first sub-board according to an alternative embodiment of this application.

[0028] Figure 3C shows a schematic diagram of the structure of the first sub-board according to another alternative embodiment of this application.

[0029] Figure 4A shows a schematic diagram of the structure of the second sub-board according to an embodiment of this application.

[0030] Figure 4B shows a schematic diagram of the structure of a second sub-board according to an alternative embodiment of this application.

[0031] Figure 4C shows a schematic diagram of the structure of a second sub-board according to another alternative embodiment of this application.

[0032] Figure 5 shows a schematic diagram of the structure of a PCB board with an intermediate plate having two metal layers according to an embodiment of this application.

[0033] Figure 6A shows a schematic diagram of the structure of a PCB board with a four-layer metal intermediate board according to an embodiment of the present application.

[0034] Figure 6B shows a schematic diagram of the structure of a PCB board with a four-layer metal intermediate board according to another embodiment of this application.

[0035] Figure 7A shows a schematic diagram of the structure of a PCB board with a six-layer metal intermediate board according to an embodiment of the present application.

[0036] Figure 7B shows a schematic diagram of the structure of a PCB board with a six-layer metal intermediate board according to another embodiment of this application. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0038] Given the problems of complex manufacturing processes, high losses, and high costs associated with existing millimeter-wave base station designs, this application provides a PCB board compatible with millimeter-wave and high-speed digital signals. Figure 2 shows a schematic diagram of the structure of a PCB board 100 according to an embodiment of this application. The PCB board 100 includes a first sub-board 11, an intermediate board 12, and a second sub-board 13 stacked sequentially. The first sub-board 11 includes a first core board 111 and a second core board 112 laminated together; both the first core board 111 and the second core board 112 include two metal layers; the intermediate board 12 includes at least one metal layer Lk. The second sub-board 13 includes a third core board 131 and a fourth core board 132 laminated together. Both the third core board 131 and the fourth core board 132 include two metal layers. Metal shielding holes Vs penetrating the sub-boards are provided in both the first sub-board 11 and the second sub-board 13, wherein the metal shielding hole Vs in the first sub-board 11 is a first metal shielding hole, and the metal shielding hole Vs in the second sub-board 13 is a second metal shielding hole.

[0039] Since the first sub-board 11 and the second sub-board 13 include more than two core boards, during manufacturing, the two sub-boards can be pressed together separately first, and their respective holes can be prepared in each sub-board before being pressed together with the intermediate board. Only two pressing processes are needed, reducing the number of pressing steps and lowering production costs.

[0040] In this application, because the metal shielding holes Vs are located within their respective sub-boards and do not pass through the intermediate board 12 and the other sub-board, there is no need to allocate wiring space in the intermediate board and the other sub-board, improving the routing freedom in the intermediate board and the other sub-board, and enhancing the overall design flexibility and space utilization. The position of the metal shielding holes Vs in the sub-boards can be flexibly set, so the metal shielding holes Vs can be set symmetrically in the first sub-board and the second sub-board, increasing the symmetry of the first sub-board and the second sub-board and reducing board warpage.

[0041] The first daughterboard 11 includes a first signal line for transmitting radio frequency (RF) signals and a second signal line for transmitting digital signals (the first and second signal lines are not shown in Figure 2 for clarity; please refer to Figures 3A to 4C for their specific structures); or, the first daughterboard 11 includes a first signal line for transmitting RF signals, and the second daughterboard 13 includes a second signal line for transmitting digital signals. The RF signal can be a millimeter-wave compatible signal, and the digital signal can be a high-speed digital signal, thus enabling compatibility between millimeter-wave traces and high-speed digital signal traces on a single PCB board.

[0042] The PCB board 100 also includes a conductive via Vt that penetrates the first sub-board 11, the intermediate board 12, and the second sub-board 13. The intermediate board 12 may include a third signal line, and the conductive via Vt connects to the third signal line, serving to lead the third signal line out of the PCB board. In some embodiments, the conductive via Vt may penetrate the third signal line to achieve the connection between the conductive via Vt and the third signal line; or, the sidewall of the conductive via Vt may abut against the sidewall of the third signal line to achieve the connection between the conductive via Vt and the third signal line. Since the manufacturing process of vias is relatively simple, leading the third signal line out of the PCB board through the conductive via Vt avoids the need to use blind vias with complex manufacturing processes. The linewidth of the third signal line can be larger than the diameter of the conductive via Vt, ensuring the reliability of the conductive via fabrication and electrical connection.

[0043] The third signal line is independent of the first daughter board 11 and the second daughter board 13. It can transmit signals other than millimeter wave and high-speed digital signals, thus providing more wiring channels for complex circuit designs and improving space utilization. In some embodiments, the third signal line includes, but is not limited to, power signal lines, control signal lines (for transmitting control signals), digital signal lines (for transmitting low-speed digital signals), etc. These signals do not have high requirements for impedance, shielding, etc., and can be flexibly set in the intermediate board 12.

[0044] The first core board 111 and the second core board 112, as well as the third core board 131 and the fourth core board 132, are all bonded together using PP (Prepreg). The first sub-board 11 and the second sub-board 13 are bonded together individually before being bonded together with the intermediate board 12 to form the overall PCB board 100. In this application, the core board refers to a pre-manufactured rigid substrate having a metal layer and a dielectric layer, typically comprising two metal layers and a dielectric layer between them. For example, the core board can be a double-sided copper-clad laminate, where the two metal layers are copper foil and the intermediate dielectric layer can be epoxy resin.

[0045] As shown in Figure 2, the first sub-board 11 has a symmetrical four-layer structure, with the following stacking order from top to bottom: first metal layer L1 (also known as the Top layer), first dielectric layer M1, second metal layer L2, second dielectric layer M2, third metal layer L3, third dielectric layer M3, and fourth metal layer L4. The first core board 111 includes the first metal layer L1, first dielectric layer M1, and second metal layer L2, while the second core board 112 includes the third metal layer L3, third dielectric layer M3, and fourth metal layer L4. Optionally, the dielectric material and thickness of the first dielectric layer M1 and the third dielectric layer M3 can be the same. These materials can be ultra-low loss dielectric materials of M6 / M7 / M8 level, which have low dielectric constants, reducing delay and distortion during signal transmission and improving signal transmission speed and quality.

[0046] The second sub-board 13 has a symmetrical stacked structure with the first sub-board 11. As shown in Figure 2, the stacked order of the second sub-board 13 from top to bottom is: fifth metal layer Ln-3, fourth dielectric layer Mm-2, sixth metal layer Ln-2, ​​fifth dielectric layer Mm-1, seventh metal layer Ln-1, sixth dielectric layer Mm, and eighth metal layer Ln (also known as the bottom layer). The third core board 131 includes the fifth metal layer Ln-3, fourth dielectric layer Mm-2, and sixth metal layer Ln-2, ​​while the fourth core board 132 includes the seventh metal layer Ln-1, sixth dielectric layer Mm, and eighth metal layer Ln. Optionally, the dielectric thickness of the third core board 131 and the fourth core board 132 is the same.

[0047] In PCB board 100, radio frequency (RF) signals (millimeter-wave signals) and high-speed digital signals are transmitted within the first sub-board 11 and / or the second sub-board 13. Therefore, the dielectric layer materials in the first sub-board 11 and the second sub-board 13 are selected to be suitable for the transmission of RF signals (millimeter-wave signals) and high-speed digital signals. Specifically, the dielectric has a stable and low dielectric constant in the millimeter-wave band, for example, a dielectric constant ≤ 3.5, and a dielectric loss angle ≤ 0.004 (the dielectric loss angle refers to the ratio of the active component to the reactive component in the dielectric under AC voltage, reflecting the phase difference between the electric displacement and the electric field strength under the action of an alternating electric field, used to measure the energy loss per unit volume within the dielectric). For example, materials of M6, M7, and M8 grades are used. The selected copper foil roughness is HVLP2 or higher. The total thickness of the first sub-board 11 and the second sub-board 13 can be approximately equal, and the materials can be the same, or different materials can be selected based on actual signal performance requirements and cost considerations. In some embodiments, the dielectric constant is 1, 1.5, 2, 2.5, or 3.5, and the dielectric loss angle is 0.001, 0.002, 0.003, or 0.004.

[0048] The intermediate board is mainly used for routing secondary or non-critical signal lines and laying power planes. The requirements for the board material are relatively low. The dielectric layer can use more common and lower-cost dielectric materials, such as standard loss FR4, low loss M2, lower loss M4, and S7439C level dielectric materials. The copper foil of its metal layer can use standard copper foil.

[0049] In the embodiment shown in Figure 2, the first sub-board 11 is located above the second sub-board 13, that is, the first metal layer L1 is the top layer and the eighth metal layer Ln is the bottom layer. In some embodiments, the first sub-board 11 may also be located below the second sub-board 13, that is, the first metal layer L1 is the bottom layer and the eighth metal layer Ln is the top layer.

[0050] Figure 3A shows a schematic diagram of the structure of the first sub-board according to an embodiment of this application, wherein the first metal layer L1 is the component layer 1, and the area where no components are placed is grounded so that the first metal layer L1 serves as the reference layer for the signal lines in the second metal layer L2, thereby improving the overall EMC (Electromagnetic Compatibility) performance of the board. The second metal layer L2 includes a first signal line S1 for carrying millimeter-wave signals, and the reference ground of the first signal line S1 is the first metal layer L1 / the fourth metal layer L4. The portion of the second metal layer L2 where the first signal line S1 is not placed is grounded, serving as the adjacent ground layer of the component layer 1 and the reference layer for the signals in the third metal layer L3. For practical design needs such as impedance control and loss control, the area in the third metal layer L3 located vertically below the first signal line S1 can be hollowed out (windowed), and the hollowed-out area is shown in the dashed box in Figure 3A. A certain distance d between this hollowed-out area can be used to place the second signal line S2 for high-speed digital signals. The second signal line S2 references the second metal layer L2 / the fourth metal layer L4. The portion of the third metal layer L3 that is not hollowed out and does not have the second signal line S2 can be used for metal grounding to facilitate inter-layer shielding. The fourth metal layer L4 is a complete metal grounding layer, such as a full-layer copper grounding layer, serving as a reference layer for the first signal line S1 and the second signal line S2. Additionally, the area in the third metal layer L3 that is not hollowed out and does not have the second signal line S2 can also be used to lay secondary signal lines or power lines (or power planes), etc.

[0051] The first sub-board also includes a first conductive blind via V1 passing through the first metal layer L1, the first dielectric layer M1, and the second metal layer L2, for connecting the first metal layer L1 and the second metal layer L2, and specifically for connecting the pin P1 of the component on the first metal layer L1 and the first signal line S1 on the second metal layer L2. In this application, the pins of the components can be pins of amplifiers, switches, etc., connected to the PCB board via pads on the surface metal layer, and connected to the interior of the PCB board via metal holes through the pads. The first conductive blind via V1 can be implemented by mechanical drilling followed by electroplating (preferably, a cylindrical hole) before lamination. The first sub-board also includes a first metal shielding via V2 penetrating the entire first sub-board. Multiple first metal shielding vias V2 are arranged on both sides of the first signal line S1 and / or around the first conductive blind via V1 as shielding grounding vias. The fourth metal layer L4 serves as a ground reference layer, forming a continuous and complete ground plane coverage between the multiple first metal shielding vias V2. The first sub-board also includes a second conductive through-hole V3 that runs through the entire first sub-board, used to connect the pin P2 of the component in the first metal layer L1 to the second signal line S2 in the third metal layer L3. The first sub-board also includes a third metal shielding hole V4 that runs through the entire first sub-board, and multiple third metal shielding holes V4 are arranged on both sides of the second signal line S2 and / or around the second conductive through-hole V3 as shielding grounding holes.

[0052] Because the first metal layer and the second metal layer are located on opposite sides of the same core board, the dielectric thickness between the first metal layer and the second metal layer can be relatively large, and the linewidth of the first radio frequency signal line (strip line) can be relatively wide. The first conductive blind via can be prepared using mechanical drilling technology, reducing the processing difficulty.

[0053] Figure 3B shows a schematic diagram of the structure of a first sub-board according to an alternative embodiment of this application. Unlike the first sub-board shown in Figure 3A, when the second signal line S2 carrying a high-speed digital signal has high insertion loss requirements, the second signal line S2 can be arranged in the second metal layer L2, referencing the first metal layer L1 / fourth metal layer L4, just like the first signal line S1. For practical design needs such as impedance control and loss control, the area in the third metal layer L3 located vertically below the second signal line S2 can be hollowed out (windowed). The hollowed-out area is shown in a dashed box in Figure 3B. In this embodiment, the first signal line S1 and the second signal line S2 are arranged in the same layer, requiring a certain distance between them to spatially separate their signals; and the linewidth of the second signal line S2 is widened to effectively reduce its insertion loss. In this embodiment, the pin P2 of the component in the first metal layer L1 and the second signal line S2 on the second metal layer L2 are connected through a second conductive blind via V5. Multiple third metal shielding holes V4 are arranged on both sides of the second signal line S2 and / or around the second conductive blind hole V5 as shielding grounding holes.

[0054] Figure 3C shows a schematic diagram of the structure of a first sub-board according to another alternative embodiment of this application. Unlike the first sub-board shown in Figure 3B, the second signal line S2 of the high-speed digital signal is routed on the second metal layer L2, but references the first metal layer L1 / third metal layer L3 to free up space in the fourth metal layer L4. Therefore, except for the area directly below the first signal line S1 in the second metal layer L2, the remaining area in the fourth metal layer L4 can be used to route some secondary signal lines or power lines (or power planes).

[0055] Figure 4A shows a schematic diagram of the structure of the second sub-board according to an embodiment of this application, wherein the eighth metal layer Ln is the component layer 2. Metal grounding is laid in the area where no components are placed, so that the eighth metal layer Ln serves as a reference layer for the signal lines of the seventh metal layer Ln-1, while simultaneously improving the overall EMC performance of the board. The seventh metal layer Ln-1 is used for the sixth signal line S6 of the millimeter-wave signal, and the sixth signal line S6 references the eighth metal layer Ln / the fifth metal layer Ln-3. Metal grounding is laid in the portion of the seventh metal layer Ln-1 where the sixth signal line S6 is not placed, serving as the adjacent ground layer of component layer 2 and a reference layer for the signals of the sixth metal layer Ln-2. For practical design needs such as impedance control and loss control, the area in the sixth metal layer Ln-2 located vertically above the sixth signal line S6 is hollowed out (windowed), and the hollowed-out area is shown in a dashed box in Figure 4A. A certain distance d between this hollowed-out area can be used to lay the fourth signal line S4 of the high-speed digital signal. The fourth signal line S4 is referenced to the seventh metal layer Ln-1 / the fifth metal layer Ln-3. The portion of the sixth metal layer Ln-2 that is not hollowed out and does not have the fourth signal line S4 can be used for metal grounding to facilitate inter-layer shielding. The fifth metal layer Ln-3 is a fully laid metal ground layer, serving as the reference layer for both the sixth signal line S6 and the fourth signal line S4. Additionally, the area in the sixth metal layer Ln-2 that is not hollowed out and does not have the fourth signal line S4 can also be used to lay secondary signal lines or power lines (or power planes), etc.

[0056] The second sub-board also includes a fourth metal blind via V6 passing through the eighth metal layer Ln, the sixth dielectric layer Mn, and the seventh metal layer Ln-1, for connecting the eighth metal layer Ln and the seventh metal layer Ln-1, specifically for connecting the pin P3 of the component in the eighth metal layer Ln and the sixth signal line S6 on the seventh metal layer Ln-1. The fourth metal blind via V6 can be achieved by mechanical drilling followed by electroplating (preferably, a cylindrical hole) before lamination. The second sub-board also includes a second metal shielding via V7 penetrating the entire second sub-board, with multiple second metal shielding vias V7 arranged on both sides of the sixth signal line S6 and / or around the fourth metal blind via V6 as shielding grounding vias. The fifth metal layer Ln-3 serves as a grounding reference layer, forming a continuous and complete ground plane coverage between the multiple second metal shielding vias V7. The second sub-board also includes a third conductive through-hole V8 penetrating the entire second sub-board, for connecting the pin P4 of the component in the eighth metal layer Ln to the fourth signal line S4 in the sixth metal layer Ln-2. The second sub-board also includes a fourth metal shielding hole V9 that runs through the entire second sub-board. Multiple fourth metal shielding holes V9 are arranged on both sides of the fourth signal line S4 and / or around the third conductive through hole V8 as shielding grounding holes.

[0057] Figure 4B shows a schematic diagram of the structure of a second sub-board according to an alternative embodiment of this application. Unlike the second sub-board shown in Figure 4A, when the fourth signal line S4, which carries high-speed digital signals, has high insertion loss requirements, the fourth signal line S4 can be routed in the seventh metal layer Ln-1, referencing the eighth metal layer Ln / fifth metal layer Ln-3, just like the sixth signal line S6. For practical design needs such as impedance control and loss control, the area in the sixth metal layer Ln-2 located vertically above the fourth signal line S4 can be hollowed out (windowed). The hollowed-out area is shown in a dashed box in Figure 4B. In this embodiment, the sixth signal line S6 and the fourth signal line S4 are routed in the same layer, requiring a certain distance between them to spatially separate their signals; and by widening the linewidth of the fourth signal line S4, its insertion loss can be effectively reduced. In this embodiment, the pin P4 of the component in the eighth metal layer Ln and the fourth signal line S4 on the seventh metal layer Ln-1 are connected through a third conductive blind via V10. Multiple fourth metal shielding holes V9 are arranged on both sides of the fourth signal line S4 and / or around the third conductive blind hole V10 as shielding grounding holes.

[0058] Figure 4C shows a schematic diagram of the structure of a second sub-board according to another alternative embodiment of this application. Unlike the second sub-board shown in Figure 4B, the fourth signal line S4 of the high-speed digital signal is routed on the seventh metal layer Ln-1, but references are made to the eighth metal layer Ln / sixth metal layer Ln-2 to free up some space in the fifth metal layer Ln-3. Therefore, except for the area directly below the sixth signal line S6 in the seventh metal layer Ln-1, the remaining area in the fifth metal layer Ln-3 can be used to route some secondary signal lines or power lines (or power planes).

[0059] In some embodiments of this application, depending on actual needs, if the circuitry on the PCB is simple, the signal lines for millimeter-wave signals and high-speed digital signals can be routed only in the first daughter board. In this case, the second daughter board does not need to have the fourth metal blind via V6, the third conductive through-hole V8, and the third conductive blind via V10, or only some of them. For example, the inner layer (e.g., metal layer Ln-2) of the second daughter board may only have power lines routed, while components may be arranged on the surface metal layer (metal layer Ln) as needed. These components are connected to the power lines of the inner layer (e.g., metal layer Ln-2) using blind vias or through-holes, or connected to the intermediate board or the first daughter board using conductive vias penetrating the PCB.

[0060] Depending on the type, quantity, and characteristics of the signals that need to be routed on the second daughterboard, there are four types of holes on the second daughterboard: one is a metal blind via that connects the eighth metal layer Ln and the seventh metal layer Ln-1, and a metal through-hole that runs through the entire second daughterboard; another is a metal blind via; a third is a through-hole; and a fourth is no holes at all.

[0061] According to some embodiments of this application, the intermediate board may include two or more metal layers. When the intermediate board has two metal layers, it is composed of one core board, and the overall PCB board has 10 metal layers; when the intermediate board has four metal layers, it is composed of two core boards, and the overall PCB board has 12 layers; and so on. When the intermediate board includes at least two metal layers, multiple of the at least two metal layers may each include a third signal line; the intermediate board also includes a first conductive through-hole, penetrating the intermediate board and respectively connecting to the third signal lines located in different metal layers, thereby conducting the third signal lines located in different metal layers. The first conductive through-hole facilitates the conduction of the third signal lines in different metal layers.

[0062] In this application, the layer attributes of the intermediate board can be flexibly defined according to the signal characteristics of the actual PCB board. For example, it can be set as a ground layer, power layer, signal layer, or a mixed layer with different attributes. This application does not impose any limitations. If the PCB board is relatively complex, the number of layers of the intermediate board can be increased as needed to increase the space for routing and power layers. For example, in an intermediate board with only two metal layers, if a power layer is set, one or two metal layers can be selected as power layers according to actual needs. If only one layer is selected as a power layer, the other layer can be used to route other secondary signal lines.

[0063] The following section uses examples of 2, 4, and 6 metal layers as intermediate layers to introduce the fabrication of the overall PCB board.

[0064] Figure 5 shows a schematic diagram of the structure of a PCB board with an intermediate plate having two metal layers according to an embodiment of the present application. The PCB board 400 includes metal layers L41-L410 and dielectric layers M41-M49.

[0065] Sub-board 41 includes metal layers L41-L44 and dielectric layers M41-M43; intermediate board 42 includes metal layer L45, dielectric layer M45, and metal layer L46; sub-board 43 includes metal layers L47-L410 and dielectric layers M47-M49. Core board 411 includes metal layer L41, dielectric layer M41, and metal layer L42; core board 412 includes metal layer L43, dielectric layer M43, and metal layer L44; core board 421 includes metal layer L45, dielectric layer M45, and metal layer L46; core board 431 includes metal layer L47, dielectric layer M47, and metal layer L48; core board 432 includes metal layer L49, dielectric layer M49, and metal layer L410.

[0066] Sub-board 41 includes a through hole V41, core board 421 includes a through hole V42 (a first conductive through hole for conducting signal lines between metal layers L45 and L46), and sub-board 43 includes a through hole V43. In this embodiment, the through hole V41 corresponds to the first metal shielding hole V2 and the third metal shielding hole V4 in Figures 3A, 3B, and 3C, or the second conductive through hole V3 in Figure 3A; the through hole V43 corresponds to the second metal shielding hole V7 and the fourth metal shielding hole V9 in Figures 4A, 4B, and 4C, or the third conductive through hole V8 in Figure 4A.

[0067] In this application, a first conductive through-hole V42 penetrates the intermediate plate. When metal layers L45 and L46 each have a third signal line, the first conductive through-hole V42 conducts the third signal line in metal layers L45 and L46 to realize the transmission of signals between metal layers L45 and L46.

[0068] Figures 6A and 6B show schematic diagrams of a PCB board with a four-metal intermediate board according to an embodiment of the present application. The PCB board 500 includes metal layers L51-L512 and dielectric layers M51-M511. Sub-board 51 includes metal layers L51-L54 and dielectric layers M51-M53, intermediate board 52 includes metal layers L55-L58 and dielectric layers M55-M57, and sub-board 53 includes metal layers L59-L512 and dielectric layers M59-M511. Core board 511 includes metal layer L51, dielectric layer M51 and metal layer L52; core board 512 includes metal layer L53, dielectric layer M53 and metal layer L54; core board 521 includes metal layer L55, dielectric layer M55 and metal layer L56 of intermediate board 52; core board 522 includes metal layer L57, dielectric layer M57 and metal layer L58; core board 531 includes metal layer L59, dielectric layer M59 and metal layer L510; core board 532 includes metal layer L511, dielectric layer M511 and metal layer L512.

[0069] Figure 6A shows the through hole V51 on sub-board 51 and the through hole V53 on sub-board 53. Figure 6B also shows the through hole V52 on intermediate board 52. In this embodiment, the through hole V51 corresponds to the first metal shielding hole V2 and the third metal shielding hole V4 in Figures 3A, 3B, and 3C, or the second conductive through hole V3 in Figure 3A; the through hole V53 corresponds to the second metal shielding hole V7 and the fourth metal shielding hole V9 in Figures 4A, 4B, and 4C, or the third conductive through hole V8 in Figure 4A.

[0070] Figures 7A and 7B show schematic diagrams of a PCB board with a six-layer intermediate board according to an embodiment of the present application. The PCB board 600 includes metal layers L61-L614 and dielectric layers M61-M613. Sub-board 6 includes metal layers L61-L64 and dielectric layers M61-M631, intermediate board 62 includes metal layers L65-L610 and dielectric layers M65-M69, and sub-board 63 includes metal layers L611-L614 and dielectric layers M611-M613. Core board 611 includes metal layer L61, dielectric layer M61 and metal layer L62; core board 612 includes metal layer L63, dielectric layer M63 and metal layer L64; core board 621 includes metal layer L65, dielectric layer M65 and metal layer L66 of intermediate board 62; core board 622 includes metal layer L67, dielectric layer M67 and metal layer L68; core board 623 includes metal layer L69, dielectric layer M69 and metal layer L610; core board 631 includes metal layer L611, dielectric layer M611 and metal layer L612 in sub-board 63; core board 632 includes metal layer L613, dielectric layer M613 and metal layer L614.

[0071] Figure 7A shows the through hole V61 on sub-board 61 and the through hole V63 on sub-board 63. Figure 7B also shows the through hole V63 on intermediate plate 62. In this embodiment, the through hole V61 corresponds to the first metal shielding hole V2 and the third metal shielding hole V4 in Figures 3A, 3B, and 3C, or the second conductive through hole V3 in Figure 3A; the through hole V63 corresponds to the second metal shielding hole V7 and the fourth metal shielding hole V9 in Figures 4A, 4B, and 4C, or the third conductive through hole V8 in Figure 4A.

[0072] In the scheme of this application, the entire PCB board can be fabricated through two lamination processes:

[0073] The first pressing includes: pressing the first sub-board, pressing the second sub-board, and pressing the intermediate board (when the intermediate board is composed of multiple core boards);

[0074] The second pressing includes pressing the core board of the completed first sub-board, second sub-board, intermediate board or several intermediate boards together using PP.

[0075] After the second lamination, conductive vias that penetrate the entire PCB board can be formed through mechanical drilling, and these vias are then electroplated. These electroplated conductive vias are used to achieve signal connections between different sub-boards and intermediate boards. Because the intermediate board only has conductive vias that penetrate the entire board, the power plane is protected from being penetrated by shielding ground holes for millimeter-wave signals or high-speed digital signals, effectively increasing the power plane area and current carrying capacity.

[0076] The following describes the PCB board manufacturing process in detail, taking the PCB board 500 of Figures 6A and 6B as an example.

[0077] Referring to Figures 6A and 6B, during the fabrication of PCB board 500, the first lamination process involves bonding core boards 511 and 512 together using a prepreg (PP) layer (dielectric layer M52) to form sub-board 51. Core boards 521 and 522 are then bonded together using a prepreg (dielectric layer M56) to form intermediate board 52. Finally, core boards 531 and 532 are bonded together using a prepreg (dielectric layer M510) to form sub-board 53. After this lamination process, through holes can be drilled on sub-board 51, intermediate board 52, and sub-board 53 as needed.

[0078] The second lamination bondes the sub-board 51 and the intermediate board 52 together through a prepreg (dielectric layer M54), and the intermediate board 52 and the sub-board 53 together through a prepreg (dielectric layer M58), forming a complete PCB board 500. After the second lamination, through holes are drilled on the entire PCB board 500, such as the conductive vias V54 shown in Figures 6A and 6B. The through hole V52 on the intermediate board 52 becomes a buried via on the entire PCB board 500, while the through holes V51 on the sub-board 51 and V52 on the sub-board 53 become blind vias on the entire PCB board 500.

[0079] The following is an example of how PCB board 500 is fabricated in a specific scenario:

[0080] Step 1, material cutting: Cut the large copper-clad laminate into small production boards of various required specifications.

[0081] Step 2, one-time mechanical drilling: drill blind holes in metal layer L51, dielectric layer M51, metal layer L52, metal layer L511, dielectric layer M511, and metal layer L512, and perform copper plating and resin filling.

[0082] Step 3, Inner Layer Circuit Fabrication: Fabricate the circuitry for metal layers L52 / L53 / L55 / L56 / L57 / L58 / L510 / L511.

[0083] Step 4, one-time pressing: Complete the pressing of sub-board 51 (L51-L54 layers) and sub-board 53 (L59-L512) respectively.

[0084] Step 5, secondary mechanical drilling: Drill through holes on sub-boards 51 and 53 respectively, and then perform copper plating and resin filling.

[0085] Step 6, Secondary inner layer circuit fabrication: Fabricate the circuitry for metal layers L54 / L59.

[0086] Step 7, Secondary lamination: The two core boards of the prepared sub-board 51 and sub-board 53 and the intermediate board 52 are laminated together in the order of stacking using a prepreg.

[0087] Step 8, three mechanical drillings: make conductive through holes in the above-pressed board.

[0088] Step 9, Outer Layer Pattern Creation: Create the circuitry for the outer metal layers L51 and L512.

[0089] Step 10 involves creating solder resist, silkscreen printing, and surface treatment.

[0090] Step 11, PCB outline fabrication, final inspection.

[0091] In this application, the stacked structure of the first sub-board, second sub-board, and intermediate board allows them to be laminated in stages. Blind vias can be machined without being limited by the size and aspect ratio of laser-drilled blind vias. Therefore, a core board with a thicker dielectric layer (any size between 0.1mm and 0.254mm) can be selected. The stripline on the sub-layer references the two layers of the sub-board, and the linewidth can be made wider. In some embodiments, the thickness of the dielectric layer can be 0.1mm, 0.15mm, 0.2mm, or 0.254mm.

[0092] In this application, since the surface layer and the sub-surface layer are implemented from a single core board, when the thickness of the core board is greater than 0.1 mm, the blind holes between the surface layer and the sub-surface layer can be made using a mature mechanical hole process. The hole has a large thickness-to-diameter ratio and low process requirements. When the core board is relatively thick, the diameter of the blind holes can be at least 0.15 mm.

[0093] In this application, the metal layer can be a single piece of metal material, or it can include metal structures for functions such as signal transmission, power distribution, and grounding, with the metal structures separated by an insulating dielectric material. Within a metal layer, metal structures with a specific pattern can form conductive paths extending within the layer plane for signal transmission, power supply, etc. The metal can be copper, aluminum, silver, gold, etc. The dielectric layer is composed of an insulating material, providing insulation between the different metal layers. For example, the fourth metal layer L4 and the fifth metal layer Ln-3 can be a single piece of metal material to serve as a grounding reference layer (refer to Figures 3B, 3C, 4B, and 4C). In some cases, the fourth metal layer L4 and the fifth metal layer Ln-3 can also have partial openings (filled with dielectric material) to ground the conductive through-holes (refer to Figures 3A and 4A). As another example, some metals in the second metal layer L2, the third metal layer L3, the sixth metal layer Ln-2, ​​and the seventh metal layer Ln-1, where signal lines are laid, can serve as signal lines. The signal lines are isolated from other metal materials in the same layer to avoid signal interference (refer to Figures 3A and 4A).

[0094] In this application, metal shielding vias, conductive through-holes, and conductive blind vias can be metallized vias or plugs in a PCB. Metallized vias are formed by drilling and then electroplating a conductive metal layer on the hole wall, creating a conductive channel that penetrates all layers of the PCB. Plugs are formed by filling the space inside a metallized via with insulating or conductive material.

[0095] In this application, the metal shielding hole is grounded, for example, the metal shielding hole is connected to the ground reference layer for grounding, thereby shielding the signal line.

[0096] It is understood that the specific embodiments described herein are merely for illustrative purposes and not for limiting the scope of this application. Furthermore, for ease of description, the accompanying drawings show only the parts relevant to this application, and not all of the structures or processes. It should be noted that similar reference numerals and letters in this specification denote similar items in the accompanying drawings.

[0097] It should be understood that although the terms "first," "second," etc., may be used herein to describe various features, these features should not be limited by these terms. The use of these terms is merely for distinction and should not be construed as indicating or implying relative importance. For example, without departing from the scope of the exemplary embodiments, a first feature may be referred to as a second feature, and similarly, a second feature may be referred to as a first feature.

[0098] In the description of this application, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set up," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this embodiment based on the specific circumstances.

[0099] The illustrative embodiments of this application include, but are not limited to, PCBs compatible with millimeter waves and high-speed digital signals.

[0100] Various aspects of the illustrative embodiments will be described using terminology commonly employed by those skilled in the art to convey the essence of their work to others skilled in the art. However, it will be apparent to those skilled in the art that some alternative embodiments will be practiced using the features partially described. Specific figures and configurations are set forth for purposes of explanation in order to provide a more thorough understanding of the illustrative embodiments. However, it will be apparent to those skilled in the art that alternative embodiments may be practiced without specific details. In some other instances, well-known features have been omitted or simplified herein to avoid obscuring the illustrative embodiments of this application.

[0101] Furthermore, the various operations will be described as multiple separate operations in a manner most conducive to understanding the illustrative embodiments; however, the order of description should not be construed as implying that these operations must depend on the order of description, and many of these operations may be performed in parallel, concurrently, or simultaneously. Moreover, the order of the operations may also be rearranged. The process may be terminated when the described operations are completed, but may also include additional steps not included in the figures. The process may correspond to a method, function, procedure, subroutine, subroutine, etc.

[0102] References to "an embodiment," "embodiment," "illustrative embodiment," etc., in this specification indicate that the described embodiment may include specific features, structures, or properties; however, each embodiment may or may not necessarily include specific features, structures, or properties. Furthermore, these phrases are not necessarily directed to the same embodiment. Additionally, when specific features are described in conjunction with specific embodiments, the knowledge of those skilled in the art can influence the combination of these features with other embodiments, whether or not those embodiments are explicitly described.

[0103] Unless the context otherwise specifies, the terms “comprising,” “having,” and “including” are synonyms. The phrase “A and / or B” means “(A), (B), or (A and B).”

[0104] In the accompanying drawings, some structural or methodological features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order is not necessary. Rather, in some embodiments, these features may be illustrated in a manner and / or order different from that shown in the illustrative drawings. Furthermore, the inclusion of structural or methodological features in a particular drawing does not mean that all embodiments need to include such features; in some embodiments, these features may be omitted or may be combined with other features.

[0105] The embodiments of this application have been described in detail above with reference to the accompanying drawings. However, the use of the technical solutions of this application is not limited to the various applications mentioned in the embodiments of this application. Various structures and modifications can be easily implemented with reference to the technical solutions of this application to achieve the various beneficial effects mentioned herein. Within the scope of knowledge possessed by those skilled in the art, all changes made without departing from the spirit of this application should be considered within the scope of this patent application. For example, partial mixed pressing in the entire PCB structure (i.e., the stacking of this utility model in a local area of ​​the PCB), adding back drilling process to the sub-board or the entire finished board, etc.

Claims

1. A PCB board compatible with millimeter-wave and high-speed digital signals, characterized in that, In order, they include: The first sub-board includes a laminated first core board and a second core board; both the first core board and the second core board include two metal layers; wherein a first metal shielding hole is disposed within the first sub-board and penetrates through the first sub-board; an intermediate board includes at least one metal layer; the second sub-board includes a laminated third core board and a fourth core board; both the third core board and the fourth core board include two metal layers; wherein a second metal shielding hole is disposed within the second sub-board and penetrates through the second sub-board; wherein the first sub-board includes a first signal line for transmitting radio frequency signals and a second signal line for transmitting digital signals; or, the first sub-board includes a first signal line for transmitting radio frequency signals, and the second sub-board includes a second signal line for transmitting digital signals; the PCB board further includes: a conductive via penetrating the first sub-board, the intermediate board, and the second sub-board; the intermediate board includes a third signal line, and the conductive via connects to the third signal line.

2. The PCB board according to claim 1, characterized in that, The intermediate plate includes at least two metal layers, or the intermediate plate includes at least one fifth core plate, the fifth core plate including at least two metal layers; multiple of the at least two metal layers include the third signal line; the intermediate plate is further provided with: a first conductive through hole, which penetrates the intermediate plate and is respectively connected to the third signal line located in different metal layers, so as to conduct the third signal line located in different metal layers.

3. The PCB board according to claim 1, characterized in that, The third signal line includes a power line, a control signal line, or a digital signal line.

4. The PCB board according to claim 1, characterized in that, The first core board includes a first metal layer and a second metal layer stacked together, the second metal layer including the first signal line; the first sub-board is further provided with: a first conductive blind via, which conducts the first signal line and the first metal layer, and a plurality of first metal shielding holes surrounding the first conductive blind via.

5. The PCB board according to claim 4, characterized in that, The second core board sequentially includes a third metal layer and a fourth metal layer; the third core board sequentially includes a fifth metal layer and a sixth metal layer; the fourth core board sequentially includes a seventh metal layer and an eighth metal layer; the second metal layer or the third metal layer includes a second signal line; the first sub-board is further provided with a second conductive blind via or a second conductive through-hole, the second conductive blind via or the second conductive through-hole connecting the second signal line and the first metal layer, the second conductive through-hole penetrating the first sub-board; and / or, the sixth metal layer or the seventh metal layer includes a fourth signal line for transmitting digital signals; the second sub-board is further provided with a third conductive blind via or a third conductive through-hole, the third conductive blind via or the third conductive through-hole connecting the fourth signal line and the eighth metal layer, the third conductive through-hole penetrating the second sub-board.

6. The PCB board according to claim 5, characterized in that, The first sub-board further includes a third metal shielding hole that penetrates the first sub-board, and a plurality of the third metal shielding holes surround the second conductive blind hole or the second conductive through hole; and / or, the second sub-board further includes a fourth metal shielding hole that penetrates the second sub-board, and a plurality of the fourth metal shielding holes surround the third conductive blind hole or the third conductive through hole.

7. The PCB board according to claim 5, characterized in that, A plurality of first metal shielding holes surround the first conductive blind hole; the fourth metal layer is a grounding layer, and the fourth metal layer forms a continuous and complete grounding plane coverage between the plurality of first metal shielding holes.

8. The PCB board according to claim 7, characterized in that, Within the area surrounded by multiple first metal shielding holes, the third metal layer has windows.

9. The PCB board according to claim 5, characterized in that, A plurality of second metal shielding holes surround the third conductive blind hole, and the fifth metal layer is a grounding layer, which forms a continuous and complete grounding plane coverage between the plurality of second metal shielding holes.

10. The PCB board according to claim 1, characterized in that, The first core board includes a dielectric layer between the two metal layers. The dielectric layer has a dielectric constant ≤3.5, a dielectric loss angle ≤0.004, and a thickness of 0.1mm~0.254mm.

Images