Display substrate and display device

Abstract

A display substrate and a display device, in which the display substrate includes: a substrate, and a plurality of sub-pixels, a plurality of first power lines and a plurality of scanning signal lines disposed on the substrate, the scanning signal lines at least partially extending in a first direction, the first power lines including: a plurality of first power connection portions and a plurality of second power connection portions, the first power connection portions being connected to the first power connection portions in a second direction, the second power connection portions being connected to the second power connection portions; the plurality of first power supply connecting parts and the plurality of second power supply connecting parts are alternately arranged and are mutually connected, at least parts of the first power supply connecting parts and the second power supply connecting parts extend along a second direction, and in a direction perpendicular to the display substrate, the first power supply connecting parts are positioned on one side, close to the substrate, of the active pattern of the at least one transistor, and the second power supply connecting parts are positioned on one side, close to the substrate, of the active pattern of the at least one transistor. The second power supply connecting part and the first electrode and the second electrode of the at least one transistor are arranged on the same layer, and the orthographic projection of the first power supply connecting part on the substrate is at least partially overlapped with the orthographic projection of the scanning signal line on the substrate.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and specifically to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Utility Model Content

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display substrate and a display device.

[0005] In a first aspect, this disclosure provides a display substrate, comprising: a substrate and a plurality of sub-pixels, a plurality of first power lines and a plurality of scan signal lines disposed on the substrate, wherein at least one sub-pixel includes: a pixel driving circuit, wherein the pixel driving circuit is connected to the first power lines and the scan signal lines respectively, and the pixel driving circuit includes: at least one transistor, wherein the transistor includes: an active pattern, a first electrode and a second electrode.

[0006] The scanning signal line extends at least partially along a first direction, and the first power line includes: a plurality of first power connection portions and a plurality of second power connection portions. In a second direction, the plurality of first power connection portions and the plurality of second power connection portions are alternately arranged and interconnected. The first power connection portions and the second power connection portions extend at least partially along a second direction, and the first direction and the second direction intersect.

[0007] In a direction perpendicular to the display substrate, the first power connection portion is located on the side of the active pattern of at least one transistor close to the substrate, the second power connection portion is disposed on the same layer as the first and second electrodes of at least one transistor, and the orthographic projection of the first power connection portion on the substrate at least partially overlaps with the orthographic projection of the scan signal line on the substrate.

[0008] In an exemplary embodiment, at least one transistor includes a driving transistor; the display substrate further includes a blocking structure located at at least one sub-pixel;

[0009] The shielding structure is disposed on the same layer as the first power connection portion, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the active pattern of the driving transistor on the substrate.

[0010] In an exemplary embodiment, the sub-pixel includes: a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel constituting a pixel unit, and the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel arranged sequentially along a first direction;

[0011] The first power line connecting the first sub-pixel and the second sub-pixel is located on the side of the first sub-pixel away from the second sub-pixel, and the first power line connecting the third sub-pixel and the fourth sub-pixel is located on the side of the fourth sub-pixel away from the third sub-pixel.

[0012] The distance between the orthographic projection of the occlusion structure of the first sub-pixel on the substrate and the orthographic projection of the first power line connecting the first sub-pixel and the second sub-pixel on the substrate along the first direction is less than 0.5 times the linewidth of the first power line connecting the first sub-pixel and the second sub-pixel.

[0013] The distance between the orthographic projection of the occlusion structure of the fourth sub-pixel on the substrate and the orthographic projection of the first power line connecting the third and fourth sub-pixels on the substrate along the first direction is less than 0.5 times the linewidth of the first power line connecting the third and fourth sub-pixels.

[0014] In an exemplary embodiment, the blocking structure includes: a first blocking part and a second blocking part, the first blocking part and the second blocking part are arranged along a first direction, and the length of the first blocking part along a second direction is less than the length of the second blocking part along the second direction, and the first direction intersects the second direction;

[0015] In the occlusion structure of the first sub-pixel, the first occlusion part is located on the side of the second occlusion part near the first power line connecting the first sub-pixel and the second sub-pixel; in the occlusion structure of the fourth sub-pixel, the first occlusion part is located on the side of the second occlusion part near the first power line connecting the third sub-pixel and the fourth sub-pixel.

[0016] The distance between the orthographic projection of the first occluding part in the occluding structure of the first sub-pixel on the substrate and the orthographic projection of the first power line connecting the first sub-pixel and the second sub-pixel on the substrate along the first direction is less than 0.5 times the line width of the first power line connecting the first sub-pixel and the second sub-pixel;

[0017] The distance between the orthographic projection of the first occluding part in the occluding structure of the fourth sub-pixel on the substrate and the orthographic projection of the first power line connecting the third and fourth sub-pixels on the substrate along the first direction is less than 0.5 times the linewidth of the first power line connecting the third and fourth sub-pixels.

[0018] In an exemplary embodiment, at least a portion of the scan signal lines that overlap with the first power connection portion are disposed in the same layer as the second power connection portion and are located in the film layer where the first and second electrodes of at least one transistor are located.

[0019] In an exemplary embodiment, the circuit further includes: a plurality of data signal lines disposed on the substrate, at least one of the data signal lines extending at least partially along a second direction; the pixel driving circuit further includes: a capacitor, the capacitor including: a first electrode plate and a second electrode plate.

[0020] For at least one sub-pixel, the distance between the orthographic projection of at least one of the first and second plates of the capacitor on the substrate and the orthographic projection of the data signal line connected to the sub-pixel on the substrate along a first direction is greater than the line width of the data signal line connected to the sub-pixel, and the first direction intersects the second direction.

[0021] In an exemplary embodiment, the data signal line is a single-layer structure and is disposed on the same layer as the shielding structure.

[0022] In an exemplary embodiment, the data signal line includes: a first data signal line and a second data signal line. For at least one pixel unit, the data signal line connected to at least one sub-pixel is the first data signal line, and the data signal line connected to at least one sub-pixel is the second data signal line.

[0023] The first data signal line has a single-layer structure, and the second data signal line has a double-layer structure.

[0024] In an exemplary embodiment, at least one sub-pixel further includes: a light-emitting device, the light-emitting device including: an anode, the display substrate further includes: a pixel definition layer, the pixel definition layer being provided with a pixel opening, the anode of the light-emitting device being connected to a pixel driving circuit through the pixel opening, and the orthographic projection of the pixel opening on the substrate being within the range of the orthographic projection of the anode of the light-emitting device on the substrate;

[0025] The first plate of the capacitor includes a first capacitor body and a first capacitor connection part; the second plate of the capacitor includes a second capacitor body and a second capacitor connection part; the display substrate further includes a plurality of compensation signal lines disposed on the substrate.

[0026] The orthographic projection of the pixel opening of at least one sub-pixel on the substrate at least partially overlaps with the orthographic projections of the first capacitor connection portion, the second capacitor connection portion and the second capacitor body portion on the substrate, and has no overlapping area with the orthographic projections of at least one transistor and at least one of the data signal lines, the first power line, the scan signal line and the compensation signal line on the substrate.

[0027] The second length is greater than the first length, wherein the first length is the length of the pixel opening of the sub-pixel connected to the first data signal line along the first direction, and the second length is the length of the pixel opening of the sub-pixel connected to the second data signal line along the first direction;

[0028] The third length is less than the fourth length, wherein the third length is the minimum length of at least one of the first capacitor body portion and the second capacitor body portion of the sub-pixel connected to the first data signal line along the first direction, and the fourth length is the minimum length of at least one of the first capacitor body portion and the second capacitor body portion of the sub-pixel connected to the second data signal line along the first direction.

[0029] In an exemplary embodiment, the difference between the second length and the first length is greater than 0.5 times the line width of the first data signal line;

[0030] The difference between the fourth length and the third length is greater than 0.5 times the line width of the first data signal line.

[0031] In an exemplary embodiment, the difference between the second length and the first length is greater than 3 micrometers;

[0032] The difference between the fourth length and the third length is greater than 3 micrometers.

[0033] In an exemplary embodiment, the sub-pixel includes: a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel constituting a pixel unit, and the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel arranged sequentially along a first direction;

[0034] The data signal lines connected to the first sub-pixel and the data signal lines connected to the second sub-pixel are located between the first sub-pixel and the second sub-pixel, and the data signal lines connected to the third sub-pixel and the data signal lines connected to the fourth sub-pixel are located between the third sub-pixel and the fourth sub-pixel.

[0035] The data signal line connecting one of the first sub-pixels and the second sub-pixel is the first data signal line, and the data signal line connecting the other sub-pixel is the second data signal line.

[0036] The data signal line connected to one of the third and fourth sub-pixels is the first data signal line, and the data signal line connected to the other sub-pixel is the second data signal line.

[0037] The first data signal line is disposed on the same layer as the first power connection portion. The second data signal line includes: a plurality of first data connection portions and a plurality of second data connection portions. In the second direction, the plurality of first data connection portions and the plurality of second data connection portions are arranged alternately and connected to each other. At least one of the first data connection portions and the second data connection portions extends at least partially along the second direction.

[0038] The first data connection portion and the first power connection portion are disposed on the same layer, and their orthographic projections on the substrate and the orthographic projections of the scan signal line on the substrate at least partially overlap. The second data connection portion and the second power connection portion are disposed on the same layer, and the length of the second data connection portion along the second direction is less than the length of the second power connection portion along the second direction.

[0039] In an exemplary embodiment, the pixel driving circuit further includes a capacitor, which includes a first electrode plate and a second electrode plate.

[0040] The shielding structure is located on the side of the first plate of the capacitor away from the substrate and on the side of the second plate of the capacitor close to the substrate. The second plate of the capacitor is disposed on the same layer as the active pattern of at least one transistor.

[0041] In an exemplary embodiment, the orthographic projection of at least one of the second plate of the capacitor and the shielding structure onto the substrate at least partially overlaps with the orthographic projection of the first plate of the capacitor onto the substrate.

[0042] In an exemplary embodiment, for at least one sub-pixel, the occlusion structure is provided with a via, the via exposing the first plate of the capacitor;

[0043] The orthographic projection of the active pattern of the driving transistor on the substrate at least partially overlaps with the orthographic projection of the via on the substrate; a composite insulating layer is provided between the film layer containing the first and second electrodes of the at least one transistor and the film layer containing the shielding structure, the composite insulating layer is provided with a connecting via, the orthographic projection of the connecting via on the substrate is within the range of the orthographic projection of the via on the substrate, and the second electrode of the driving transistor is electrically connected to the first plate of the capacitor through the connecting via and the via.

[0044] In an exemplary embodiment, the first plate of the capacitor includes: a first capacitor body portion and a first capacitor connection portion connected to each other, the first capacitor connection portion being located on one side of the first capacitor body portion, and the length of the first capacitor connection portion along a first direction being less than the length of the first capacitor body portion along the first direction;

[0045] The second plate of the capacitor includes: a second capacitor body and a second capacitor connection part connected to each other, the second capacitor connection part being located on one side of the second capacitor body part, and the length of the second capacitor connection part along the first direction being less than the length of the second capacitor body part along the first direction.

[0046] The orthographic projection of the first capacitor body on the substrate at least partially overlaps with the orthographic projection of the second capacitor body on the substrate, and at least partially overlaps with the orthographic projection of the shielding structure on the substrate. The orthographic projections of the first capacitor connection portion on the substrate and the orthographic projections of the second capacitor connection portion on the substrate are arranged along a first direction.

[0047] In an exemplary embodiment, the region where the orthographic projection of the first capacitor body portion on the substrate is located includes: a first region and a second region, the first region and the second region being arranged along a second direction, and the second region being located on the side of the first region away from the first capacitor connection portion;

[0048] The orthographic projection of the second capacitor body onto the substrate is at least partially located in the first region, and the orthographic projection of the shielding structure onto the substrate is at least partially located in the second region.

[0049] In an exemplary embodiment, the scanning signal line has a single-layer structure and is disposed on the same layer as the second power connection portion.

[0050] In an exemplary embodiment, the scan signal line includes: a plurality of first scan connection portions and a plurality of second scan connection portions; in the first direction, the plurality of first scan connection portions and the plurality of second scan connection portions are alternately arranged and interconnected with each other, and at least one of the first scan connection portions and the second scan connection portions extends at least partially along the first direction; the transistor further includes: a control electrode.

[0051] The first scan connection portion is disposed on the same layer as the control electrode of at least one transistor, and the second scan connection portion is disposed on the same layer as the second power supply connection portion.

[0052] In an exemplary embodiment, it further includes: a plurality of data signal lines and a plurality of compensation signal lines disposed on the substrate, wherein the sub-pixels are electrically connected to the data signal lines and the compensation signal lines respectively;

[0053] The orthographic projection of at least one second scan connection portion on the substrate at least partially overlaps with the orthographic projection of at least one of the structures of the data signal line, the compensation signal line, and the first power connection portion on the substrate.

[0054] In an exemplary embodiment, it further includes: a plurality of compensation signal lines disposed on the substrate, wherein the sub-pixel is connected to the compensation signal lines, and the compensation signal lines extend at least partially along a second direction;

[0055] The compensation signal line is disposed on the same layer as the first power connection part, and at least one sub-pixel in the same pixel unit is connected to the same compensation signal line.

[0056] In an exemplary embodiment, the sub-pixel includes: a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel constituting a pixel unit, and the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel arranged sequentially along a first direction;

[0057] The first power line connecting the first sub-pixel and the second sub-pixel is located on the side of the first sub-pixel away from the second sub-pixel, and the first power line connecting the third sub-pixel and the fourth sub-pixel is located on the side of the fourth sub-pixel away from the third sub-pixel.

[0058] The first power line connecting the first sub-pixel and the second sub-pixel of one of two adjacent pixel units arranged along the first direction is the same signal line as the first power line connecting the third sub-pixel and the fourth sub-pixel of the other pixel unit.

[0059] In at least one pixel unit, the distance between the first boundary of the control electrode of the driving transistor of at least one of the first sub-pixels and the fourth sub-pixels and the second boundary of the first power line connecting the first sub-pixel and the fourth sub-pixel along a first direction is greater than 11.5 micrometers;

[0060] The first boundary is the boundary of the control electrode of the driving transistor of at least one of the first sub-pixels and the fourth sub-pixels near the boundary of the first power line connecting the first sub-pixel and the fourth sub-pixel. The second boundary is the boundary of the first power line connecting the first sub-pixel and the fourth sub-pixel near the boundary of the control electrode of the driving transistor of the first sub-pixel and the fourth sub-pixel.

[0061] In an exemplary embodiment, the circuit further includes a compensation signal line, and the pixel driving circuit further includes a capacitor, which includes a first electrode plate and a second electrode plate.

[0062] The display substrate further includes: a driving structure layer disposed on the substrate, the driving structure layer including: a first conductive layer, a second conductive layer, a semiconductor layer, a third conductive layer and a fourth conductive layer sequentially stacked on the substrate; the transistor further includes: a control electrode;

[0063] The first conductive layer includes at least: the first electrode of the capacitor of at least one sub-pixel;

[0064] The second conductive layer includes at least: a masking structure for at least one sub-pixel, a compensation signal line, and a first power connection portion for at least one first power line;

[0065] The semiconductor layer includes at least: an active pattern of at least one transistor of at least one sub-pixel and a second plate of a capacitor;

[0066] The third conductive layer includes at least: the control electrode of at least one transistor of at least one sub-pixel;

[0067] The fourth conductive layer includes at least: a first electrode and a second electrode of at least one transistor of at least one sub-pixel, and a second power connection portion of at least one first power line;

[0068] The first conductive layer and the semiconductor layer are transparent films.

[0069] In an exemplary embodiment, it further includes: a data signal line, wherein when the data signal line is a single-layer structure, the data signal line is located in the second conductive layer;

[0070] When the data signal line includes a first data connection portion and a second data connection portion, the first data connection portion is located in the second conductive layer, and the second data connection portion is located in the fourth conductive layer.

[0071] In an exemplary embodiment, when the scan signal line has a single-layer structure, the scan signal line is located in the fourth conductive layer;

[0072] When the scanning signal line includes a first scanning connection portion and a second scanning connection portion, the first scanning connection portion is located in the third conductive layer, and the second scanning connection portion is located in the fourth conductive layer.

[0073] Secondly, this disclosure also provides a display device, including: the aforementioned display substrate.

[0074] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0075] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0076] Figure 1 This is a schematic diagram of the structure of a display device;

[0077] Figure 2 This is a schematic diagram of an equivalent circuit for a pixel driving circuit.

[0078] Figure 3 A top view of the display substrate provided in the embodiments of this disclosure. Figure 1 ;

[0079] Figure 4 A top view of the display substrate provided in the embodiments of this disclosure. Figure 2 ;

[0080] Figure 5 A top view of the display substrate provided in the embodiments of this disclosure. Figure 3 ;

[0081] Figure 6 A top view of the display substrate provided in the embodiments of this disclosure. Figure 4 ;

[0082] Figure 7 for Figures 3 to 6 Enlarged view of the central area;

[0083] Figure 8A for Figure 4 and Figure 6 Cross-sectional view along the BB direction;

[0084] Figure 8B for Figure 3 and Figure 5 Cross-sectional view along the BB direction;

[0085] Figure 8C for Figures 3 to 6 Schematic diagram of the cross section along the CC direction;

[0086] Figure 9 for Figure 3 A schematic diagram of the structure of the provided display substrate;

[0087] Figure 10 for Figure 4 A schematic diagram of the structure of the provided display substrate;

[0088] Figure 11 for Figure 5 A schematic diagram of the structure of the provided display substrate;

[0089] Figure 12 for Figure 6 A schematic diagram of the structure of the provided display substrate;

[0090] Figure 13 for Figures 9 to 12Cross-sectional view along direction AA;

[0091] Figure 14 for Figure 9 , Figure 10 , Figure 11 and Figure 12 A schematic diagram after the first conductive layer pattern has been formed;

[0092] Figure 15 for Figure 9 and Figure 10 A schematic diagram of the second conductive layer pattern in the image;

[0093] Figure 16 for Figure 9 and Figure 10 A schematic diagram after the second conductive layer pattern has been formed;

[0094] Figure 17 for Figure 11 and Figure 12 A schematic diagram of the second conductive layer pattern in the image;

[0095] Figure 18 for Figure 11 and Figure 12 A schematic diagram after the second conductive layer pattern has been formed;

[0096] Figure 19 for Figure 9 , Figure 10 , Figure 11 and Figure 12 A schematic diagram of the semiconductor layer pattern in the image;

[0097] Figure 20 for Figure 9 and Figure 10 A schematic diagram after the semiconductor layer pattern has been formed;

[0098] Figure 21 for Figure 11 and Figure 12 A schematic diagram after the semiconductor layer pattern has been formed;

[0099] Figure 22 for Figure 9 and Figure 11 A schematic diagram of the third conductive layer pattern in the image;

[0100] Figure 23 for Figure 9 A schematic diagram after the formation of the third conductive layer pattern;

[0101] Figure 24 for Figure 11 A schematic diagram after the formation of the third conductive layer pattern;

[0102] Figure 25 for Figure 10 and Figure 12A schematic diagram of the third conductive layer pattern in the image;

[0103] Figure 26 for Figure 10 A schematic diagram after the formation of the third conductive layer pattern;

[0104] Figure 27 for Figure 12 A schematic diagram after the formation of the third conductive layer pattern;

[0105] Figure 28 for Figure 9 A schematic diagram showing the formation of the third insulating layer pattern;

[0106] Figure 29 for Figure 10 A schematic diagram showing the formation of the third insulating layer pattern;

[0107] Figure 30 for Figure 11 A schematic diagram showing the formation of the third insulating layer pattern;

[0108] Figure 31 for Figure 12 A schematic diagram showing the formation of the third insulating layer pattern;

[0109] Figure 32 for Figure 9 A schematic diagram of the pattern of the fourth conductive layer;

[0110] Figure 33 for Figure 9 A schematic diagram after the fourth conductive layer pattern has been formed;

[0111] Figure 34 for Figure 10 A schematic diagram of the pattern of the fourth conductive layer;

[0112] Figure 35 for Figure 10 A schematic diagram after the fourth conductive layer pattern has been formed;

[0113] Figure 36 for Figure 11 A schematic diagram of the pattern of the fourth conductive layer;

[0114] Figure 37 for Figure 11 A schematic diagram after the fourth conductive layer pattern has been formed;

[0115] Figure 38 for Figure 12 A schematic diagram of the formation of the fourth conductive layer pattern;

[0116] Figure 39 for Figure 12 A schematic diagram after the fourth conductive layer pattern has been formed;

[0117] Figure 40 for Figure 9 A schematic diagram after the planarization layer pattern has been formed;

[0118] Figure 41 for Figure 10 A schematic diagram after the planarization layer pattern has been formed;

[0119] Figure 42 for Figure 11 A schematic diagram after the planarization layer pattern has been formed;

[0120] Figure 43 for Figure 12 A schematic diagram after the planarization layer pattern has been formed;

[0121] Figure 44 for Figure 9 , Figure 10 , Figure 11 and Figure 12 A schematic diagram of the fifth conductive layer pattern;

[0122] Figure 45 for Figure 9 A schematic diagram after the fifth conductive layer pattern has been formed;

[0123] Figure 46 for Figure 10 A schematic diagram after the fifth conductive layer pattern has been formed;

[0124] Figure 47 for Figure 11 A schematic diagram after the fifth conductive layer pattern has been formed;

[0125] Figure 48 for Figure 12 A schematic diagram after the fifth conductive layer pattern has been formed. Detailed Implementation

[0126] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0127] In the accompanying drawings, the size of the constituent elements, the thickness of the layers, or the area are sometimes exaggerated for clarity. Therefore, one aspect of this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0128] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0129] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0130] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0131] In this specification, a transistor is a device that includes at least three terminals: a control electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain terminal, drain region, or drain electrode) and the source electrode (source terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0132] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0133] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0134] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0135] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0136] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0137] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0138] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0139] Figure 1 This is a schematic diagram of the structure of a display device. Figure 1 As shown, the display device may include a timing controller, a data signal driver, a scan signal driver, and a pixel array. The pixel array may include multiple scan signal lines (S1 to Sm), multiple data signal lines (D1 to Data), and multiple sub-pixels Pxij.

[0140] In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data signal driver to the data signal driver, and can provide clock signals, scan start signals, etc. of specifications suitable for the scan signal driver to the scan signal driver.

[0141] In an exemplary embodiment, the data signal driver can use grayscale values ​​and control signals received from a timing controller to generate data voltages that will be provided to data signal lines D1, D2, D3, ... and Data. For example, the data signal driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 through Data on a sub-pixel row basis, where n can be a natural number.

[0142] In an exemplary embodiment, the scan signal driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving a clock signal, a scan start signal, etc., from a timing controller. For example, the scan signal driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan signal driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number.

[0143] In an exemplary embodiment, the subpixel array may include multiple subpixels PXij. Each subpixel PXij may be connected to a corresponding data signal line and a corresponding scan signal line, where i and j can be natural numbers. Subpixel PXij may refer to a subpixel in which a transistor is connected to the i-th scan signal line and to the j-th data signal line.

[0144] The display substrate may include multiple pixel units P arranged in a matrix. Each pixel unit P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, a third sub-pixel P3 emitting a third color light, and a fourth sub-pixel P4 emitting a fourth color light. Each of the first sub-pixel P1, second sub-pixel P2, third sub-pixel P3, and fourth sub-pixel P4 includes a pixel driving circuit and a light-emitting device. The pixel driving circuits in each of these sub-pixels are connected to scan signal lines and data signal lines, respectively. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal lines under the control of the scan signal lines and output a corresponding current to the light-emitting device. The light-emitting devices in each of these sub-pixels are connected to the pixel driving circuit of their respective sub-pixels. The light-emitting devices are configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.

[0145] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a blue sub-pixel (B) that emits green light, the third sub-pixel P3 may be a green sub-pixel (G) that emits blue light, and the fourth sub-pixel P4 may be a green sub-pixel (G) that emits white light.

[0146] In an exemplary embodiment, the shape of the sub-pixel can be rectangular, rhomboid, pentagonal or hexagonal, and the three sub-pixels can be arranged horizontally side by side, vertically side by side or in a triangular pattern, which is not limited in this disclosure.

[0147] In an exemplary embodiment, the four sub-pixels can be arranged in a horizontal, vertical, or square manner, etc., and this disclosure does not limit the arrangement.

[0148] In exemplary embodiments, the light-emitting device includes a current-driven device, which may employ a current-driven light-emitting diode, such as a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum light-emitting diode (QLED). The typical size (e.g., length) of a Micro LED can be less than 100 μm, for example, 10 μm to 50 μm. The typical size (e.g., length) of a Mini LED can be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0149] For example, when the light-emitting device is an organic light-emitting diode (OLED), the light-emitting device may include a stacked electrode (anode), an organic light-emitting layer, and a second electrode (cathode).

[0150] In an exemplary embodiment, the organic light-emitting layer may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In this exemplary embodiment, the hole injection layer of all sub-pixels may be a common layer connected together, the electron injection layer of all sub-pixels may be a common layer connected together, the hole transport layer of all sub-pixels may be a common layer connected together, the electron transport layer of all sub-pixels may be a common layer connected together, and the hole block layer of all sub-pixels may be a common layer connected together. The emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0151] In exemplary embodiments, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure, and this disclosure does not limit it in any way. Here, T refers to a transistor in the pixel driving circuit, C refers to a capacitor in the pixel driving circuit, the number before T refers to the number of transistors in the pixel driving circuit, and the number before C refers to the number of capacitors in the pixel driving circuit. The transistor includes: an active pattern, a control electrode, a first electrode, and a second electrode.

[0152] Figure 2 This is a schematic diagram of the equivalent circuit of a pixel driving circuit. Figure 2 This explanation uses a 3T1C pixel driving circuit as an example. Figure 2 As shown, the pixel driving circuit may include three transistors (first transistor T1 to third transistor T3) and one capacitor C. The pixel driving circuit is electrically connected to four signal lines (data signal line Data, scan signal line Gate, compensation signal line Sense, and first power supply line VDD). The capacitor C may include a first plate C1 and a second plate C2.

[0153] In an exemplary embodiment, the first transistor T1 can be referred to as a switching transistor. The control electrode of the first transistor T1 is coupled to the scan signal line Gate, the first electrode of the first transistor T1 is coupled to the data signal line Data, and the second electrode of the first transistor T1 is coupled to the first node N1. The first transistor T1 is configured to transmit the data signal of the data signal line Data to the first node N1 (the control electrode of the third transistor T3) under the control of the signal of the scan signal line Gate.

[0154] In an exemplary embodiment, the second transistor T2 may be referred to as a compensation transistor. The control electrode of the second transistor T2 is coupled to the scan signal line Gate, the first electrode of the second transistor T2 is coupled to the compensation signal line Sense, and the second electrode of the second transistor T2 is coupled to the second node N2. The second transistor T2 is configured to extract the threshold voltage Vth and mobility of the third transistor T3 in response to the compensation timing to compensate for the threshold voltage Vth.

[0155] In an exemplary embodiment, the third transistor T3 is a driving transistor. The control electrode of the third transistor T3 is coupled to the first node N1, the first electrode of the third transistor T3 is coupled to the first power supply line VDD, and the second electrode of the third transistor T3 is coupled to the second node N2. The third transistor T3 is configured to generate a corresponding current in the second node N2 under the control of the signal from the first node N1.

[0156] In an exemplary embodiment, the first electrode of the light-emitting device L is electrically connected to the second node N2, and the second electrode of the light-emitting device L is electrically connected to the second power line VSS. The light-emitting device L is configured to emit light of a corresponding brightness in response to the current in the second node N2.

[0157] In an exemplary embodiment, the first plate C1 of capacitor C is electrically connected to the second node N2, and the second plate C2 of capacitor C is electrically connected to the first node N1. Capacitor C is configured to store the voltage difference between the signals of the first node N1 and the second node N2 within one frame of emission, which can ensure the stability of the signal of the first node N1.

[0158] Based on their characteristics, transistors can be classified into N-type transistors and P-type transistors. When a transistor is P-type, its turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and its turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is N-type, its turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and its turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0159] In an exemplary embodiment, the first transistor T1 to the third transistor T3 can be low-temperature polysilicon (LTPS) thin-film transistors (LTPS), oxide thin-film transistors (OPTs), or a combination of both. The active layer of the LTPS is made of low-temperature polysilicon (LTPS), while the active layer of the OPT is made of oxide. LTPS offers advantages such as high mobility and fast charging, while OPT offers advantages such as low leakage current. Integrating LTPS and OPTs onto a single display substrate to form an LTPO display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0160] In an exemplary embodiment, the transistors of the first transistor T1 to the third transistor T3 can be N-type transistors.

[0161] In an exemplary embodiment, the first power line VDD continuously provides a high-level signal with a constant voltage value, and the second power line VSS continuously provides a low-level signal with a constant voltage value.

[0162] Taking the first transistor T1 to the third transistor T3 as N-type transistors as an example, Figure 2 The operation of the provided pixel driving circuit includes: the signal of the scan signal line Gate is a high-level signal, the data signal line Data provides a data signal, the signal of the scan signal line Gate is a high-level signal, the first transistor T1 is turned on, the data signal of the data signal line Data is written into the first node N1, driving the current of the transistor T3, and the light-emitting device L emits light.

[0163] The large parasitic capacitance between some signal lines in the display substrate causes crosstalk between the signals of some signal lines, affecting the reliability of the display substrate.

[0164] Therefore, this disclosure provides a display substrate.

[0165] Figure 3 A top view of the display substrate provided in the embodiments of this disclosure. Figure 1 , Figure 4 A top view of the display substrate provided in the embodiments of this disclosure. Figure 2 , Figure 5 A top view of the display substrate provided in the embodiments of this disclosure. Figure 3 , Figure 6 A top view of the display substrate provided in the embodiments of this disclosure. Figure 4 .like Figures 3 to 6As shown, this embodiment of the present disclosure provides a display substrate including: a substrate and a plurality of sub-pixels disposed on the substrate, a plurality of first power lines VDD and a plurality of scan signal lines Gate, wherein at least one sub-pixel includes: a pixel driving circuit, which is connected to the first power line VDD and the scan signal line Gate respectively.

[0166] like Figures 3 to 6 As shown, the first power line VDD includes: a plurality of first power connection portions VL1 and a plurality of second power connection portions VL2. In the second direction D2, the plurality of first power connection portions VL1 and the plurality of second power connection portions VL2 are alternately arranged and interconnected. The first power connection portions VL1 and the second power connection portions VL2 extend at least partially along the second direction D2. The scan signal line Gate extends at least partially along the first direction D1. The first direction D1 and the second direction D2 intersect.

[0167] like Figures 3 to 6 As shown, in a direction perpendicular to the display substrate, the first power connection portion VL1 is located on the side of the active pattern of at least one transistor close to the substrate, and the second power connection portion VL2 is located on the side of the active pattern of at least one transistor away from the substrate. The orthographic projection of the first power connection portion VL1 on the substrate at least partially overlaps with the orthographic projection of the scan signal line Gate on the substrate.

[0168] This disclosure increases the distance between the scan signal line and the first power line in the overlapping area by placing the first power connection portion that overlaps with the scan signal line on the side of the active pattern of at least one transistor close to the substrate. This reduces the parasitic capacitance between the scan signal line and the first power line, reduces the influence between the signals of the first power line and the scan signal line, and improves the reliability of the display substrate.

[0169] In an exemplary implementation, such as Figures 3 to 6 As shown, at least a portion of the scan signal line Gate, which overlaps with the first power connection portion VL1, is disposed in the same layer as the second power connection portion VL2, and is located in the film layer where the first and second electrodes of at least one transistor are located.

[0170] In an exemplary embodiment Figure 7 for Figures 3 to 6 An enlarged view of the central area. (See diagram below.) Figure 7 As shown, the display substrate further includes a blocking structure SH located at at least one sub-pixel. The blocking structure SH is disposed on the same layer as the first power connection portion VL1, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the active pattern 31 of the driving transistor on the substrate.

[0171] In an exemplary embodiment, the provision of the shielding structure can reduce the impact of illumination on the active pattern of the driving transistor, thereby improving the reliability of the driving transistor.

[0172] Combination Figures 3 to 7 As shown, the sub-pixels include: a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. These sub-pixels constitute one pixel unit and are arranged sequentially along a first direction D1. The first power line connecting the first sub-pixel P1 and the second sub-pixel P2 is located on the side of the first sub-pixel P1 furthest from the second sub-pixel P2, and the first power line connecting the third sub-pixel P3 and the fourth sub-pixel P4 is located on the side of the fourth sub-pixel P4 furthest from the third sub-pixel P3.

[0173] like Figures 3 to 6 As shown, the distance between the orthographic projection of the occlusion structure SH of the first sub-pixel P1 on the substrate and the orthographic projection of the first power line VDD connecting the first sub-pixel P1 and the second sub-pixel P2 on the substrate along the first direction D1 is less than 0.5 times the linewidth of the first power line VDD connecting the first sub-pixel P1 and the second sub-pixel P2.

[0174] like Figures 3 to 6 As shown, the distance between the orthographic projection of the occlusion structure of the fourth sub-pixel P4 on the substrate and the orthographic projection of the first power line VDD connecting the third sub-pixel P3 and the fourth sub-pixel P4 on the substrate along the first direction D1 is less than 0.5 times the linewidth of the first power line connecting the third sub-pixel P3 and the fourth sub-pixel P4.

[0175] like Figure 7 As shown, the blocking structure SH includes: a first blocking part SH1 and a second blocking part SH2. The first blocking part SH1 and the second blocking part SH2 are arranged along a first direction D1, and the length of the first blocking part SH1 along the second direction D2 is less than the length of the second blocking part SH2 along the second direction D2.

[0176] Combination Figures 3 to 7 As shown, in the occlusion structure SH of the first sub-pixel P1, the first occlusion part SH1 is located on the side of the second occlusion part SH2 close to the first power line VDD connecting the first sub-pixel P1 and the second sub-pixel P2. In the occlusion structure SH of the fourth sub-pixel P4, the first occlusion part SH1 is located on the side of the second occlusion part SH2 close to the first power line VDD connecting the third sub-pixel P3 and the fourth sub-pixel P4.

[0177] In an exemplary embodiment, the distance between the orthographic projection of the first occluding portion SH1 in the occluding structure SH of the first sub-pixel P1 on the substrate and the orthographic projection of the first power line VDD connecting the first sub-pixel P1 and the second sub-pixel P2 on the substrate along the first direction D1 is less than 0.5 times the linewidth of the first power line VDD connecting the first sub-pixel P1 and the second sub-pixel P2.

[0178] In an exemplary embodiment, the distance between the orthographic projection of the first occlusion portion SH1 in the occlusion structure SH of the fourth sub-pixel P4 onto the substrate and the orthographic projection of the first power line VDD connecting the third sub-pixel P3 and the fourth sub-pixel P4 onto the substrate along the first direction D1 is less than 0.5 times the linewidth of the first power line VDD connecting the third sub-pixel P3 and the fourth sub-pixel P4.

[0179] In an exemplary implementation, such as Figure 7 As shown, capacitor C includes a first plate C1 and a second plate C2. A shielding structure SH is located on the side of the first plate C1 away from the substrate and on the side of the second plate C2 close to the substrate. The second plate C2 is disposed on the same layer as the active pattern of at least one transistor.

[0180] In an exemplary implementation, such as Figure 7 As shown, the orthographic projection of at least one of the capacitor's second plate C2 and the shielding structure SH onto the substrate at least partially overlaps with the orthographic projection of the capacitor's first plate C1 onto the substrate.

[0181] In an exemplary implementation, such as Figure 7 As shown, for at least one sub-pixel, the occlusion structure SH is provided with a via V, which exposes the first plate C1 of the capacitor.

[0182] In an exemplary embodiment, a composite insulating layer is disposed between the film layer containing the first and second electrodes of at least one transistor and the film layer containing the shielding structure SH. The composite insulating layer has a connecting via CV. The orthographic projection of the connecting via CV onto the substrate falls within the range of the orthographic projection of the via V onto the substrate. The orthographic projection of the active pattern 31 of the driving transistor onto the substrate at least partially overlaps with the orthographic projection of the via V onto the substrate. The second electrode of the driving transistor is electrically connected to the first plate C1 of the capacitor via the connecting via CV and the via V. The arrangement of the connecting via CV and the via V in this disclosure can increase the connection yield between the second electrode of the driving transistor and the first plate of the capacitor.

[0183] In an exemplary implementation, such as Figure 7As shown, the first plate C1 of the capacitor includes a first capacitor body portion C1-1 and a first capacitor connection portion C1-2 connected to each other. The first capacitor connection portion C1-2 is located on one side of the first capacitor body portion C1-1, and the length of the first capacitor connection portion C1-2 along the first direction D1 is less than the length of the first capacitor body portion C1-1 along the first direction D1.

[0184] In an exemplary implementation, such as Figure 7 As shown, the second plate C2 of the capacitor includes: a second capacitor body part C2-1 and a second capacitor connection part C2-2 connected to each other. The second capacitor connection part C2-2 is located on one side of the second capacitor body part C2-1, and the length of the second capacitor connection part C2-2 along the first direction D1 is less than the length of the second capacitor body part C2-1 along the first direction D1.

[0185] In an exemplary implementation, such as Figure 7 As shown, the orthographic projection of the first capacitor body C1-1 on the substrate at least partially overlaps with the orthographic projection of the second capacitor body C2-1 on the substrate, and at least partially overlaps with the orthographic projection of the shielding structure SH on the substrate.

[0186] In an exemplary implementation, such as Figure 7 As shown, the orthographic projections of the first capacitor connection C1-2 and the second capacitor connection C2-2 on the substrate are arranged along the first direction D1.

[0187] In an exemplary implementation, such as Figure 7 As shown, the region where the orthographic projection of the first capacitor body C1-1 on the substrate is located includes a first region R1 and a second region R2. The first region R1 and the second region R2 are arranged along the second direction D2, and the second region R2 is located on the side of the first region R1 away from the first capacitor connection portion C1-2. The orthographic projection of the second capacitor body C2-1 on the substrate is at least partially located in the first region R1, and the orthographic projection of the shielding structure SH on the substrate is at least partially located in the second region R2.

[0188] In an exemplary embodiment, the scan signal line gate can be a single-layer structure or a double-layer structure. For example... Figure 3 and Figure 5 This explanation uses the two-layer structure of the scan signal line Gate as an example. Figure 4 and Figure 6 This explanation uses a single-layer structure for the scan signal line Gate as an example.

[0189] In an exemplary embodiment Figure 8A for Figure 4 and Figure 6 Cross-sectional view along the BB direction, as shown Figure 4 , Figure 6 and Figure 8A As shown, the scan signal line Gate has a single-layer structure and is set on the same layer as the second power supply connection part VL2.

[0190] In an exemplary embodiment Figure 8B for Figure 3 and Figure 5 Cross-sectional view along the BB direction, as shown Figure 3 , Figure 5 and Figure 8B As shown, the scan signal line Gate includes a plurality of first scan connection portions GL1 and a plurality of second scan connection portions GL2. Along a first direction D1, the plurality of first scan connection portions GL1 and the plurality of second scan connection portions GL2 are alternately arranged and interconnected, and at least one of the first scan connection portions GL1 and the second scan connection portions GL2 extends at least partially along the first direction D1.

[0191] In an exemplary embodiment Figure 8A and Figure 8B The provided display substrate includes: an active pattern 11 of a first transistor, an active pattern 21 of a second transistor, a control electrode 12 of the first transistor, and a control electrode 22 of the second transistor.

[0192] In an exemplary implementation, such as Figure 3 and Figure 5 As shown, the first scan connection portion GL1 is disposed on the same layer as the control electrode of at least one transistor, and the second scan connection portion GL2 is disposed on the same layer as the second power supply connection portion VL2.

[0193] When the scan signal line (Gate) receives a signal, the signal voltage changes from low to high, meaning there is a charging current in the Gate. The larger the display substrate, the greater the charging current required by the Gate. The Gate is connected to the transistor's control electrode via a gate via. If the uniformity of the gate via is insufficient, the resistance of the Gate within the via will be high, or its current-carrying capacity will be reduced, leading to abnormal charging of the Gate. Figure 4 and Figure 6 The provided scan signal line gate has a single-layer structure, which can reduce the number of gate vias opened in the composite insulating layer, thereby improving the charging reliability of the scan signal line gate and thus improving the reliability of the display substrate.

[0194] In an exemplary embodiment, the display substrate further includes: a plurality of data signal lines Data and a plurality of compensation signal lines Sense disposed on the substrate, wherein sub-pixels are electrically connected to the data signal lines Data and the compensation signal lines Sense, respectively. At least one data signal line Data and at least one compensation signal line Sense extend at least partially along the second direction D2.

[0195] For at least one sub-pixel, the distance between the orthographic projection of at least one of the first plates C1 and C2 of the capacitor onto the substrate and the orthographic projection of the data signal line Data connected to the sub-pixel onto the substrate along the first direction D1 is greater than the linewidth of the data signal line connected to the sub-pixel. This disclosure, by setting the distance between the orthographic projection of at least one of the first plates C1 and C2 of the capacitor onto the substrate and the orthographic projection of the data signal line Data connected to the sub-pixel onto the substrate along the first direction D1 to be greater than the linewidth of the data signal line connected to the sub-pixel, can reduce the parasitic capacitance between the data signal line signal and at least one of the first plates C1 and C2 of the capacitor, reduce the influence of the data signal line signal on the signal of the data signal line and the signal of at least one of the first plates C1 and C2 of the capacitor, improve the voltage regulation effect of the capacitor, and further improve the reliability of the display substrate.

[0196] In an exemplary implementation, such as Figure 3 and Figure 5 As shown, the orthographic projection of at least one second scan connection GL2 on the substrate at least partially overlaps with the orthographic projection of at least one of the structures of the data signal line Data, the compensation signal line Sense, and the first power connection VL1 on the substrate.

[0197] In an exemplary embodiment, the data signal line Data has a single-layer structure, or the data signal line Data can have a double-layer structure. Figure 3 and Figure 4 This explanation uses the data signal line (Data) as an example, which has a single-layer structure. Figure 5 and Figure 6 This explanation uses the example of some data signal lines having a single-layer structure and some data signal lines having a double-layer structure.

[0198] In an exemplary implementation, such as Figure 3 and Figure 4 As shown, the data signal line Data has a single-layer structure and is arranged on the same layer as the shielding structure and the first power supply connection part.

[0199] In an exemplary implementation, such as Figure 5 and Figure 6As shown, the data signal line Data includes: a first data signal line Data1 and a second data signal line Data2. For at least one pixel unit, the data signal line Data connected to at least one sub-pixel is the first data signal line Data1, and the data signal line Data connected to at least one sub-pixel is the second data signal line Data2. The first data signal line Data1 has a single-layer structure, and the second data signal line Data2 has a double-layer structure.

[0200] In an exemplary implementation, such as Figure 5 and Figure 6 As shown, the first data signal line Data1 and the first power connection part VL1 are arranged on the same layer.

[0201] In an exemplary implementation, such as Figure 5 and Figure 6 As shown, the second data signal line Data2 includes a plurality of first data connection portions DL1 and a plurality of second data connection portions DL2. In the second direction D2, the plurality of first data connection portions DL1 and the plurality of second data connection portions DL2 are alternately arranged and interconnected, and at least one of the first data connection portions DL1 and the second data connection portions DL2 extends at least partially along the second direction D2.

[0202] In an exemplary implementation, such as Figure 5 and Figure 6 As shown, the first data connection part DL1 and the first power connection part VL1 are disposed on the same layer, and their orthographic projections on the substrate and the orthographic projections of the scan signal line Gate on the substrate at least partially overlap. The second data connection part DL2 and the second power connection part VL2 are disposed on the same layer.

[0203] In an exemplary embodiment, the length of the second data connection portion DL2 along the second direction D2 is less than the length of the second power connection portion VL2 along the second direction D2.

[0204] In the exemplary embodiments, regardless of whether the scan signal line is a single-layer or double-layer structure, at least a portion of the scan signal line that overlaps with the data signal line is disposed in the same layer as the second power connection portion. Similarly, regardless of whether the data signal line is a single-layer or double-layer structure, at least a portion of the data signal line that overlaps with the scan signal line is disposed in the same layer as the first power connection portion. Because the distance between the film layer containing the first power connection portion and the film layer containing the second power connection portion is relatively large, the arrangement of the scan signal line and data signal line in this disclosure can reduce the parasitic capacitance of the scan signal line and data signal line, avoid mutual interference between the signals of the scan signal line and data signal line, and improve the reliability of the display substrate.

[0205] Figure 8C for Figures 3 to 6A schematic diagram of the cross-section along the CC direction. (See attached diagram.) Figure 8C As shown, the second electrode 34 of the third transistor is connected to the active pattern 31 of the third transistor and the first plate C1 of the capacitor via a bridging hole. A portion of the bridging hole exposes the active pattern of the third transistor, while the other portion exposes the first plate C1 of the capacitor.

[0206] In an exemplary embodiment Figure 9 for Figure 3 A schematic diagram of the provided display substrate structure. Figure 10 for Figure 4 A schematic diagram of the provided display substrate structure. Figure 11 for Figure 5 A schematic diagram of the provided display substrate structure. Figure 12 for Figure 6 A schematic diagram of the provided display substrate structure. Figure 13 for Figures 9 to 12 Cross-sectional view along direction AA. (See attached image.) Figures 9 to 13 As shown, at least one sub-pixel further includes a light-emitting device, which includes an anode 61. The display substrate further includes a pixel definition layer 61, which has a pixel opening PV. The anode 61 of the light-emitting device is connected to the pixel driving circuit through the pixel opening PV. The orthographic projection of the pixel opening PV on the substrate is located within the range of the orthographic projection of the anode 61 of the light-emitting device on the substrate.

[0207] Combination Figures 3 to 7 , Figures 9 to 11 As shown, the orthographic projection of the pixel opening PV of at least one sub-pixel on the substrate at least partially overlaps with the orthographic projections of the first capacitor connection portion, the second capacitor connection portion, and the second capacitor body portion on the substrate, and there is no overlap with the orthographic projection of at least one of the following signals on the substrate: at least one transistor and at least one of the data signal lines Data, VDD, Gate, and Sense.

[0208] In an exemplary embodiment, the length of the pixel opening of the sub-pixel connected to the first data signal line along the first direction is the first length, and the length of the pixel opening of the sub-pixel connected to the second data signal line along the first direction is the second length, which is greater than the first length.

[0209] In an exemplary embodiment, the minimum length of at least one of the first capacitor body portion and the second capacitor body portion of the sub-pixel connected to the first data signal line along the first direction is the third length, and the minimum length of at least one of the first capacitor body portion and the second capacitor body portion of the sub-pixel connected to the second data signal line along the first direction is the fourth length, and the third length is less than the fourth length.

[0210] In an exemplary embodiment, the difference between the second length and the first length is greater than 0.5 times the linewidth of the first data signal line. For example, the difference between the second length and the first length is greater than 3 micrometers.

[0211] In an exemplary embodiment, the difference between the fourth length and the third length is greater than 0.5 times the linewidth of the first data signal line. For example, the difference between the fourth length and the third length is greater than 3 micrometers.

[0212] In an exemplary implementation, such as Figures 3 to 6 As shown, the compensation signal line Sense is disposed on the same layer as the first power connection part VL1, and at least one sub-pixel in the same pixel unit is connected to the same compensation signal line Sense.

[0213] In an exemplary implementation, such as Figures 3 to 6 As shown, the first power line VDD connecting the first sub-pixel P1 and the second sub-pixel P2 of one of the two adjacent pixel units arranged along the first direction D1 is the same signal line as the first power line VDD connecting the third sub-pixel P3 and the fourth sub-pixel P4 of the other pixel unit.

[0214] In an exemplary implementation, such as Figures 3 to 6 As shown, in at least one pixel unit, the distance L along the first direction D1 between the first boundary of the control electrode of the driving transistor of at least one of the first sub-pixels P1 and P4 and the second boundary of the first power line VDD connecting at least one of the first sub-pixels P1 and P4 is greater than 11.5 micrometers. The first boundary is the boundary where the control electrode of the driving transistor of at least one of the first sub-pixels P1 and P4 is close to the first power line VDD connecting at least one of the first sub-pixels P1 and P4, and the second boundary is the boundary where the first power line VDD connecting at least one of the first sub-pixels P1 and P4 is close to the control electrode of the driving transistor of at least one of the first sub-pixels P1 and P4.

[0215] In an exemplary implementation, such as Figures 3 to 6 As shown, the data signal line Data connected to the first sub-pixel P1 and the data signal line Data connected to the second sub-pixel P2 are located between the first sub-pixel P1 and the second sub-pixel P2. The data signal lines Data connected to the third sub-pixel P3 and the fourth sub-pixel P4 are located between the third sub-pixel P3 and the fourth sub-pixel P4.

[0216] In an exemplary embodiment, when the data signal line includes a first data signal line and a second data signal line, the data signal line Data connected to one of the first sub-pixels P1 and P2 is the first data signal line Data1, the data signal line Data connected to the other sub-pixel of the first sub-pixel P1 and P2 is the second data signal line Data2, the data signal line Data connected to one of the third sub-pixels P3 and P4 is the first data signal line Data1, and the data signal line Data connected to the other sub-pixel of the third sub-pixel P3 and P4 is the second data signal line Data2. Figure 5 and Figure 6 The data signal line connecting the first sub-pixel and the fourth sub-pixel is the first data signal line, and the data signal line connecting the second sub-pixel and the third sub-pixel is the second data signal line.

[0217] In an exemplary embodiment, the display substrate further includes a driving structure layer and a light-emitting structure layer disposed on the substrate 10. The driving structure layer includes a first conductive layer, a second conductive layer, a semiconductor layer, a third conductive layer, and a fourth conductive layer sequentially stacked on the substrate 10.

[0218] like Figure 13 As shown, the driving structure layer further includes: a first insulating layer 20 disposed between the second conductive layer and the semiconductor layer, a second insulating layer 30 disposed between the semiconductor layer and the third conductive layer, a third insulating layer 40 disposed between the third conductive layer and the fourth conductive layer, a fourth insulating layer 50 disposed on the side of the fourth conductive layer away from the substrate, and a planarization layer 60 disposed on the side of the fourth insulating layer away from the substrate.

[0219] like Figure 13 As shown, the light-emitting structure layer also includes an organic light-emitting layer 62 and a cathode 63.

[0220] In an exemplary embodiment, the driving structure layer includes at least one transistor, at least one capacitor, and a shielding structure SH. The at least one transistor includes a first transistor T1 to a third transistor T3, and the at least one capacitor includes a capacitor comprising a first electrode C1 and a second electrode C2. The first transistor T1 includes an active pattern 11, a control electrode 12, a first electrode 13, and a second electrode 14; the second transistor T2 includes an active pattern 21, a control electrode 22, a first electrode 23, and a second electrode 24; and the third transistor T3 includes an active pattern 31, a control electrode 32, a first electrode 33, and a second electrode 34.

[0221] In an exemplary embodiment, the first conductive layer includes at least: a first plate of a capacitor of at least one sub-pixel.

[0222] In an exemplary embodiment, the second conductive layer includes at least: an occlusion structure of at least one sub-pixel, a compensation signal line Sense, and a first power connection portion VL1 of at least one first power line VDD.

[0223] In an exemplary embodiment, the semiconductor layer includes at least: an active pattern of at least one transistor of at least one sub-pixel and a second plate of a capacitor.

[0224] In an exemplary embodiment, the third conductive layer includes at least: a control electrode of at least one transistor of at least one sub-pixel;

[0225] In an exemplary embodiment, the fourth conductive layer includes at least: a first pole and a second pole of at least one transistor of at least one sub-pixel, and a second power connection portion VL2 of at least one first power line VDD.

[0226] In an exemplary embodiment, to ensure the impedance requirements of the data signal line and the first power line, the second conductive layer can be a metallic conductive layer. The material used to fabricate the second conductive layer can be copper.

[0227] In an exemplary embodiment, when the data signal line Data has a single-layer structure, the data signal line Data is located in the second conductive layer;

[0228] In an exemplary embodiment, when the data signal line Data includes a first data connection portion DL1 and a second data connection portion DL2, the first data connection portion DL1 is located in the second conductive layer and the second data connection portion DL2 is located in the fourth conductive layer.

[0229] In an exemplary embodiment, when the scan signal line Gate has a single-layer structure, the scan signal line Gate is located in the fourth conductive layer.

[0230] In an exemplary embodiment, when the scan signal line Gate includes a first scan connection portion GL1 and a second scan connection portion GL2, the first scan connection portion GL1 is located in a third conductive layer and the second scan connection portion GL2 is located in a fourth conductive layer.

[0231] In an exemplary embodiment, the first conductive layer and the semiconductor layer are transparent film layers. Since the first electrode of the capacitor is located on the first conductive layer and the second electrode of the capacitor is located on the semiconductor layer, the capacitor in this disclosure can be a transparent capacitor. A transparent capacitor can increase the pixel aperture area of ​​the sub-pixel and improve the aperture ratio of the display substrate.

[0232] In an exemplary embodiment, the shielding structure is located in the second conductive layer, and the second power connection portion adjacent to the orthographic projection of the shielding structure on the substrate is located in the fourth conductive layer. Since the shielding structure and the second power connection portion are located in different film layers, the distance between the shielding structure and the second power connection portion can be smaller, thereby increasing the area of ​​the shielding structure and ensuring the light-blocking effect.

[0233] In an exemplary embodiment, the composite insulating layer includes: a first insulating layer to a third insulating layer. The first insulating layer may be a buffer layer, the second insulating layer may be called a gate insulating layer, and the third insulating layer may be called an interlayer insulating layer.

[0234] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0235] Figures 14 to 48 A schematic diagram of the fabrication process of a display substrate provided for an exemplary embodiment. Figures 14 to 48 This explanation uses four sub-pixels within a single pixel unit as an example. For example... Figures 14 to 48 As shown, the fabrication process of a display substrate provided in an exemplary embodiment may include:

[0236] (1) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: coating a first conductive film on a substrate, and patterning the first conductive film using a patterning process to form a first conductive layer pattern, such as... Figure 14As shown, Figure 14 for Figure 9 , Figure 10 , Figure 11 and Figure 12 A schematic diagram after the first conductive layer pattern has been formed.

[0237] In an exemplary implementation, such as Figure 14 As shown, Figure 9 , Figure 10 , Figure 11 and Figure 12 In the provided display substrate, the first conductive layer pattern may include at least: a first electrode C1 of a capacitor located in at least one sub-pixel, a first connecting electrode 51, a second connecting electrode 52, and a third connecting electrode 53.

[0238] In an exemplary implementation, such as Figure 14 As shown, the first plate C1 of the capacitor located in at least one sub-pixel includes: a first capacitor body portion C1-1 and a first capacitor connection portion C1-2. The first capacitor connection portion C1-2 of at least one row of sub-pixels is located on the side of the first capacitor body portion C1-1 closer to the previous row.

[0239] In an exemplary embodiment, the first capacitor connection portion C1-2 is located on one side of the first capacitor body portion C1-1. The first capacitor body portion C1-1 and the first capacitor connection portion C1-2 extend at least partially along the second direction D2, and the width of the first capacitor connection portion C1-2 along the first direction D1 is smaller than the width of the first capacitor body portion C1-1 along the first direction D1.

[0240] In an exemplary embodiment, the first connecting electrode 51 is strip-shaped and extends along the first direction D1. The second connecting electrode 52 and the third connecting electrode 53 are block-shaped.

[0241] (2) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: depositing a second conductive film on a substrate on which the aforementioned pattern is formed, and patterning the second conductive film using a patterning process to form a second conductive layer pattern, such as... Figures 15 to 18 As shown, Figure 15 for Figure 9 and Figure 10 A schematic diagram of the second conductive layer pattern. Figure 16 for Figure 9 and Figure 10 A schematic diagram after the second conductive layer pattern has been formed. Figure 17 for Figure 11 and Figure 12 A schematic diagram of the second conductive layer pattern. Figure 18 for Figure 11 and Figure 12 A schematic diagram after the second conductive layer pattern has been formed.

[0242] In an exemplary implementation, such as Figure 15 and Figure 16 As shown, Figure 9 and Figure 10 In the provided display substrate, the second conductive layer pattern may include: at least one row of data signal lines Data connecting sub-pixels, at least one first power connection portion VL1 of a first power line, at least one compensation signal line Sense, and a fourth connection electrode 54 and a shielding structure SH located in at least one sub-pixel.

[0243] In an exemplary implementation, such as Figure 17 and Figure 18 As shown, Figure 11 and Figure 12 In the provided display substrate, the second conductive layer pattern may include: at least one column of data signal lines Data connected to sub-pixels, at least one column of data signal lines DL1 connected to at least one data signal line, at least one first power line VL1 connected to at least one first power line, at least one compensation signal line Sense, and a fourth connection electrode 54 and a shielding structure SH located in at least one sub-pixel.

[0244] In an exemplary implementation, such as Figure 9 , Figure 10 , Figure 11 and Figure 12 In the provided display substrate, the shape of the fourth connecting electrode 54 can extend at least partially along the second direction D2, and the orthographic projection of the fourth connecting electrode 54 on the substrate at least partially overlaps with the orthographic projection of the capacitor connection portion of the first plate of the capacitor on the substrate, and is connected to the capacitor connection portion of the first plate of the capacitor.

[0245] In an exemplary implementation, such as Figure 9 , Figure 10 , Figure 11 and Figure 12 In the provided display substrate, the orthographic projection of the blocking structure SH on the substrate at least partially overlaps with the orthographic projection of the first capacitor body portion of the first electrode plate of the capacitor on the substrate. For example, for at least one sub-pixel, the orthographic projection of the blocking structure SH on the substrate is located within the range of the orthographic projection of the first capacitor body portion of the first electrode plate of the capacitor on the substrate.

[0246] In an exemplary implementation, such as Figure 9 , Figure 10 , Figure 11 and Figure 12The outline of the shielding structure SH in the provided display substrate can be rectangular, and the corners of the rectangle can be chamfered. The shielding structure SH is provided with an opening V, which can be rectangular in shape and located in the middle of the shielding structure SH, so that the shielding structure forms a ring structure. The opening V exposes the first capacitor body portion of the first electrode plate of the capacitor, and the orthographic projection of the first capacitor body portion of the first electrode plate of the capacitor on the substrate includes the orthographic projection of the opening V on the substrate. In an exemplary embodiment, the opening V is configured to connect the second electrode of the subsequently formed third transistor to the first electrode plate of the capacitor.

[0247] In an exemplary implementation, such as Figure 9 , Figure 10 , Figure 11 and Figure 12 In the provided display substrate, at least one column of sub-pixel connected data signal lines (Data) are linear in shape and extend at least partially along the second direction D2. The orthographic projection of the at least one column of sub-pixel connected data signal lines (Data) on the substrate at least partially overlaps with the orthographic projection of the first connecting electrode on the substrate, and is connected to the first connecting electrode.

[0248] In an exemplary implementation, such as Figure 9 , Figure 10 , Figure 11 and Figure 12 In the provided display substrate, at least one compensation signal line Sense is linear in shape and extends at least partially along the second direction D2. The orthographic projection of the at least one compensation signal line Sense on the substrate overlaps the orthographic projection of the third connection electrode on the substrate, and the at least one compensation signal line Sense is connected to the third connection electrode.

[0249] In an exemplary implementation, such as Figure 9 , Figure 10 , Figure 11 and Figure 12 In the provided display substrate, the first power connection portion VL1 of at least one first power line is strip-shaped and extends at least partially along the second direction D2. The first power connection portion VL1 of at least one first power line covers the orthographic projection of the second connection electrode on the substrate, and the first power connection portion VL1 of at least one first power line is connected to the second connection electrode.

[0250] In an exemplary embodiment Figure 11 and Figure 12In the provided display substrate, the first data connection portion DL1 of at least one data signal line connected to at least one column of sub-pixels is shaped like a "├" and extends at least partially along the second direction D2. The orthographic projection of the first data connection portion DL1 of the data signal line Data connected to at least one column of sub-pixels on the substrate at least partially overlaps with the orthographic projection of the first connection electrode on the substrate, and is connected to the first connection electrode.

[0251] (3) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate on which the aforementioned pattern is formed, and patterning the semiconductor film using a patterning process to form a first insulating layer covering the substrate and a semiconductor layer pattern disposed on the first insulating layer, such as... Figures 19 to 22 As shown. Figure 19 for Figure 9 , Figure 10 , Figure 11 and Figure 12 A schematic diagram of the semiconductor layer pattern in the image. Figure 20 for Figure 9 and Figure 10 A schematic diagram after the semiconductor layer pattern has been formed. Figure 21 for Figure 11 and Figure 12 A schematic diagram after the semiconductor layer pattern has been formed.

[0252] In an exemplary implementation, such as Figures 19 to 21 As shown, Figure 9 , Figure 10 Figure 11 and Figure 12 The provided display substrate may include the following semiconductor layer patterns: an active pattern 11 of a first transistor, an active pattern 21 of a second transistor, an active pattern 31 of a third transistor, and a second plate C2 of a capacitor.

[0253] In an exemplary embodiment, the active pattern 11 of the first transistor and the second plate C2 of the capacitor are an integral structure interconnected. The active pattern 11 of the first transistor and the active pattern 21 of the second transistor are spaced apart.

[0254] In an exemplary embodiment, in the second direction D2, the active pattern 11 of the first transistor and the active pattern 21 of the second transistor of at least one row of sub-pixels are located on the side of the second plate C2 of the capacitor near the previous row of sub-pixels. The active pattern 11 of the third transistor of at least one row of sub-pixels is located on the side of the second plate C2 of the capacitor near the next row of sub-pixels. In the first direction D1, the active pattern 21 of the second transistor is located on the side of the active pattern 11 of the first transistor near the previous column of sub-pixels.

[0255] In an exemplary embodiment, the active pattern 11 of the first transistor and the active pattern 21 of the second transistor can be in the shape of an "I".

[0256] In an exemplary embodiment, the orthographic projection of the active pattern 11 of the first transistor on the substrate at least partially overlaps with the orthographic projection of at least one data signal line on the substrate.

[0257] In an exemplary embodiment, the orthographic projection of the active pattern 21 of the second transistor onto the substrate at least partially overlaps with the orthographic projection of the fourth connection electrode onto the substrate.

[0258] In an exemplary embodiment, the shape of the active pattern 41 of the third transistor can be rotated 90 degrees to the left to form an "L" shape.

[0259] In an exemplary embodiment, the orthographic projection of the active pattern 31 of the third transistor onto the substrate at least partially overlaps with the orthographic projection of the shielding structure onto the substrate. The orthographic projection of the active pattern 31 of the third transistor onto the substrate partially overlaps with the orthographic projection of the via onto the substrate.

[0260] In an exemplary embodiment, the second plate C2 of the capacitor includes a second capacitor body portion C2-1 and a second capacitor connection portion C2-2. The second capacitor body portion C2-1 is connected to the active pattern 11 of the first transistor through the second capacitor connection portion C2-2.

[0261] In an exemplary embodiment, the second capacitor body portion C2-1 and the second capacitor connection portion C2-2 extend at least partially along the second direction D2, and the width of the second capacitor connection portion C2-2 along the first direction D1 is smaller than the width of the second capacitor body portion C2-2 along the first direction D1.

[0262] In an exemplary embodiment, the orthographic projection of the second capacitor body C2-1 on the substrate at least partially overlaps with the orthographic projection of the first capacitor body of the first plate of the capacitor on the substrate. At least a portion of the orthographic projection of the second capacitor body C2-1 on the substrate is located on the side of the orthographic projection of the occluding structure on the substrate closer to the previous row of sub-pixels. There is no overlap between the orthographic projection of the second capacitor body C2-1 on the substrate and the orthographic projection of the via of the occluding structure on the substrate.

[0263] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region located between the first and second regions. The first and second regions are conductive after the subsequent formation of the third conductive layer and are therefore also referred to as conductive regions. In an exemplary embodiment, the second region 31-2 of the active pattern 31 of the third transistor can simultaneously serve as the second region 41-2 of the active pattern 41 of the fourth transistor. The first region 11-1 of the active pattern 11 of the first transistor, the first region 21-1 and the second region 21-2 of the active pattern 21 of the second transistor, and the first region 31-1 and the second region 31-2 of the active pattern 31 of the third transistor are each separately configured. The second region 11-2 of the active pattern 11 of the first transistor can be connected to the second plate of a capacitor.

[0264] (iv) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: sequentially depositing a second insulating film and a third conductive layer film on a substrate on which the aforementioned pattern is formed, and patterning the third conductive layer film using a patterning process to form a second insulating layer covering the substrate and a third conductive layer film pattern disposed on the second insulating layer, such as... Figures 22 to 27 As shown. Figure 22 for Figure 9 and Figure 11 A schematic diagram of the third conductive layer pattern in the image. Figure 23 for Figure 9 A schematic diagram after the formation of the third conductive layer pattern. Figure 24 for Figure 11 A schematic diagram after the formation of the third conductive layer pattern. Figure 25 for Figure 10 and Figure 12 A schematic diagram of the third conductive layer pattern in the image. Figure 26 for Figure 10 A schematic diagram after the formation of the third conductive layer pattern. Figure 27 for Figure 12 A schematic diagram showing the formation of the third conductive layer pattern. In an exemplary embodiment, the third conductive layer may be referred to as a gate metal (GATE) layer.

[0265] In an exemplary implementation, such as Figure 22 As shown, Figure 9 and Figure 11 In the provided display substrate, the third conductive layer pattern may include: a first scan connection portion GL1 and control electrodes 12 to 32 of the first transistor of at least one sub-pixel.

[0266] In an exemplary implementation, such as Figure 25 As shown, Figure 10 and Figure 12In the provided display substrate, the pattern of the third conductive layer may include: the control electrode 12 of the first transistor of at least one sub-pixel to the control electrode 32 of the third transistor.

[0267] In an exemplary embodiment Figure 9 and Figure 11 In the provided display substrate, the first scan connection portion GL1 is strip-shaped and extends along the first direction D1. The area where the first scan connection portion GL1 overlaps with the active pattern of the first transistor is multiplexed as the control electrode 12 of the first transistor, and the area where the first scan connection portion GL1 overlaps with the active pattern of the second transistor is multiplexed as the control electrode 22 of the second transistor.

[0268] In an exemplary embodiment, the orthographic projection of the second scan connection portion GL2 of the scan signal line on the substrate does not overlap with the orthographic projection of at least one data signal line Data on the substrate.

[0269] In an exemplary embodiment Figure 10 and Figure 12 In the provided display substrate, the control electrode 12 of the first transistor and the control electrode 22 of the second transistor are integrated into a single structure, and the shape of the integrated structure is strip-shaped and extends along the first direction D1.

[0270] In an exemplary embodiment Figure 9 , Figure 10 , Figure 11 and Figure 12 In the provided display substrate, the control electrode 32 of the third transistor is strip-shaped and extends at least partially along the second direction D2.

[0271] In an exemplary embodiment, after the third conductive layer pattern is formed, the third conductive layer can be used as a shield to conduct the semiconductor layer. The semiconductor layer in the region shielded by the third conductive layer forms the channel region of the active pattern of the first transistor to the channel region of the active pattern of the third transistor. The semiconductor layer in the region not shielded by the third conductive layer is conducted, that is, the first and second regions of the active pattern of the first transistor to the active pattern of the third transistor and the second plate of the capacitor are all conducted.

[0272] In an exemplary embodiment, the control electrode 12 of the first transistor is disposed across the active pattern of the first transistor, the control electrode 22 of the second transistor is disposed across the active pattern of the second transistor, and the control electrode 32 of the third transistor is disposed across the active pattern of the third transistor. That is, the extension direction of the control electrode of at least one transistor is perpendicular to the extension direction of the active layer.

[0273] (5) Forming a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern includes: depositing a third insulating film on a substrate having the aforementioned pattern, and patterning the third insulating film using a patterning process to form a third insulating layer pattern covering the aforementioned pattern. The third insulating layer has multiple via patterns, such as... Figure 28 , Figure 29 , Figure 30 and Figure 31 As shown, Figure 28 for Figure 9 A schematic diagram after the third insulating layer pattern has been formed. Figure 29 for Figure 10 A schematic diagram after the third insulating layer pattern has been formed. Figure 30 for Figure 11 A schematic diagram after the third insulating layer pattern has been formed. Figure 31 for Figure 12 A schematic diagram after the third insulating layer pattern has been formed.

[0274] For example, a via penetrating the second and third insulating layers can be formed in a single patterning process.

[0275] For example, a via penetrating the first, second, and third insulating layers can be formed by a single patterning process or by two patterning processes. When a via penetrating the first, second, and third insulating layers is formed by two patterning processes, it includes: forming a via in the second and third insulating layers by a first patterning process, and then forming a via in the first insulating layer by a second patterning process, thereby forming a via penetrating the first, second, and third insulating layers.

[0276] In an exemplary implementation, such as Figure 28 and Figure 29 As shown, Figure 9 and Figure 10 In the provided display substrate, the third insulating layer pattern includes: a first via V1 to an eighth via V8, a ninth via V9, and a tenth via V10 located in at least one sub-pixel.

[0277] In an exemplary implementation, such as Figure 30 and Figure 31 As shown, Figure 11 and Figure 12 In the provided display substrate, the third insulating layer pattern includes: a first via V1 to an eighth via V8 located in at least one sub-pixel, and a ninth via V9, a tenth via V10, and an eleventh via V11.

[0278] In an exemplary embodiment, Figure 9 , Figure 10 , Figure 11 and Figure 12In the provided display substrate, when the data signal line connected to at least one sub-pixel is a single-layer structure, the orthographic projection of the first via V1 on the substrate is located within the range of the first region of the active pattern of the first transistor and the orthographic projection of the data signal line on the substrate. Part of the first insulating layer in the first via V1 is etched away, exposing the surface of the first region of the active pattern of the first transistor. Part of the first insulating layer and the second insulating layer in the first via V1 are etched away, exposing the surface of the data signal line. The first via V1 is configured to allow the first electrode of the subsequently formed first transistor to be connected to the first region of the active pattern of the first transistor and the data signal line through the via.

[0279] In an exemplary embodiment, Figure 11 and Figure 12 In the provided display substrate, when the data signal line connecting the sub-pixels has a double-layer structure, the orthographic projection of the first via V1 on the substrate is located within the range of the first region of the active pattern of the first transistor and the orthographic projection of the first data connection portion on the substrate. Part of the first insulating layer in the first via V1 is etched away, exposing the surface of the first data connection portion. Part of the first insulating layer and the second insulating layer in the first via V1 are etched away, exposing the surface of the first data connection portion. The first via V1 is configured to allow the first electrode of the subsequently formed first transistor to be connected to the first region of the active pattern of the first transistor and the first data connection portion through the via.

[0280] In an exemplary embodiment, Figure 9 , Figure 10 , Figure 11 and Figure 12 In the provided display substrate, the orthographic projection of the second via V2 on the substrate is within the range of the orthographic projection of the second region of the active pattern of the first transistor on the substrate. The second via V2 exposes the surface of the second region of the active pattern of the first transistor. The second via V2 is configured to allow the second electrode of the subsequently formed first transistor to be connected to the second region of the active pattern of the first transistor through the via.

[0281] In an exemplary embodiment, Figure 9 , Figure 10 , Figure 11 and Figure 12 In the provided display substrate, the orthographic projection of the third via V3 on the substrate is located within the orthographic projection range of the first region of the active pattern of the second transistor on the substrate. The third via V3 exposes the surface of the first region of the active pattern of the second transistor. The third via V3 is configured to allow the first electrode of the subsequently formed second transistor to be connected to the first region of the active pattern of the second transistor through the via.

[0282] In an exemplary embodiment, Figure 9 , Figure 10 , Figure 11 and Figure 12 In the provided display substrate, the orthographic projection of the fourth via V4 on the substrate is located within the range of the second region of the active pattern of the second transistor and the orthographic projection of the fourth connection electrode on the substrate. A portion of the first insulating layer within the fourth via V4 is etched to expose the surface of the second region of the active pattern of the second transistor. A portion of the first insulating layer and the second insulating layer within the fourth via V4 are etched to expose the surface of the fourth connection electrode. The fourth via V4 is configured to allow the second electrode of the subsequently formed second transistor to be connected to the second region of the active pattern of the second transistor and the fourth connection electrode through the via.

[0283] In an exemplary embodiment, Figure 9 , Figure 10 , Figure 11 and Figure 12 In the provided display substrate, the orthographic projection of the fifth via V5 on the substrate is located within the orthographic projection range of the first region of the active pattern of the third transistor on the substrate. The fifth via V5 exposes the surface of the first region of the active pattern of the third transistor. The fifth via V5 is configured to allow the first electrode of the subsequently formed third transistor to be connected to the first region of the active pattern of the third transistor through the via.

[0284] In an exemplary embodiment, Figure 9 , Figure 10 , Figure 11 and Figure 12 In the provided display substrate, the orthographic projection of the sixth via V6 on the substrate is located within the range of the second region of the active pattern of the third transistor and the orthographic projection of the via on the substrate. A portion of the first insulating layer within the sixth via V6 is etched to expose the surface of the second region of the active pattern of the third transistor. A portion of the first and second insulating layers within the sixth via V6 are etched to expose the surface of the via. The sixth via V6 is configured to allow the second electrode of the subsequently formed third transistor to be connected to the second region of the active pattern of the third transistor and the first electrode plate of the capacitor through the via.

[0285] In an exemplary embodiment Figure 9 and Figure 11 In the provided display substrate, the orthographic projection of the seventh via V7 onto the substrate lies within the range of the orthographic projection of the first scan connection portion onto the substrate. The seventh via V7 exposes the surface of the first scan connection portion and is configured to allow a subsequently formed second scan connection portion to connect to the first scan connection portion through this via. At least one first scan connection portion is connected to two second scan connection portions through two seventh vias.

[0286] In an exemplary embodiment Figure 10 and Figure 12In the provided display substrate, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the control electrode of the first transistor (which is also the control electrode of the second transistor) on the substrate. The seventh via V7 exposes the surface of the control electrode of the first transistor (which is also the control electrode of the second transistor). The seventh via V7 is configured to allow the subsequently formed scan signal line to be connected to the control electrode of the first transistor (which is also the control electrode of the second transistor) through the via.

[0287] In an exemplary embodiment, Figure 9 , Figure 10 , Figure 11 and Figure 12 In the provided display substrate, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projections of the second plate of the capacitor and the control electrode of the third transistor on the substrate. Part of the eighth via V8 exposes the surface of the control electrode of the third transistor. The first insulating layer in part of the eighth via V8 is etched to expose the surface of the second plate of the capacitor. The eighth via V8 is configured to allow the subsequently formed fifth connection electrode to be connected to the second plate of the capacitor and the control electrode of the third transistor through the via.

[0288] In an exemplary embodiment Figure 9 , Figure 10 , Figure 11 and Figure 12 In the provided display substrate, the orthographic projection of the ninth via V9 on the substrate lies within the range of the orthographic projection of the first power connection portion on the substrate. The ninth via V9 exposes the surface of the first power connection portion and is configured to allow a subsequently formed second power connection portion to connect to the first power connection portion through this via. At least one first power connection portion is connected to two second power connection portions through two ninth vias.

[0289] In an exemplary embodiment Figure 9 , Figure 10 , Figure 11 and Figure 12 In the provided display substrate, the orthogonal projection of the tenth via V10 on the substrate is within the range of the orthogonal projection of the compensation signal line on the substrate. The tenth via V10 exposes the surface of the compensation signal line. The tenth via V10 is configured to allow the subsequently formed compensation connection line to be connected to the compensation signal line through the via.

[0290] In an exemplary implementation, such as Figure 11 and Figure 12In the provided display substrate, the orthographic projection of the eleventh via V11 onto the substrate lies within the orthographic projection of the first data connection portion of at least one data signal line onto the substrate. The first and second insulating layers within the eleventh via V11 are etched away, exposing the surface of the first data connection portion of at least one data signal line. The tenth via V10 is configured to allow the second data connection portions of at least one subsequently formed data signal line to connect to the first data connection portion through this via. At least one first data connection portion is connected to two second data connection portions through two tenth vias.

[0291] (6) Forming a fourth conductive layer pattern includes: depositing a fourth conductive thin film on a substrate on which the aforementioned pattern is formed, and patterning the fourth conductive thin film using a patterning process to form a fourth conductive layer pattern located on the third insulating layer, such as... Figures 32 to 39 As shown, Figure 32 for Figure 9 A schematic diagram of the pattern of the fourth conductive layer. Figure 33 for Figure 9 A schematic diagram after the fourth conductive layer pattern has been formed. Figure 34 for Figure 10 A schematic diagram of the pattern of the fourth conductive layer. Figure 35 for Figure 10 A schematic diagram after the fourth conductive layer pattern has been formed. Figure 36 for Figure 11 A schematic diagram of the pattern of the fourth conductive layer. Figure 37 for Figure 11 A schematic diagram after the fourth conductive layer pattern has been formed. Figure 38 for Figure 12 A schematic diagram of the formation of the fourth conductive layer pattern. Figure 39 for Figure 12 A schematic diagram showing the formation of the fourth conductive layer pattern. In an exemplary embodiment, the fourth conductive layer may be referred to as the source / drain metal (SD) layer.

[0292] In an exemplary embodiment Figure 9 In the provided display substrate, the fourth conductive layer pattern may include at least: a second scan connection portion GL2 of the scan signal line, a second power connection portion VL2 of the first power line, a compensation connection line SL, and a first electrode 13 and a second electrode 14 of the first transistor located in at least one sub-pixel to a first electrode 33 and a second electrode 34 of the third transistor, and a fifth connection electrode 55.

[0293] In an exemplary embodiment Figure 10 In the provided display substrate, the fourth conductive layer pattern may include at least: a scan signal line Gate, a second power connection portion VL2 of a first power line, a compensation connection line SL, and a first electrode 13 and a second electrode 14 of a first transistor located in at least one sub-pixel to a first electrode 33 and a second electrode 34 of a third transistor, and a fifth connection electrode 55.

[0294] In an exemplary embodiment Figure 11 In the provided display substrate, the fourth conductive layer pattern may include at least: a second scan connection portion GL2 of a scan signal line, a second power connection portion VL2 of a first power line, a second data connection portion DL2 of at least one data signal line, a compensation connection line SL, and a first electrode 13 and a second electrode 14 of a first transistor located in at least one sub-pixel to a first electrode 33 and a second electrode 34 of a third transistor and a fifth connection electrode 55.

[0295] In an exemplary embodiment Figure 12 In the provided display substrate, the fourth conductive layer pattern may include at least: a scan signal line Gate, a second power connection portion VL2 of a first power line, a second data connection portion DL2 of at least one data signal line, a compensation connection line SL, and a first electrode 13 and a second electrode 14 of a first transistor located in at least one sub-pixel to a first electrode 33 and a second electrode 34 of a third transistor and a fifth connection electrode 55.

[0296] In an exemplary embodiment, Figure 9 , Figure 10 , Figure 11 and Figure 12 In the provided display substrate, the first electrode 13 of the first transistor has a strip-shaped structure and extends along the first direction D1. When the data signal line connected to at least one sub-pixel has a single-layer structure, the first electrode 13 of the first transistor is connected to the first region of the active pattern of the first transistor and the data signal line through a first via.

[0297] In an exemplary embodiment, Figure 9 , Figure 10 , Figure 11 and Figure 12 In the provided display substrate, the second electrode 14 of the first transistor has a block structure. The second electrode 14 of the first transistor is connected to the second region of the active pattern of the first transistor through a second via. The second electrode 14 of the first transistor is connected to the second plate of the capacitor through the second region of the active pattern of the first transistor.

[0298] In an exemplary embodiment, Figure 9 , Figure 10 , Figure 11 and Figure 12In the provided display substrate, at least one pixel unit contains multiple sub-pixels connected to a compensation connection line SL, which extends at least partially along a first direction D1. The area where the compensation connection line SL overlaps with the first region of the active pattern of the second transistor of at least one sub-pixel can be multiplexed as the first electrode 23 of the second transistor. The compensation connection line is connected to a compensation signal line through a tenth via and to the first region of the active pattern of the second transistor through a third via.

[0299] In an exemplary embodiment, Figure 9 , Figure 10 , Figure 11 and Figure 12 In the provided display substrate, the second electrode 24 of the second transistor is a strip-shaped structure and extends along the second direction D2. The second electrode 24 of the second transistor is connected to the second region of the active pattern of the second transistor and the fourth connection electrode through a fourth via.

[0300] In an exemplary embodiment, Figure 9 , Figure 10 , Figure 11 and Figure 12 In the provided display substrate, the first electrode 33 of the third transistor in the first and fourth sub-pixels is a block structure. The first electrode 33 of the third transistor in the second sub-pixel is in the shape of a "└" and the first electrode 33 of the third transistor in the third sub-pixel is in the shape of a "┘". The first electrode 33 of the third transistor is connected to the first region of the active pattern of the third transistor through a fifth via.

[0301] In an exemplary embodiment, Figure 9 , Figure 10 , Figure 11 and Figure 12 In the provided display substrate, the second electrode 34 of the third transistor of at least one sub-pixel is a strip structure and extends at least partially along the second direction D2. The second electrode 34 of the third transistor is connected to the second region of the active pattern of the third transistor and the first plate of the capacitor through a sixth via.

[0302] In an exemplary embodiment, Figure 9 , Figure 10 , Figure 11 and Figure 12 In the provided display substrate, the fifth connection electrode 55 of at least one sub-pixel is a strip structure and extends at least partially along the second direction D2. The fifth connection electrode 55 is connected to the control electrode of the third transistor and the second plate of the capacitor through an eighth via.

[0303] In an exemplary embodiment, Figure 9 , Figure 10 , Figure 11 and Figure 12In the provided display substrate, the main body of the second power connection portion VL2 extends along the second direction D2. The second power connection portion is integrally formed with the first electrode of the third transistor in the first and second sub-pixels of one of the at least two adjacent pixel units, and is also integrally formed with the first electrodes of the third transistors in the third and fourth sub-pixels of the other at least two adjacent pixel units. The second power connection portion VL2 is connected to the first power connection portion through an eighth via.

[0304] In an exemplary embodiment, Figure 9 and Figure 11 In the provided display substrate, the second scan connection portion GL2 of the scan signal line is a horizontally shaped "dumbbell". The second scan connection portion GL2 of the scan signal line is electrically connected to the first scan connection portion through a seventh via.

[0305] In an exemplary embodiment, Figure 10 and Figure 12 In the provided display substrate, the scan signal line Gate is linear in shape, and its main body extends along the first direction D1. The scan signal line is electrically connected to the control electrode (which is also the control electrode of the second transistor) of at least one sub-pixel through a seventh via.

[0306] In an exemplary implementation, such as Figure 10 and Figure 12 As shown, the second data connection portion DL2 of at least one data signal line is strip-shaped and extends along the second direction D2. The second data connection portion DL2 of at least one data signal line is connected to the first data connection portion DL1 through an eleventh via.

[0307] (7) Forming a planarization layer pattern includes: depositing a fourth insulating film on a substrate having the aforementioned pattern; coating a first planarization film on the fourth insulating film; and patterning the fourth insulating film and the planarization film using a patterning process to form a fourth insulating layer and a planarization layer. The planarization layer pattern has multiple via patterns, such as... Figures 40 to 43 As shown, Figure 40 for Figure 9 A schematic diagram after the planarization layer pattern has been formed. Figure 41 for Figure 10 A schematic diagram after the planarization layer pattern has been formed. Figure 42 for Figure 11 A schematic diagram after the planarization layer pattern has been formed. Figure 43 for Figure 12 A schematic diagram after the flattened layer pattern has been formed.

[0308] In an exemplary embodiment, Figure 9 , Figure 10 , Figure 11 and Figure 12In the provided display substrate, the fourth insulating layer pattern includes at least one via: a twelfth via V12 located in at least one sub-pixel.

[0309] In an exemplary implementation, such as Figures 40 to 43 As shown, the orthogonal projection of the twelfth via V12 on the substrate is within the range of the orthogonal projection of the second electrode of the third transistor on the substrate. The fourth insulating layer inside the twelfth via V12 is etched away, exposing the surface of the second electrode of the third transistor. The twelfth via V12 is configured to allow the anode of the subsequently formed light-emitting device to be connected to the second electrode of the third transistor through the via.

[0310] At this point, the driving structure layer is fabricated on the substrate. In a plane parallel to the display substrate, the driving structure layer may include multiple pixel driving circuits, which are connected to scan signal lines, data signal lines, compensation signal lines, and a first power supply line. The driving structure layer may be disposed on the substrate. The driving structure layer may include, sequentially disposed on the substrate, a first conductive layer, a second conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a third conductive layer, a third insulating layer, a fourth conductive layer, a fourth insulating layer, and a planarization layer.

[0311] In an exemplary embodiment, the semiconductor layer can be an amorphous silicon layer, a polycrystalline silicon layer, or a metal oxide layer. The metal oxide layer can be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer can be a single layer, a double layer, or a multilayer.

[0312] In an exemplary embodiment, the first conductive layer may be a transparent conductive layer. The first conductive layer may be a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or it may be a multi-layer composite structure, such as ITO / Ag / ITO.

[0313] In an exemplary embodiment, the second, third, and fourth conductive layers can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo.

[0314] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.

[0315] In an exemplary embodiment, the planarization layer may be made of organic materials, such as resin.

[0316] In an exemplary embodiment, after the driving structure layer is prepared, a light-emitting structure layer is prepared on the driving structure layer. The preparation process of the light-emitting structure layer may include the following operations.

[0317] (8) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming a fifth conductive layer pattern may include: depositing a fifth conductive film on a substrate on which the aforementioned pattern is formed, patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on a second planarization layer, wherein the fifth conductive layer includes at least a plurality of first electrode patterns. Figures 44 to 48 As shown, Figure 44 for Figure 9 , Figure 10 , Figure 11 and Figure 12 A schematic diagram of the fifth conductive layer pattern. Figure 45 for Figure 9 A schematic diagram after the fifth conductive layer pattern has been formed. Figure 46 for Figure 10 A schematic diagram after the fifth conductive layer pattern has been formed. Figure 47 for Figure 11 A schematic diagram after the fifth conductive layer pattern has been formed. Figure 48 for Figure 12 A schematic diagram after the fifth conductive layer pattern has been formed.

[0318] In an exemplary embodiment, the fifth conductive layer pattern may include: anodes 61 of a plurality of light-emitting devices.

[0319] In an exemplary embodiment, the anode of the light-emitting device can be connected to the second electrode of the third transistor of the sub-pixel through the twelfth via of the sub-pixel.

[0320] In an exemplary embodiment, the fifth conductive layer adopts a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or it can adopt a multi-layer composite structure, such as ITO / Ag / ITO.

[0321] (9) Forming a sixth conductive layer pattern. In an exemplary embodiment, forming a sixth conductive layer may include: coating a pixel definition film on a substrate on which the aforementioned pattern is formed; depositing a pixel definition film on the substrate on which the aforementioned pattern is formed; patterning the pixel definition film using a patterning process to form a pixel definition layer pattern that exposes the fifth conductive layer pattern; coating an organic light-emitting material on a substrate on which the pixel definition layer pattern is formed; patterning the organic light-emitting material using a patterning process to form an organic structure layer pattern; depositing a sixth conductive film on a substrate on which the organic material layer pattern is formed; and patterning the sixth conductive film using a patterning process to form a sixth conductive layer.

[0322] In an exemplary embodiment, the subsequent fabrication process may include: forming an encapsulation structure layer on the sixth conductive layer. The encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0323] In an exemplary embodiment, the organic structure layer may include at least an organic light-emitting layer of a light-emitting device.

[0324] In an exemplary embodiment, the sixth conductive layer may include at least: the second electrode (cathode) of a plurality of light-emitting devices.

[0325] In an exemplary embodiment, the sixth conductive layer may be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. Exemplarily, the fourth conductive layer may be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0326] The display substrate described in this embodiment can be used in display products of any resolution.

[0327] This disclosure also provides a display device, including a display substrate.

[0328] The display substrate is the same as the display substrate provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0329] In an exemplary embodiment, the display device can be any product or component with display function, such as electronic paper, OLED panel, active-matrix organic light emitting diode (AMOLED) panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc.

[0330] The accompanying drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0331] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0332] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, characterized by, include: The substrate and a plurality of sub-pixels, a plurality of first power lines and a plurality of scan signal lines disposed on the substrate, wherein at least one sub-pixel includes: a pixel driving circuit, wherein the pixel driving circuit is connected to the first power lines and the scan signal lines respectively, and the pixel driving circuit includes: at least one transistor, wherein the transistor includes: an active pattern, a first electrode and a second electrode; The scanning signal line extends at least partially along a first direction, and the first power line includes: a plurality of first power connection portions and a plurality of second power connection portions. In a second direction, the plurality of first power connection portions and the plurality of second power connection portions are alternately arranged and interconnected. The first power connection portions and the second power connection portions extend at least partially along a second direction, and the first direction and the second direction intersect. In a direction perpendicular to the display substrate, the first power connection portion is located on the side of the active pattern of at least one transistor close to the substrate, the second power connection portion is disposed on the same layer as the first and second electrodes of at least one transistor, and the orthographic projection of the first power connection portion on the substrate at least partially overlaps with the orthographic projection of the scan signal line on the substrate. 2.The display substrate of claim 1, wherein, At least one transistor includes: a driving transistor; the display substrate further includes: a blocking structure located at at least one sub-pixel; The shielding structure is disposed on the same layer as the first power connection portion, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the active pattern of the driving transistor on the substrate.

3. The display substrate according to claim 1, characterized in that, The sub-pixel includes: a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel. The first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel constitute a pixel unit. The first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are arranged sequentially along a first direction. The first power line connecting the first sub-pixel and the second sub-pixel is located on the side of the first sub-pixel away from the second sub-pixel, and the first power line connecting the third sub-pixel and the fourth sub-pixel is located on the side of the fourth sub-pixel away from the third sub-pixel. The distance between the orthographic projection of the occlusion structure of the first sub-pixel on the substrate and the orthographic projection of the first power line connecting the first sub-pixel and the second sub-pixel on the substrate along the first direction is less than 0.5 times the linewidth of the first power line connecting the first sub-pixel and the second sub-pixel. The distance between the orthographic projection of the occlusion structure of the fourth sub-pixel on the substrate and the orthographic projection of the first power line connecting the third and fourth sub-pixels on the substrate along the first direction is less than 0.5 times the linewidth of the first power line connecting the third and fourth sub-pixels.

4. The display substrate according to claim 3, characterized in that, The shielding structure includes: a first shielding part and a second shielding part, the first shielding part and the second shielding part are arranged along a first direction, and the length of the first shielding part along a second direction is less than the length of the second shielding part along the second direction, and the first direction intersects the second direction; In the occlusion structure of the first sub-pixel, the first occlusion part is located on the side of the second occlusion part near the first power line connecting the first sub-pixel and the second sub-pixel; in the occlusion structure of the fourth sub-pixel, the first occlusion part is located on the side of the second occlusion part near the first power line connecting the third sub-pixel and the fourth sub-pixel. The distance between the orthographic projection of the first occluding part in the occluding structure of the first sub-pixel on the substrate and the orthographic projection of the first power line connecting the first sub-pixel and the second sub-pixel on the substrate along the first direction is less than 0.5 times the line width of the first power line connecting the first sub-pixel and the second sub-pixel; The distance between the orthographic projection of the first occluding part in the occluding structure of the fourth sub-pixel on the substrate and the orthographic projection of the first power line connecting the third and fourth sub-pixels on the substrate along the first direction is less than 0.5 times the linewidth of the first power line connecting the third and fourth sub-pixels.

5. The display substrate of claim 1, wherein, At least a portion of the scan signal lines that overlap with the first power connection portion are disposed in the same layer as the second power connection portion and are located in the film layer where the first and second electrodes of at least one transistor are located. 6.The display substrate of claim 2, wherein, Also includes: Multiple data signal lines disposed on the substrate, at least one of the data signal lines extending at least partially along the second direction, the pixel driving circuit further includes: a capacitor, the capacitor including: a first electrode plate and a second electrode plate; For at least one sub-pixel, the distance between the orthographic projection of at least one of the first and second plates of the capacitor on the substrate and the orthographic projection of the data signal line connected to the sub-pixel on the substrate along a first direction is greater than the line width of the data signal line connected to the sub-pixel, and the first direction intersects the second direction. 7.The display substrate of claim 6, wherein, The data signal line has a single-layer structure and is arranged on the same layer as the shielding structure. 8.The display substrate of claim 6, wherein, The data signal line includes: a first data signal line and a second data signal line. For at least one pixel unit, the data signal line connected to at least one sub-pixel is the first data signal line, and the data signal line connected to at least one sub-pixel is the second data signal line. The first data signal line has a single-layer structure, and the second data signal line has a double-layer structure. 9.The display substrate of claim 8, wherein, At least one sub-pixel further includes: a light-emitting device, the light-emitting device including: an anode, the display substrate further includes: a pixel definition layer, the pixel definition layer being provided with a pixel opening, the anode of the light-emitting device being connected to a pixel driving circuit through the pixel opening, and the orthographic projection of the pixel opening on the substrate being located within the range of the orthographic projection of the anode of the light-emitting device on the substrate; The first plate of the capacitor includes a first capacitor body and a first capacitor connection part; the second plate of the capacitor includes a second capacitor body and a second capacitor connection part; the display substrate further includes a plurality of compensation signal lines disposed on the substrate. The orthographic projection of the pixel opening of at least one sub-pixel on the substrate at least partially overlaps with the orthographic projections of the first capacitor connection portion, the second capacitor connection portion and the second capacitor body portion on the substrate, and has no overlapping area with the orthographic projections of at least one transistor and at least one of the data signal lines, the first power line, the scan signal line and the compensation signal line on the substrate. The second length is greater than the first length, wherein the first length is the length of the pixel opening of the sub-pixel connected to the first data signal line along the first direction, and the second length is the length of the pixel opening of the sub-pixel connected to the second data signal line along the first direction; The third length is less than the fourth length, wherein the third length is the minimum length of at least one of the first capacitor body portion and the second capacitor body portion of the sub-pixel connected to the first data signal line along the first direction, and the fourth length is the minimum length of at least one of the first capacitor body portion and the second capacitor body portion of the sub-pixel connected to the second data signal line along the first direction.

10. The display substrate according to claim 9, characterized in that, The difference between the second length and the first length is greater than 0.5 times the line width of the first data signal line; The difference between the fourth length and the third length is greater than 0.5 times the line width of the first data signal line. 11.The display substrate of claim 10, wherein, The difference between the second length and the first length is greater than 3 micrometers; The difference between the fourth length and the third length is greater than 3 micrometers.

12. The display substrate according to claim 6, characterized in that, The sub-pixel includes: a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel. The first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel constitute a pixel unit. The first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are arranged sequentially along a first direction. The data signal lines connected to the first sub-pixel and the data signal lines connected to the second sub-pixel are located between the first sub-pixel and the second sub-pixel, and the data signal lines connected to the third sub-pixel and the data signal lines connected to the fourth sub-pixel are located between the third sub-pixel and the fourth sub-pixel. The data signal line connecting one of the first sub-pixels and the second sub-pixel is the first data signal line, and the data signal line connecting the other sub-pixel is the second data signal line. The data signal line connected to one of the third and fourth sub-pixels is the first data signal line, and the data signal line connected to the other sub-pixel is the second data signal line. The first data signal line is disposed on the same layer as the first power connection portion. The second data signal line includes: a plurality of first data connection portions and a plurality of second data connection portions. In the second direction, the plurality of first data connection portions and the plurality of second data connection portions are arranged alternately and connected to each other. At least one of the first data connection portions and the second data connection portions extends at least partially along the second direction. The first data connection portion and the first power connection portion are disposed on the same layer, and their orthographic projections on the substrate and the orthographic projections of the scan signal line on the substrate at least partially overlap. The second data connection portion and the second power connection portion are disposed on the same layer, and the length of the second data connection portion along the second direction is less than the length of the second power connection portion along the second direction. 13.The display substrate of claim 2, wherein, The pixel driving circuit further includes a capacitor, which includes a first electrode plate and a second electrode plate. The shielding structure is located on the side of the first plate of the capacitor away from the substrate and on the side of the second plate of the capacitor close to the substrate. The second plate of the capacitor is disposed on the same layer as the active pattern of at least one transistor. 14.The display substrate of claim 13, wherein, The orthographic projection of at least one of the second plate of the capacitor and the shielding structure onto the substrate at least partially overlaps with the orthographic projection of the first plate of the capacitor onto the substrate.

15. The display substrate according to claim 13, characterized in that, For at least one sub-pixel, the occlusion structure is provided with a via, the via exposing the first plate of the capacitor; The orthographic projection of the active pattern of the driving transistor on the substrate at least partially overlaps with the orthographic projection of the via on the substrate; A composite insulating layer is provided between the film layer containing the first and second electrodes of the at least one transistor and the film layer containing the shielding structure. The composite insulating layer is provided with a connection via. The orthographic projection of the connection via on the substrate is within the range of the orthographic projection of the via on the substrate. The second electrode of the driving transistor is electrically connected to the first plate of the capacitor through the connection via and the via. 16.The display substrate of claim 13, wherein, The first plate of the capacitor includes: a first capacitor body and a first capacitor connection part connected to each other, the first capacitor connection part is located on one side of the first capacitor body part, and the length of the first capacitor connection part along the first direction is less than the length of the first capacitor body part along the first direction. The second plate of the capacitor includes: a second capacitor body and a second capacitor connection part connected to each other, the second capacitor connection part being located on one side of the second capacitor body part, and the length of the second capacitor connection part along the first direction being less than the length of the second capacitor body part along the first direction. The orthographic projection of the first capacitor body on the substrate at least partially overlaps with the orthographic projection of the second capacitor body on the substrate, and at least partially overlaps with the orthographic projection of the shielding structure on the substrate. The orthographic projections of the first capacitor connection portion on the substrate and the orthographic projections of the second capacitor connection portion on the substrate are arranged along a first direction. 17.The display substrate of claim 16, wherein, The region where the orthographic projection of the first capacitor body portion on the substrate is located includes: a first region and a second region, the first region and the second region being arranged along a second direction, and the second region being located on the side of the first region away from the first capacitor connection portion; The orthographic projection of the second capacitor body onto the substrate is at least partially located in the first region, and the orthographic projection of the shielding structure onto the substrate is at least partially located in the second region.

18. The display substrate according to claim 1, characterized in that, The scanning signal line has a single-layer structure and is disposed on the same layer as the second power connection part. 19.The display substrate of claim 1, wherein, The scan signal line includes: a plurality of first scan connection portions and a plurality of second scan connection portions; in the first direction, the plurality of first scan connection portions and the plurality of second scan connection portions are alternately arranged and interconnected with each other, and at least one of the first scan connection portions and the second scan connection portions extends at least partially along the first direction; the transistor further includes: a control electrode. The first scan connection portion is disposed on the same layer as the control electrode of at least one transistor, and the second scan connection portion is disposed on the same layer as the second power supply connection portion. 20.The display substrate of claim 19, wherein, Also includes: Multiple data signal lines and multiple compensation signal lines are disposed on the substrate, and the sub-pixels are electrically connected to the data signal lines and the compensation signal lines respectively. The orthographic projection of at least one second scan connection portion on the substrate at least partially overlaps with the orthographic projection of at least one of the structures of the data signal line, the compensation signal line, and the first power connection portion on the substrate.

21. The display substrate according to claim 1, characterized in that, Also includes: Multiple compensation signal lines are disposed on the substrate, the sub-pixels are connected to the compensation signal lines, and the compensation signal lines extend at least partially along the second direction; The compensation signal line is disposed on the same layer as the first power connection part, and at least one sub-pixel in the same pixel unit is connected to the same compensation signal line. 22.The display substrate of claim 1, wherein, The sub-pixel includes: a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel. The first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel constitute a pixel unit. The first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are arranged sequentially along a first direction. The first power line connecting the first sub-pixel and the second sub-pixel is located on the side of the first sub-pixel away from the second sub-pixel, and the first power line connecting the third sub-pixel and the fourth sub-pixel is located on the side of the fourth sub-pixel away from the third sub-pixel. The first power line connecting the first sub-pixel and the second sub-pixel of one of two adjacent pixel units arranged along the first direction is the same signal line as the first power line connecting the third sub-pixel and the fourth sub-pixel of the other pixel unit. In at least one pixel unit, the distance between the first boundary of the control electrode of the driving transistor of at least one of the first sub-pixels and the fourth sub-pixels and the second boundary of the first power line connecting the first sub-pixel and the fourth sub-pixel along a first direction is greater than 11.5 micrometers; The first boundary is the boundary of the control electrode of the driving transistor of at least one of the first sub-pixels and the fourth sub-pixels near the boundary of the first power line connecting the first sub-pixel and the fourth sub-pixel. The second boundary is the boundary of the first power line connecting the first sub-pixel and the fourth sub-pixel near the boundary of the control electrode of the driving transistor of the first sub-pixel and the fourth sub-pixel. 23.The display substrate of claim 2, wherein, Also includes: The pixel driving circuit further includes a compensation signal line and a capacitor, which includes a first plate and a second plate. The display substrate further includes: a driving structure layer disposed on the substrate, the driving structure layer including: a first conductive layer, a second conductive layer, a semiconductor layer, a third conductive layer and a fourth conductive layer sequentially stacked on the substrate; the transistor further includes: a control electrode; The first conductive layer includes at least: the first electrode of the capacitor of at least one sub-pixel; The second conductive layer includes at least: a shading structure for at least one sub-pixel, a compensation signal line, and a first power connection portion for at least one first power line; The semiconductor layer includes at least: an active pattern of at least one transistor in at least one sub-pixel and a second plate of a capacitor; The third conductive layer includes at least: the control electrode of at least one transistor of at least one sub-pixel; The fourth conductive layer includes at least: a first electrode and a second electrode of at least one transistor of at least one sub-pixel, and a second power connection portion of at least one first power line; The first conductive layer and the semiconductor layer are transparent films.

24. The display substrate according to claim 23, characterized in that, Also includes: When the data signal line has a single-layer structure, the data signal line is located in the second conductive layer; When the data signal line includes a first data connection portion and a second data connection portion, the first data connection portion is located in the second conductive layer, and the second data connection portion is located in the fourth conductive layer. 25.The display substrate of claim 23, wherein, When the scanning signal line has a single-layer structure, the scanning signal line is located in the fourth conductive layer; When the scanning signal line includes a first scanning connection portion and a second scanning connection portion, the first scanning connection portion is located in the third conductive layer, and the second scanning connection portion is located in the fourth conductive layer.

26. A display device comprising: include: The display substrate as described in any one of claims 1 to 25.

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