Substrate

Abstract

The utility model provides a substrate which comprises a base layer, a stacked structure and a graphene layer, the base layer is provided with a front face and a back face which are oppositely arranged, the stacked structure is at least located on the front face of the base layer, the graphene layer is at least located on the surface, away from the substrate, of the stacked structure, and the stacked structure comprises at least two stress buffer layers. The thermal expansion coefficient of each stress buffer layer is between the thermal expansion coefficient of the base layer and the thermal expansion coefficient of the graphene layer, and the thermal expansion coefficient of the stress buffer layer closer to the base layer is larger. The graphene layer can rapidly dissipate heat, improve the heat dissipation performance of the substrate, reduce the working temperature of a device on the substrate and improve the stability, the at least two stress buffer layers are utilized to form a thermal expansion coefficient transition area between the graphene layer and the base layer, thermal stress concentration can be reduced, and the reliability of the substrate is improved. The problems of bonding layer breakage, interface stripping or substrate cracking / deformation and the like are reduced, the service life of the substrate is prolonged, the stress buffer layer can assist in heat dissipation, and the heat dissipation efficiency of the substrate is further improved.

Description

Technical Field

[0001] This application relates to the field of LED technology, specifically to a substrate. Background Technology

[0002] In the field of LED packaging, the substrate plays a crucial role. Currently, the mainstream substrates are resin substrates, metal substrates, and ceramic substrates. However, metal substrates are widely used due to their superior thermal conductivity, electrical insulation, and machinability. The base material of metal substrates is often aluminum, copper, or iron, but copper is expensive and iron has poor stability, making aluminum-based metal substrates the most widely used.

[0003] With the continuous development of LED technology, the requirements for heat dissipation performance of substrates are becoming increasingly stringent. Traditional metal substrates used for LED packaging still suffer from poor heat dissipation performance and heat accumulation, which leads to accelerated light decay and shortened lifespan. In particular, when multi-chip array packaging is used, the heat superposition effect is significant, resulting in problems such as bonding layer breakage, interface peeling, and substrate cracking or deformation. Utility Model Content

[0004] In view of this, the embodiments of this application aim to provide a substrate to solve the problems of difficult heat dissipation and thermal stress concentration in the prior art.

[0005] This application provides a substrate including a base layer, a stacked structure, and a graphene layer. The base layer has a front side and a back side disposed opposite to each other. The stacked structure is located at least on the front side of the base layer, and the graphene layer is located at least on the surface of the stacked structure opposite to the base layer.

[0006] The stacked structure includes at least two stress buffer layers, each of which has a thermal expansion coefficient between that of the base layer and that of the graphene layer, with the thermal expansion coefficient of the stress buffer layer being greater the closer it is to the base layer.

[0007] In some embodiments, the stress buffer layer includes a stacked first stress buffer layer and at least one second stress buffer layer, wherein the first stress buffer layer is closer to the base layer than the second stress buffer layer, the first stress buffer layer is a non-porous structure, or the first stress buffer layer has at least one first through hole and the second stress buffer layer has at least one second through hole;

[0008] The diameter of the first through hole is larger than that of the second through hole, the porosity of the first stress buffer layer is smaller than that of the second stress buffer layer, and the closer the second stress buffer layer is to the base layer, the larger the diameter of the second through hole and the smaller the porosity.

[0009] In some embodiments, at least a portion of the second through holes in two adjacent second stress buffer layers are connected to each other; and / or, at least a portion of the first through holes in the first stress buffer layer are connected to at least a portion of the second through holes in adjacent second stress buffer layers.

[0010] In some embodiments, the first through hole is a hole of constant diameter, or the diameter of the first through hole gradually increases along the direction close to the substrate, and the minimum diameter of the first through hole is greater than or equal to 20% of its maximum diameter; and,

[0011] The second through hole is a hole of equal diameter, or the diameter of the second through hole gradually increases along the direction close to the base layer, and the minimum diameter of the second through hole is greater than or equal to 20% of its maximum diameter.

[0012] In some embodiments, the base layer is made of aluminum, and the second stress buffer layer has three layers, with the first to third layers of the second stress buffer layer stacked sequentially on the surface of the first stress buffer layer away from the base layer. The coefficient of thermal expansion of the first stress buffer layer is 16 × 10⁻⁶. -6 / K~18×10 -6 / K, the coefficients of thermal expansion of the first to third layers of the second stress buffer layer are 12×10. -6 / K~14×10 -6 / K、9×10 -6 / K~10×10 -6 / K and 7×10 -6 / K~8×10 -6 / K.

[0013] In some embodiments, the second stress buffer layer has three layers, with the first to third layers of the second stress buffer layer stacked sequentially on the surface of the first stress buffer layer away from the base layer. The pore sizes of the first to third layers of the second stress buffer layer are 200nm to 500nm, 50nm to 200nm, and 10nm to 50nm, respectively, and the porosities are 10% to 20%, 20% to 30%, and 30% to 50%, respectively.

[0014] In some embodiments, the stacked structure is located on the front side of the base layer, and the graphene layer is also located on the back side of the base layer.

[0015] In some embodiments, the stacked structures are located on the front and back sides of the base layer, and the graphene layers are located on the surfaces of the two stacked structures facing away from the base layer.

[0016] In some embodiments, the thickness of the graphene layer is 0.5 μm to 2 μm.

[0017] In some embodiments, the substrate is a packaging substrate for LED chips.

[0018] This application provides a substrate including a base layer, a stacked structure, and a graphene layer. The base layer has a front side and a back side disposed opposite to each other. The stacked structure is located at least on the front side of the base layer, and the graphene layer is located at least on the surface of the stacked structure opposite to the base layer. The stacked structure includes at least two stress buffer layers, and the coefficient of thermal expansion of each stress buffer layer is between the coefficient of thermal expansion of the base layer and the coefficient of thermal expansion of the graphene layer, with the coefficient of thermal expansion of the stress buffer layer being larger the closer it is to the base layer. On the one hand, the graphene layer in this application can dissipate heat quickly, improve the heat dissipation performance of the substrate, reduce the operating temperature of the devices on the board, and improve stability. On the other hand, this application utilizes at least two stress buffer layers to form a transition region of thermal expansion coefficient between the graphene layer and the base layer (the thermal expansion coefficient of the graphene layer increases from small to large in the direction from the base layer to the base layer), thereby reducing thermal stress concentration, reducing problems such as bonding layer breakage, interface peeling, or substrate cracking / deformation, and extending the life of the substrate. The stress buffer layer can also assist in heat dissipation, further improve the heat dissipation efficiency of the substrate, realize a substrate with high thermal conductivity suitable for high heat flux scenarios, and also support the evolution of electronic devices towards higher power, smaller size, and longer life. Attached Figure Description

[0019] Figure 1 This is a schematic cross-sectional view of a substrate provided in an embodiment of this application.

[0020] Figure 2 A top view of a first stress buffer layer provided in an embodiment of this application.

[0021] Figure 3 This is a top view of a first second stress buffer layer provided in an embodiment of this application.

[0022] Figure 4 This is a top view of the second stress buffer layer provided in an embodiment of this application.

[0023] Figure 5 This is a top view of the third second stress buffer layer provided in an embodiment of this application.

[0024] Figure 6 This is a cross-sectional structural diagram of another substrate provided in one embodiment of this application.

[0025] Figure 7 This is a cross-sectional structural schematic diagram of another substrate provided in an embodiment of this application.

[0026] The attached figures are labeled as follows:

[0027] 100 - Base layer; 200 - Stacked structure; 200a - First through hole; 200b - Second through hole; 201 - First stress buffer layer; 202 - First second stress buffer layer; 203 - Second second stress buffer layer; 204 - Third second stress buffer layer; 300 - Graphene layer. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0029] Figure 1 This is a schematic cross-sectional view of a substrate provided in one embodiment of this application. Figure 1 As shown, one embodiment of this application provides a substrate including a base layer 100, a stacked structure 200, and a graphene layer 300. The base layer 100 has a front side and a back side disposed opposite to each other. The stacked structure 200 is located at least on the front side of the base layer 100, and the graphene layer 300 is located at least on the surface of the stacked structure 200 away from the base layer 100. The stacked structure 200 includes at least two stress buffer layers. The coefficient of thermal expansion of each stress buffer layer is between the coefficient of thermal expansion of the base layer 100 and the coefficient of thermal expansion of the graphene layer 300, and the coefficient of thermal expansion of the stress buffer layer closer to the base layer 100 is larger. On the one hand, the graphene layer 300 in this application can dissipate heat quickly, improve the heat dissipation performance of the substrate, reduce the operating temperature of the devices on the board, and improve stability. On the other hand, this application utilizes at least two stress buffer layers to form a transition region of thermal expansion coefficient between the graphene layer 300 and the base layer 100 (the thermal expansion coefficient in the direction from the graphene layer 300 to the base layer 100 increases from small to large), thereby reducing thermal stress concentration, reducing problems such as bonding layer breakage, interface peeling, or substrate cracking / deformation, and extending the life of the substrate. In addition, the stress buffer layer can also assist in heat dissipation, further improve the heat dissipation efficiency of the substrate, realize a substrate with high thermal conductivity suitable for high heat flow scenarios, and also support the evolution of electronic devices towards higher power, smaller size, and longer life.

[0030] Specifically, the substrate can be a packaging substrate for LED chips. In this case, the substrate can be a metal substrate, and the material of the base layer 100 can be a metallic material, such as aluminum, iron, or copper, but it should not be limited to this. The substrate can also be other circuit boards. In this case, the material of the base layer 100 can also be a dielectric material, such as AlN, Al2O3, SiO, SiO2, Si3N4, or SiON. The base layer 100 has a front and a back side. The front side of the base layer 100 is usually used to set core electronic components (such as LED chips). These electronic components generate a lot of heat when they are working. This heat needs to be conducted away in a timely manner to avoid heat accumulation affecting the normal operation of the electronic components. In some embodiments, the back side of the base layer 100 can also be used to set some electronic components (such as driver chips, control chips, etc.). In this case, the back side of the base layer 100 will also have a heat source and needs to be dissipated.

[0031] The stacked structure 200 includes at least two stress-buffering layers, each with a coefficient of thermal expansion between that of the base layer 100 and that of the graphene layer 300. For example, the base layer 100 is made of aluminum, which has a coefficient of thermal expansion of 23 × 10⁻⁶. -6 / K, while the material of graphene layer 300 is graphene, whose coefficient of thermal expansion can be -1.5×10. -6 / K~-6×10 -6 / K (assuming it is -2×10) -6 / K), at this point, the coefficient of thermal expansion of each stress buffer layer needs to be between -2×10 -6 / K~23×10 -6 Between / K. Furthermore, the thermal expansion coefficient of the stress buffer layer is greater the closer it is to the base layer 100. In this way, the stacked structure 200 can form a transition region of thermal expansion coefficient between the graphene layer 300 and the base layer 100 (the thermal expansion coefficient from small to large in the direction from the graphene layer 300 to the base layer 100), so that the thermal expansion coefficient of the stress buffer layer gradually transitions to match the thermal expansion coefficient of the base layer 100. This can reduce thermal stress concentration, reduce problems such as bonding layer breakage, interface peeling, or substrate cracking / deformation, and extend the life of the substrate. At the same time, each stress buffer layer also has a certain thickness, and heat can be dissipated through the side of each stress buffer layer, thereby improving the heat dissipation performance of the substrate.

[0032] Furthermore, the stress buffer layer may include a stacked first stress buffer layer 201 and at least one second stress buffer layer, wherein the first stress buffer layer 201 is closer to the base layer 100 than the second stress buffer layer. The first stress buffer layer 201 may be a non-porous structure, or it may have at least one first through-hole 200a, and the second stress buffer layer may have at least one second through-hole 200b. The diameter of the first through-hole 200a is larger than that of the second through-hole 200b, and the porosity of the first stress buffer layer 201 is smaller than that of the second stress buffer layer. Furthermore, the closer the second stress buffer layer is to the base layer 100, the larger the diameter of the second through-hole 200b and the smaller its porosity. In this way, by forming through-holes of different diameters in different stress buffer layers and controlling the porosity of different stress buffer layers, the coefficient of thermal expansion of the first stress buffer layer 201 can be greater than that of the second stress buffer layer, and the coefficient of thermal expansion of the second stress buffer layer closer to the base layer 100 can be greater. In other words, by drilling holes in at least part of the stress buffer layer, the thermal expansion coefficient of each stress buffer layer can be easily and effectively controlled by controlling the pore size and porosity of the through holes in the stress buffer layer. At the same time, the through holes in the stress buffer layer are also conducive to heat transfer, further improving the heat dissipation performance of the substrate. In addition, the through holes in the stress buffer layer can also provide deformation space for thermal expansion / contraction, indirectly reducing the internal stress caused by the geometric constraints inside the substrate, thereby further reducing the deformation of the substrate.

[0033] In some embodiments, each stress buffer layer can be made of graphene composite material. For example, the first stress buffer layer 201 and the second stress buffer layer can both contain graphene, and the graphene content in the first stress buffer layer 201 and the second stress buffer layer is the same. That is, the first stress buffer layer 201 and the second stress buffer layer are made of the same material, differing only in the presence or absence of through holes and the size and porosity of the through holes. This reduces the difficulty of fabricating the first stress buffer layer 201 and the second stress buffer layer. Simultaneously, the stress buffer layer composed of a two-dimensional graphene structure can also enhance the tensile strength of the substrate, thereby improving the mechanical properties of the substrate.

[0034] In some embodiments, each stress buffer layer contains graphene. For example, each stress buffer layer can be made of graphene composite material, and the graphene content varies in each stress buffer layer. The graphene content decreases in stress buffer layers closer to the base layer 100, thus ensuring a higher coefficient of thermal expansion for stress buffer layers closer to the base layer 100. In other words, the coefficient of thermal expansion of each stress buffer layer can be easily and effectively controlled simply by adjusting the graphene content in different stress buffer layers, without the need for drilling.

[0035] Figure 1 In this structure, the stacked structure 200 is located only on the front side of the base layer 100. The stress buffer layer has four layers, including a stacked first stress buffer layer 201 and three second stress buffer layers. The first stress buffer layer 201 is closer to the base layer 100 than the second stress buffer layers, and the three second stress buffer layers are stacked sequentially on the first stress buffer layer 201. For ease of description, the three second stress buffer layers will be referred to as the first second stress buffer layer 202, the second second stress buffer layer 203, and the third second stress buffer layer 204. The first second stress buffer layer 202, the second second stress buffer layer 203, and the third second stress buffer layer 204 are stacked sequentially on the surface of the first stress buffer layer 201 facing away from the base layer 100.

[0036] Furthermore, the coefficient of thermal expansion of the first stress buffer layer 201 is greater than that of the first second stress buffer layer 202, the coefficient of thermal expansion of the first second stress buffer layer 202 is greater than that of the second second stress buffer layer 203, and the coefficient of thermal expansion of the second second stress buffer layer 203 is greater than that of the third second stress buffer layer 204.

[0037] Figure 2 This is a top view of a first stress buffer layer 201 provided in an embodiment of this application. Figure 3 This is a top view of the first and second stress buffer layers 202 provided in an embodiment of this application. Figure 4 This is a top view of the second stress buffer layer 203 provided in an embodiment of this application. Figure 5 This is a top view of the third, second stress buffer layer 204 provided in an embodiment of this application. (In conjunction with...) Figures 2-4 As can be seen, the first stress buffer layer 201 has multiple first through holes 200a, and the first second stress buffer layer 202, the second second stress buffer layer 203, and the third second stress buffer layer 204 each have multiple second through holes 200b. Furthermore, the diameter of each first through hole 200a is larger than the diameter of each second through hole 200b, and the porosity of the first stress buffer layer 201 is smaller than the porosity of the first second stress buffer layer 202. The diameter of the second through holes 200b in the first second stress buffer layer 202, the second second stress buffer layer 203, and the third second stress buffer layer 204 gradually decreases, while the porosity of the first second stress buffer layer 202, the second second stress buffer layer 203, and the third second stress buffer layer 204 gradually increases. Tests have shown that, under the same conditions, compared to conventional substrates, the deformation of the substrate in this application can be reduced from 1.2 mm / m to 0.5 mm / m, the thermal conductivity can be increased by 15% to 25%, and the high-temperature stability can be improved by 60%.

[0038] Furthermore, at least a portion of the second through holes 200b in two adjacent second stress buffer layers can be interconnected, and at least a portion of the first through holes 200a in the first stress buffer layer 201 can be interconnected with at least a portion of the second through holes 200b in the adjacent second stress buffer layer. This indirectly increases the porosity of each stress buffer layer, creating heat conduction channels between adjacent stress buffer layers, optimizing heat transfer paths, reducing temperature gradients, and improving the uniformity of surface temperature distribution on the substrate 100. Combined with far-infrared radiation effects, this accelerates heat dissipation through radiation and convection, significantly improving the heat dissipation efficiency of the substrate. For example, at least a portion of the second through holes 200b in the first second stress buffer layer 202 and the second second stress buffer layer 203 can be interconnected vertically, at least a portion of the second through holes 200b in the second second stress buffer layer 203 and the third second stress buffer layer 204 can be interconnected vertically, and at least a portion of the first through holes 200a in the first stress buffer layer 201 and at least a portion of the second through holes 200b in the first second stress buffer layer 202 can be interconnected vertically.

[0039] It should be noted that the two directly connected second through holes 200b or the directly connected first through hole 200a and second through hole 200b can be aligned (center lines coincide) or not aligned (center lines do not coincide), as long as they can be connected to better transfer heat.

[0040] In some embodiments, the first through hole 200a can be a hole of equal diameter (e.g., a cylindrical hole or a square hole) or a hole of variable diameter. For example, the diameter of the first through hole 200a can gradually increase along the direction close to the base layer 100. In this way, the coefficient of thermal expansion of the first stress buffer layer 201 is gradually changing, and the closer to the base layer 100, the greater the coefficient of thermal expansion of the first stress buffer layer 201 is. This allows the coefficient of thermal expansion of the first stress buffer layer 201 to gradually transition to match the coefficient of thermal expansion of the base layer 100, avoiding an excessive difference in the coefficient of thermal expansion between the first stress buffer layer 201 and the base layer 100, which would make it difficult to buffer stress.

[0041] It should be noted that when the first through hole 200a is a variable diameter hole, the minimum diameter of the first through hole 200a is greater than or equal to 20% of its maximum diameter. That is, the change rate of the diameter of the first through hole 200a is less than or equal to 20%, thereby avoiding affecting the stress absorption effect of the first stress buffer layer 201.

[0042] In some embodiments, a portion of the first through holes 200a in the first stress buffer layer 201 can be regular equal-diameter holes, while another portion of the first through holes 200a can be variable-diameter holes. Examples will not be given here.

[0043] In some embodiments, the second through hole 200b can be a hole of equal diameter (e.g., a cylindrical hole or a square hole) or a hole of variable diameter. For example, the diameter of the second through hole 200b can gradually increase along the direction close to the base layer 100. In this way, the coefficient of thermal expansion of the second stress buffer layer is gradually changing, and the closer to the base layer 100, the greater the coefficient of thermal expansion of the second stress buffer layer. This allows the coefficients of thermal expansion between adjacent second stress buffer layers and between the first stress buffer layer 201 and the first second stress buffer layer 202 to gradually transition to a matching ratio, avoiding excessive differences in the coefficients of thermal expansion between adjacent second stress buffer layers and between the first stress buffer layer 201 and the first second stress buffer layer 202, which would make it difficult to buffer stress.

[0044] It should be noted that when the second through hole 200b is a variable diameter hole, the minimum diameter of the second through hole 200b is greater than or equal to 20% of its maximum diameter. That is, the rate of change of the diameter of the second through hole 200b is less than or equal to 20%, thereby avoiding affecting the stress absorption effect of the second stress buffer layer.

[0045] In some embodiments, the second through holes 200b in a portion of the second stress buffer layer can be regular equal-diameter holes, while the second through holes 200b in another portion of the second stress buffer layer can be variable-diameter holes. Alternatively, a portion of the second through holes 200b in the same second stress buffer layer can be regular equal-diameter holes, while the other portion of the second through holes 200b can be variable-diameter holes. Examples will not be provided here.

[0046] In some embodiments, the base layer 100 is made of aluminum, in which case the coefficient of thermal expansion of the first stress buffer layer 201 can be 16 × 10⁻⁶. -6 / K~18×10 -6 / K, the coefficient of thermal expansion of the first and second stress buffer layers 202 can be 12×10. -6 / K~14×10 -6 / K, the coefficient of thermal expansion of the second stress buffer layer 203 can be 9×10. -6 / K~10×10 -6 / K, the coefficient of thermal expansion of the third layer, the second stress buffer layer 204, can be 7×10. -6 / K~8×10 -6 / K; however, this should not be the limitation, and the coefficients of thermal expansion of the first stress buffer layer 201 and each second stress buffer layer can also be designed according to actual needs.

[0047] In some embodiments, the pore size of the second through hole 200b in the first second stress buffer layer 202 can be 200nm to 500nm, and the porosity of the first second stress buffer layer 202 can be 10% to 20%; the pore size of the second through hole 200b in the second second stress buffer layer 203 can be 50nm to 200nm, and the porosity of the second second stress buffer layer 203 can be 20% to 30%; the pore size of the second through hole 200b in the third second stress buffer layer 204 can be 10nm to 50nm, and the porosity of the third second stress buffer layer 204 can be 30% to 50%; however, this should not be a limitation, and the pore size of the second through hole 200b in each second stress buffer layer and the porosity of each second stress buffer layer can be designed according to actual needs.

[0048] Figure 6 A cross-sectional schematic diagram of another substrate provided in an embodiment of this application, as shown below. Figure 6 As shown, in some embodiments, the first stress buffer layer 201 can be a non-porous structure. As long as the coefficient of thermal expansion of the first stress buffer layer 201 is greater than the coefficient of thermal expansion of the first and second stress buffer layers 202, the technical effect in this application can be achieved.

[0049] It should be noted that the second stress buffer layer in the stacked structure 200 is not limited to having three layers, but can also have one, two, four, or five layers, etc., which will not be listed here.

[0050] Furthermore, the stacked structure 200 is not limited to being located only on the front side of the base layer 100; in fact, the stacked structure 200 can also be located on the back side of the base layer 100. Figure 7 A cross-sectional schematic diagram of another substrate provided in an embodiment of this application, as shown below. Figure 7 As shown, the stacked structure 200 can also be located on the front and back sides of the base layer 100, thereby providing heat dissipation for the electronic components on the front and back sides of the base layer 100. It should be noted that if the stacked structure 200 is also located on the back side of the base layer 100, the rule that the coefficient of thermal expansion of the stress buffer layer closer to the base layer 100 is also required to be met.

[0051] Please continue reading. Figure 1The graphene layer 300 is located at least on the surface of the stacked structure 200 away from the base layer 100, thereby enabling rapid heat dissipation, improving the heat dissipation performance of the substrate, reducing the operating temperature of the devices on the board, and enhancing stability. Of course, if the stacked structure 200 is only located on the front side of the base layer 100, the graphene layer 300 can be located on the surface of the stacked structure 200 away from the substrate and on the back side of the base layer 100, thereby also promoting the dissipation of residual heat on the back side of the base layer 100; or, for example, if the stacked structure 200 is located on both the front and back sides of the base layer 100, the graphene layer 300 can be located on the surfaces of both stacked structures 200 away from the base layer 100.

[0052] Optionally, the thickness of the graphene layer 300 can be 0.5 μm to 2 μm, but should not be limited to this.

[0053] In summary, this embodiment provides a substrate including a base layer 100, a stacked structure 200, and a graphene layer 300. The base layer 100 has a front side and a back side disposed opposite to each other. The stacked structure 200 is located at least on the front side of the base layer 100, and the graphene layer 300 is located at least on the surface of the stacked structure 200 away from the substrate. The stacked structure 200 includes at least two stress buffer layers. The coefficient of thermal expansion of each stress buffer layer is between the coefficient of thermal expansion of the base layer 100 and the coefficient of thermal expansion of the graphene layer 300, and the coefficient of thermal expansion of the stress buffer layer closer to the base layer 100 is larger. On the one hand, the graphene layer 300 in this application can dissipate heat quickly, improve the heat dissipation performance of the substrate, reduce the operating temperature of the devices on the board, and improve stability. On the other hand, this application utilizes at least two stress buffer layers to form a transition region of thermal expansion coefficient between the graphene layer 300 and the base layer 100 (the thermal expansion coefficient in the direction from the graphene layer 300 to the base layer 100 increases from small to large), thereby reducing thermal stress concentration, reducing problems such as bonding layer breakage, interface peeling, or substrate cracking / deformation, and extending the life of the substrate. The stress buffer layer can also assist in heat dissipation, further improve the heat dissipation efficiency of the substrate, realize a substrate with high thermal conductivity suitable for high heat flow scenarios, and also support the evolution of electronic devices towards higher power, smaller size, and longer life.

[0054] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0055] It should also be noted that although preferred embodiments have been disclosed above, these embodiments are not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application, or modify them into equivalent embodiments, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application, without departing from the content of the technical solutions of this application, shall still fall within the scope of protection of the technical solutions of this application.

[0056] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0057] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and is not intended to limit the scope of this application. It must be noted that the singular forms “a” and “an” as used herein include plural bases unless the context clearly indicates the opposite. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood as having the definition of logical “or”, not logical “exclusive OR”, unless the context clearly indicates the opposite. Furthermore, implementations of the methods and / or devices in the embodiments of this application may include performing selected tasks manually, automatically, or in combination.

Claims

1. A substrate, characterized in that, The system includes a base layer (100), a stacked structure (200), and a graphene layer (300). The base layer (100) has a front side and a back side disposed opposite to each other. The stacked structure (200) is located at least on the front side of the base layer (100), and the graphene layer (300) is located at least on the surface of the stacked structure (200) opposite to the base layer (100). The stacked structure (200) includes at least two stress buffer layers, each of which has a thermal expansion coefficient between that of the base layer (100) and that of the graphene layer (300), with the thermal expansion coefficient of the stress buffer layer being greater the closer it is to the base layer (100).

2. The substrate according to claim 1, characterized in that, The stress buffer layer includes a stacked first stress buffer layer (201) and at least one second stress buffer layer, wherein the first stress buffer layer (201) is closer to the base layer (100) than the second stress buffer layer, the first stress buffer layer (201) is a non-porous structure, or the first stress buffer layer (201) has at least one first through hole (200a), and the second stress buffer layer has at least one second through hole (200b); The diameter of the first through hole (200a) is larger than the diameter of the second through hole (200b), the porosity of the first stress buffer layer (201) is smaller than the porosity of the second stress buffer layer, and the closer the second stress buffer layer is to the base layer (100), the larger the diameter of the second through hole (200b) and the smaller the porosity.

3. The substrate according to claim 2, characterized in that, At least a portion of the second through holes (200b) in two adjacent second stress buffer layers are in communication with each other; and / or, at least a portion of the first through holes (200a) in the first stress buffer layer (201) is in communication with at least a portion of the second through holes (200b) in the adjacent second stress buffer layer.

4. The substrate according to claim 2, characterized in that, The first through hole (200a) is a hole of constant diameter, or the diameter of the first through hole (200a) gradually increases along the direction close to the base layer (100), and the minimum diameter of the first through hole (200a) is greater than or equal to 20% of its maximum diameter; and, The second through hole (200b) is a hole of equal diameter, or the diameter of the second through hole (200b) gradually increases along the direction close to the base layer (100), and the minimum diameter of the second through hole (200b) is greater than or equal to 20% of its maximum diameter.

5. The substrate according to claim 2, characterized in that, The base layer (100) is made of aluminum. The second stress buffer layer has three layers, with the first to third layers of the second stress buffer layer stacked sequentially on the surface of the first stress buffer layer (201) away from the base layer (100). The coefficient of thermal expansion of the first stress buffer layer (201) is 16 × 10⁻⁶. -6 / K~18×10 -6 / K, the coefficients of thermal expansion of the first to third layers of the second stress buffer layer are 12×10. -6 / K~14×10 -6 / K、9×10 -6 / K~10×10 -6 / K and 7×10 -6 / K~8×10 -6 / K.

6. The substrate according to claim 2 or 5, characterized in that, The second stress buffer layer has three layers. The first to third layers of the second stress buffer layer are stacked sequentially on the surface of the first stress buffer layer (201) away from the base layer (100). The pore sizes of the first to third layers of the second stress buffer layer are 200nm~500nm, 50nm~200nm and 10nm~50nm, respectively, and the porosities are 10%~20%, 20%~30% and 30%~50%, respectively.

7. The substrate according to claim 1, characterized in that, The stacked structure (200) is located on the front side of the base layer (100), and the graphene layer (300) is also located on the back side of the base layer (100).

8. The substrate according to claim 1, characterized in that, The stacked structures (200) are located on the front and back sides of the base layer (100), and the graphene layers (300) are located on the surfaces of the two stacked structures (200) facing away from the base layer (100).

9. The substrate according to any one of claims 1, 7, or 8, characterized in that, The thickness of the graphene layer (300) is 0.5 μm to 2 μm.

10. The substrate according to claim 1, characterized in that, The substrate is a packaging substrate for LED chips.

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