Electronic chip

Abstract

The utility model relates to an electronic chip. There is provided a CSP type electronic chip with electromagnetic shielding, including: an insulating substrate having a resistivity higher than 1 k [Omega]. Cm and including a lower surface, a side surface, and an upper surface, an active portion of the electronic chip being formed on the substrate; an interconnection structure covering an upper surface of the substrate, the interconnection structure including an insulating layer in which a conductive track is formed, the connection pad being disposed on the interconnection structure, the conductive track being disposed to be exposed to at least one of one or more side surfaces of the interconnection structure; a resin covering the interconnect structure and leaving a portion of a channel to the connection pad; and a conductive coating covering and contacting the side surface and the lower surface of the substrate of the chip and the side surfaces of the interconnection structure to connect the conductive track to the conductive coating on at least one of the side surfaces of the interconnection structure.

Description

[0001] Cross-references to (one or more) related applications

[0002] This application claims priority to French patent application number 2404174, filed on April 23, 2024, entitled “Procédéde fabrication d'unepuceélectronique ayant un blindageélectromagnétique”, which is hereby incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This disclosure relates to the field of chips of CSP (“chip-scale package”) type or WLCSP (“wafer-scale package”). More particularly, it relates to a method for manufacturing an electronic chip with electromagnetic shielding. Background Technology

[0004] An electronic chip includes a substrate in which electronic circuitry has been fabricated, or on the substrate. The substrate is covered with interconnect areas to allow the chip to be assembled with, for example, a printed circuit board.

[0005] However, the chip may be subject to electromagnetic interference (EMI) that interferes with its operation or may even cause significant damage, and / or may generate such EMI.

[0006] To protect the chip from unwanted electromagnetic radiation, a molding is typically formed around the chip at the component level, and an electromagnetic shield is formed around the molding. Optionally, a second molding can be formed on the electromagnetic shield. Grounding of the electromagnetic shield can be achieved via vias and / or laminates, and can also be used to add antennas.

[0007] To manufacture electronic chips, low-temperature co-fired ceramics (LTCC) can be used. These LCCs comprise multiple dielectric layers, conductive material (e.g., screen-printed), and vias for interconnecting the different layers. The use of vias / through-holes facilitates the fabrication of shielding.

[0008] However, such chips include many interconnect layers and components, thus complicating manufacturing and / or increasing the size of the final chip. Utility Model Content

[0009] There is a need to improve, at least partially, certain aspects of known methods for manufacturing electronic chips, including those with electromagnetic shielding.

[0010] This objective is achieved by a method for manufacturing an electronic chip with electromagnetic shielding, the method comprising the following steps:

[0011] i) Provide an electronic chip, the electronic chip comprising:

[0012] - An insulating substrate, including a lower surface, side surfaces and a top surface;

[0013] - An interconnect structure covering the upper surface of a substrate, the interconnect structure including an insulating layer in which conductive tracks are formed, pads arranged on the interconnect structure, and the conductive tracks arranged to expose at least one side of the side surface of the interconnect structure.

[0014] - Resin, covering the upper surface of the interconnect structure and partially coating the connection pads to enable the connection pads to be connected to external components;

[0015] ii) A conductive coating is formed on the side and bottom surfaces of the substrate and on the side surfaces of the interconnect structure, whereby the conductive coating is connected to a conductive track on at least one side surface of the interconnect structure.

[0016] According to a specific embodiment, step ii) is performed by spraying a solution or inkjet printing.

[0017] According to specific embodiments, the solution or ink contains silver nanoparticles.

[0018] According to a specific embodiment, the electronic chip provided in step i) is obtained according to the following steps:

[0019] - A substrate covered by an interconnect structure is provided, with connection pads arranged on the interconnect structure and conductive tracks arranged to expose at least one side of the interconnect structure.

[0020] - Deposit resin on the interconnect structure and connection pads.

[0021] -Thin the resin to leave a channel to a portion of the bonding pads.

[0022] - If possible, thin the substrate and / or cover the back of the chip with an additional resin layer.

[0023] - Cut the substrate into different chips.

[0024] This objective is also achieved by an electronic chip, which includes:

[0025] - An insulating substrate, including a lower surface, side surfaces and a top surface;

[0026] - An interconnect structure covering the upper surface of a substrate, the interconnect structure including an insulating layer in which conductive tracks are formed, connection pads arranged on the interconnect structure, the conductive tracks being arranged to expose at least one side of the interconnect structure.

[0027] - Resin, covering the interconnect structure and leaving a channel to a portion of the connection pads;

[0028] - A conductive coating that covers and contacts the side and bottom surfaces of the chip's substrate and the sides of the interconnect structure to connect conductive tracks to at least one of the sides of the interconnect structure.

[0029] According to specific embodiments, the thickness of the conductive track ranges from 2 to 12 μm.

[0030] According to a specific embodiment, the width of the conductive track is greater than 10 μm.

[0031] According to a specific embodiment, the conductive coating is made of silver.

[0032] According to a specific embodiment, the conductive tracks exposed on the sides of the interconnect structure include comb-shaped ends.

[0033] According to a specific embodiment, conductive tracks are exposed on two opposite sides of the interconnect structure.

[0034] This objective is also achieved through the use of such electronic chips in the automotive sector, such as in advanced driver assistance systems, in personal electronics, and in communication equipment such as computers, cellular phones (“smartphones”), connected objects (IoT), or one of their peripherals.

[0035] This objective can also be achieved through automobiles, communication equipment (such as computers, cellular phones (“smartphones”), Internet of Things (IoT) or one of their peripherals) that include such electronic chips.

[0036] According to one aspect of this disclosure, a method for manufacturing a CSP-type electronic chip with electromagnetic shielding is provided, comprising:

[0037] i) Provides CSP-type electronic chips, which include:

[0038] - An insulating substrate having a resistivity higher than 1 kΩ·cm and including a lower surface, a side surface and a upper surface, wherein the active portion of the electronic chip is formed on the substrate;

[0039] - An interconnect structure covering the upper surface of the substrate, the interconnect structure including an insulating layer in which conductive tracks are formed, connection pads arranged on the interconnect structure, the conductive tracks being arranged to expose at least one side of one or more sides of the interconnect structure.

[0040] - Resin, covering the upper surface of the interconnect structure and partially coating the connection pads to enable connection of the connection pads to external components; and

[0041] ii) A conductive coating is formed on the side and bottom surfaces of the substrate and on the side surfaces of the interconnect structure, the conductive coating covering and contacting the side and bottom surfaces of the substrate of the electronic chip and the side surfaces of the interconnect structure, thereby connecting the conductive coating to a conductive track on at least one side surface of the interconnect structure.

[0042] According to embodiments of this disclosure, step ii) is performed by spraying a solution or inkjet printing.

[0043] According to embodiments of this disclosure, the solution or ink contains silver nanoparticles.

[0044] According to embodiments of this disclosure, the electronic chip provided at step i) is obtained according to the following steps:

[0045] - A substrate covered by an interconnect structure is provided, with connection pads arranged on the interconnect structure and conductive tracks arranged to expose at least one side of the interconnect structure.

[0046] - Deposit resin on the interconnect structure and connection pads;

[0047] - Thin the resin to leave a channel to a portion of the bonding pads; and

[0048] - The substrate is cut into different electronic chips.

[0049] According to embodiments of this disclosure, the electronic chip provided in step i) is obtained according to the following steps:

[0050] - A substrate covered by an interconnect structure is provided, with connection pads arranged on the interconnect structure and conductive tracks arranged to expose at least one side of the interconnect structure.

[0051] - Deposit resin on the interconnect structure and connection pads;

[0052] - Thin the resin to leave a channel to a portion of the bonding pad;

[0053] - Thinning the substrate or covering the lower surface of the electronic chip formed on the substrate with an additional resin layer; and

[0054] - The substrate is cut into different electronic chips.

[0055] According to another aspect of this disclosure, a CSP-type electronic chip with electromagnetic shielding is provided, comprising:

[0056] - An insulating substrate having a resistivity higher than 1 kΩ·cm and including a lower surface, a side surface and a top surface, on which the active portion of the electronic chip is formed;

[0057] - An interconnect structure covering the upper surface of the substrate, the interconnect structure including an insulating layer in which conductive tracks are formed, connection pads arranged on the interconnect structure, and the conductive tracks being arranged to expose at least one side of one or more sides of the interconnect structure.

[0058] - Resin, covering the interconnect structure and leaving a channel to a portion of the connection pads; and

[0059] - A conductive coating that covers and contacts the side and bottom surfaces of the substrate of the chip and the sides of the interconnect structure to connect conductive tracks to at least one of the sides of the interconnect structure.

[0060] According to embodiments of this disclosure, the thickness of the conductive track is in the range of 2 to 12 μm.

[0061] According to embodiments of this disclosure, the width of the conductive track is greater than 10 μm.

[0062] According to embodiments of this disclosure, the conductive coating is made of silver.

[0063] According to embodiments of this disclosure, the conductive tracks exposed on the sides of the interconnect structure have comb-shaped ends.

[0064] According to embodiments of this disclosure, conductive tracks are exposed on two opposite sides of the interconnect structure. Attached Figure Description

[0065] The foregoing features and advantages, as well as other features and advantages, will be described in detail below with reference to the accompanying drawings, which are given by way of illustration rather than limitation, in which:

[0066] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G , Figure 1H , Figure 1I and Figure 1J Cross-sectional views of different steps in a method for manufacturing an electromagnetically shielded electronic chip according to a specific embodiment are shown.

[0067] Figure 2 A cross-sectional view of an electronic chip with electromagnetic shielding according to another specific embodiment is shown;

[0068] Figure 3 A top view of an electronic chip with electromagnetic shielding according to another specific embodiment is shown. Detailed Implementation

[0069] In the figures, the same features are indicated by the same reference numerals. In particular, common structural and / or functional features in the various embodiments may have the same reference numerals and be deployed with the same structure, dimensions, and material properties.

[0070] For clarity, only detailed illustrations and descriptions are provided to aid in understanding the embodiments described herein.

[0071] Unless otherwise stated, when referring to two elements connected together, it means a direct connection without any intermediate elements other than conductors, and when referring to two elements coupled together, it means that the two elements can be connected or they can be coupled via one or more other elements.

[0072] In the following disclosure, unless otherwise stated, when referring to absolute positional qualifiers such as the terms “front,” “back,” “top,” “bottom,” “left,” “right,” etc., or relative positional qualifiers such as the terms “above,” “below,” “higher,” “lower,” etc., or directional qualifiers such as “horizontal,” “vertical,” etc., the direction shown in the figure is used.

[0073] Unless otherwise stated, the expressions “about,” “approximately,” “substantially,” and “approximately” indicate within 10%, preferably within 5%.

[0074] Now we will combine Figures 1A to 1J The method for manufacturing an electronic chip with electromagnetic shielding is described in further detail.

[0075] The method includes the following steps:

[0076] i) Provide electronic chip 100, including:

[0077] - Insulating substrate 12, which includes a lower surface 14, a side surface 15 and a upper surface 16;

[0078] - Interconnection structure 22, which covers the upper surface 16 of substrate 12, interconnection structure 22 includes an upper surface, a side surface and a lower surface in contact with substrate 12, interconnection structure 22 includes an insulating layer 24, in which conductive tracks 26 are formed, the conductive tracks being exposed on the upper surface to form a connection area on one side and on one side of the interconnection structure 22 on the other side.

[0079] - Connecting pad 30, which is bonded to connecting area 26;

[0080] - Resin 40, which covers the interconnect structure 22 and leaves a channel to a portion of the connection pads 30 so that they can be connected to external components;

[0081] ii) A conductive coating 50 is formed on the side surface 15 and the lower surface 16 of the substrate 12 of the chip 100 and on the side surface of the interconnect structure 22, whereby the conductive track 26 is connected to the conductive coating 50 on the side surface of the interconnect structure 22.

[0082] Using this method, the grounding of the electromagnetic coating 50 is performed directly at track 26 of the interconnect structure 22 of the chip 100. This not only frees up space because no further additional components are needed to couple the chip to the coating, but also leaves a path to the interconnect pads 30 for subsequent assembly of the chip to external components (e.g., chips or printed circuits).

[0083] The electromagnetic shielding (EMI) is connected to ground via an interconnect structure. The conductive tracks connected to the electromagnetic shielding are ground interconnects.

[0084] This method does not require covering the sides of the substrate 12 with a resin layer, nor does it require forming through holes in the substrate 12.

[0085] More specifically, the method may include the following steps:

[0086] a) Provides a structure including multiple chips 100, the structure including a substrate 12 covered by an interconnect structure 22, with connection pads 30 bonded to the interconnect structure 22. Figure 1A ),

[0087] b) Deposit resin 40 on interconnect structure 22 and connection pad 30, and thin resin 40 to leave a channel to a portion of connection pad 30. Figure 1B ),

[0088] c) Preferably, the substrate 12 is thinned. Figure 1C ) and / or cover the back side 16 of chip 100 with an additional resin layer,

[0089] d) Separate chip 100 by cutting the structure between the chips, thereby obtaining an individualized chip 100 as defined in step i). Figure 1D The cutting step can be performed by bonding the structure obtained in step c) to the first adhesive 201 (or carrier), preferably, the substrate 12 is bonded to the first adhesive 201 on its back side to perform the cutting step from the front.

[0090] e) Simultaneously, the diced chip 100 is bonded to the second adhesive 202, with the chip bonded in front of it, i.e., the resin 40 of the chip 100 and the bonding pads 30 are bonded to the second adhesive 202. Figure 1E ).

[0091] f) Remove the first adhesive 201 ( Figure 1F ),

[0092] g) If necessary, stretch the second adhesive 202 to leave more channels to the side surfaces of the substrate 12 and the sides of the interconnect structure 22 of the chip 100. Figure 1G ),

[0093] h) Implement step ii), that is, deposit an electromagnetic coating 50 on the side surface 15 and back surface 14 of the chip 100 and on the side surface of the interconnect structure 22. Figure 1H ).

[0094] The method may also include the following steps following step ii):

[0095] - On the back of chip 100, chip 100 is bonded to the third adhesive 203.

[0096] (Carrier), which is achieved by bonding coating 50 to third adhesive 203 ( Figure 1I ),

[0097] -Remove the third adhesive 203 ( Figure 1J ).

[0098] Preferably, the steps of the method are implemented to process all chips originating from the same substrate simultaneously.

[0099] At the end of the method, a chip 100 including an electromagnetic coating 50 is obtained. Figure 2 and Figure 3 ).

[0100] Each step in the different steps will now be described in further detail.

[0101] During step a), the active portion of chip 100 is formed on the same substrate 12 and has not yet been individualized.

[0102] During step a), one or more discrete components (not shown) may have been formed. These discrete components may be selected from, for example, transistors, diodes, thyristors, triac switching elements, filters, etc. Chip 100 may include one or more electronic circuits. Chip 100 enables the implementation of various electronic functions.

[0103] The chips can be the same or different.

[0104] Each electronic chip 100 includes:

[0105] -Insulating substrate 12,

[0106] - Interconnection structure 22 covering substrate 12,

[0107] - Connecting pads 30 arranged on interconnect structure 20.

[0108] According to an embodiment, at this stage of the process, substrate 12 corresponds to plate.

[0109] Substrate 12 is an insulating substrate (“high insulating substrate”). Its resistivity is, for example, higher than 1 kΩ·cm. For example, it is a resistive silicon substrate (HRSI, meaning “high resistivity silicon”) or a glass substrate. Any other high electrical insulating substrate or electrically insulating substrate can be used.

[0110] The thickness of the substrate 12 ranges from, for example, 100 to 900 μm, preferably from 300 to 900 μm, for example, approximately 725 μm.

[0111] The substrate 12 includes a first surface 16 (upper surface, front surface, or active surface) and a second surface 14 (lower surface or back surface). The two surfaces 14 and 16 are parallel to each other. They are coupled together through sidewalls 15. An insulating layer may cover the lower surface 14.

[0112] The interconnect structure 22 includes one or more (e.g., two or three) conductive rail levels 26 and an insulating layer 24.

[0113] The conductive track 26 is made of one or more materials selected from copper, copper alloys, titanium, titanium alloys, titanium nitride, gold, tungsten, platinum, and platinum alloys. The conductive track 26 may also be aluminum. According to embodiments, the thickness of each metal track 26 is in the range of 2 to 40 μm, for example, in the range of 2 to 12 μm. A thicker track increases the contact surface area between the track 26 and the electromagnetic coating 50. A thinner track 26 is easier to cut.

[0114] The insulating layer 24 can be a multilayer formed of multiple insulating layers. According to an embodiment, the thickness of each insulating layer 24 is in the range of 0.5 μm to 15 μm.

[0115] The insulating layer 24 can be made of a dielectric material, such as an oxide or nitride, preferably silicon dioxide (SiO2) or silicon nitride (e.g., Si3N4). Alternatively, the insulating layer can also be made of a polymer, particularly polyimide.

[0116] The interconnect structure 22 includes an upper surface, a lower surface, and a side surface. The lower surface is in contact with the upper surface 16 of the substrate 12.

[0117] The metal track 26 is flush with the upper surface to form a connection area. The connection area (also called an electrical contact) allows the electrical terminals of the chip 100 to be connected to other components (e.g., chips or printed circuits) by means of the connection pad 30.

[0118] The electrical connection region is also called "UBM" (Under-Bump Metallization). Preferably, at least two connection regions exist. For example, in... Figure 3 Six electrical connection regions are shown in the diagram.

[0119] For example, the distance between the electrical connection area and the sidewall of the chip ranges from 10 to 30 μm. This distance depends on the chip. It can be hundreds of micrometers or even a few millimeters, depending on the component being manufactured.

[0120] A portion of the metal track 26 may be accessed from the side of the interconnect region 22 to enable direct connection to the metal coating 50, thereby grounding the coating 50. The metal tracks may be accessed on at least one side of the chip 100. They may be accessible on multiple sides of the chip 100, for example, on two opposite sides.

[0121] The connection pad 30 is bonded to the connection area. The connection pad 30 is advantageously soldered to the electrical connection area. The connection pad 30 is formed of a conductive and wettable (i.e., solderable or weldable) material (i.e., a material on which soldering can be performed). For example, a metal pad is made of a tin-based solderable material (typically SnAgCu or Cu / SnAg).

[0122] During step b), resin layer 40 is deposited on the front surface of interconnect structure 22 and on connection pad 30.

[0123] Resin 40 is an electrically insulating resin. It can be a thermosetting or thermoplastic resin. The material should be selected as non-melting within the operating temperature range of the electronic component. The resin can be selected from the group consisting of: epoxy resins, phenolic resins, and acrylic resins.

[0124] The resin may also contain electrically insulating particles. These particles are, for example, oxide particles, and in particular, alumina or silica particles.

[0125] The resin layer 40 includes an upper surface, a lower surface that contacts the interconnect structure 22, and a side surface.

[0126] The resin 40 is thinned after it has been deposited to leave a channel to the top of the pad.

[0127] During step c), the substrate 12 may be thinned on its back side 14, and / or a resin layer 30 may be deposited on the back side of the substrate 12. For this purpose, the structure is flipped over and bonded from its front side to a first support 201. The first support 201 is, for example, an adhesive strip. The structure is then thinned on its back side, such that the substrate 12 has its final thickness.

[0128] Preferably, the side surface of the substrate 12 is not covered with resin.

[0129] During step d), substrate 110 is cut between chips 100 to cut single chips. For this purpose, a trench is formed that runs through the structure obtained in step c). The trench 120 defines the lateral profile of the chips 100.

[0130] The width of the groove 120 is, for example, in the range of 20 to 80 μm.

[0131] This cutting step can be performed using cutting or etching equipment. Cutting equipment can be, for example, mechanical cutting tools such as saws. Cutting can be done with a single blade or two blades.

[0132] It can also be laser cutting ("laser grooving" or "laser scribing") or plasma scribing. These different cutting processes can also be used together.

[0133] Trenching can also be formed through a laser dislocation dicing (stealth dicing) step followed by an expansion step. In the stealth dicing step, a specific laser is used to create dislocations in the dicing path within the substrate. These dislocations are defects in the substrate thickness, which, under mechanical stress, allow the chip to separate. Only the adhesive carrier is stretched to pull the chip apart and deposit material.

[0134] The first step can also be implemented by using a laser to cut the upper part of the device, which extends from the front to the bottom of the interconnect structure 22; then, the second step is implemented by using a saw to cut the substrate 12. Using a laser to cut the tracks (especially those made of copper) and insulating layers of the interconnect structure allows for clean cuts and avoids delamination.

[0135] The cutting step is preferably performed from the front. For this purpose, the structure obtained in step c) is bonded to the first adhesive 201 via its back side.

[0136] Once the substrate has been cut, the structure is flipped over to allow coating to be deposited from the back side. For this purpose, a second adhesive 202 is bonded to the front of the cut chip (step e). The second adhesive 202 is a stretchable adhesive.

[0137] Remove the first adhesive 201 (step f). Then, stretch the second adhesive 202 to increase the distance between the two chips 100 and make it easier to access the sides of the electronic chip (step g). This step is optional. It depends on the width of the cut made in step d) and / or the type of process used to deposit the shielding layer 50.

[0138] Alternatively, during step c), chip 100 can be bonded to a stretchable adhesive via its front end. The cutting step (step c) and the coating deposition step (step h) can then be performed on the same stretchable adhesive. There is no need to flip chip 100.

[0139] The various adhesives used in this process can be ultraviolet (UV) sensitive adhesives (“UV scribing tape”) used for cutting applications.

[0140] Then proceed with step ii).

[0141] The coating can be deposited in one step. In other words, it covers both the back and side surfaces of chip 100 simultaneously.

[0142] Preferably, coating 50 is deposited by liquid phase deposition. Electromagnetic coating 50 is deposited, for example, by solution spraying or inkjet printing. It can also be screen printed. The coating can also be deposited by evaporation or atomic layer deposition (ALD).

[0143] The solution or ink used contains conductive nanoparticles, typically metallic nanoparticles such as silver nanoparticles. Alternatively, the nanoparticles can be granules or microparticles.

[0144] Depending on the process used, the sidewalls 15 of the chip may be partially or completely covered by the coating. For example, the sidewalls of the resin layer 40 may or may not be covered by the coating 50.

[0145] At the end of the method, obtain such as Figure 2 and Figure 3 The chip 100 shown is an electronic chip 100 comprising:

[0146] - Insulating substrate 12, which includes a lower surface 14, a side surface 15 and a upper surface 16.

[0147] - Interconnect structure 22, which covers the upper surface 16 of the substrate, includes an upper surface, a side surface, and a lower surface in contact with the substrate 12. The interconnect structure includes an insulating layer 24, in which conductive tracks 26 are formed. The conductive tracks are exposed on one side of the upper surface of the interconnect structure to form a connection area, and on the other side of one of the side surfaces of the interconnect structure 22.

[0148] - Connecting pad 30, which is connected to the connection area.

[0149] - Resin 40, which covers the interconnect structure and leaves a channel to a portion of the connection pads.

[0150] - A conductive coating 50 covers and contacts the side surface 15 and lower surface 14 of the substrate of the chip 100 and the side surface of the interconnect structure 22 to connect the conductive track 26 to the conductive coating on the side surface of the interconnect structure 22.

[0151] The conductive coating is, for example, a metallic coating. It could be silver.

[0152] The conductive tracks 26 exposed on the sides of the interconnect structure 22 may include comb-shaped ends. Figure 3 Or it may have a solid shape, such as a strip.

[0153] The same chip 100 may include the same or different tracks. The conductive tracks 26 may be symmetrical or asymmetrical.

[0154] The goal is to maximize the contact surface area between the metal track 26 and the conductive coating 50 to ensure good electrical contact.

[0155] Preferably, different conductive tracks 26 are exposed on multiple sides of the interconnect structure 22. Preferably, the conductive tracks 26 are exposed on two opposite sides of the interconnect structure 22.

[0156] Track 26 is preferably made of copper or aluminum.

[0157] Each electronic chip 100 can then be coupled to an external component, such as another chip, package, printed circuit board, or another electronic chip.

[0158] This type of electronic chip can be applied in many industrial fields, especially in the automotive industry, in personal electronic products, particularly communication equipment, or in computers and peripherals.

[0159] For example, these could be 5G connected devices, or more generally, networked devices.

[0160] They can also be advanced driver assistance systems (ADAS).

[0161] Microchips can be used in smartphones or for the Internet of Things (IoT). Devices connect via, for example, 5G, Wi-Fi, or ultra-wideband (UWB).

[0162] This chip may also attract attention in other areas, such as industrial applications, especially green energy.

[0163] Such applications are provided for illustrative purposes only and are not restrictive.

[0164] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will occur to those skilled in the art.

[0165] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will occur to those skilled in the art.

Claims

1. A CSP-type electronic chip with electromagnetic shielding, characterized in that, include: - An insulating substrate having a resistivity higher than 1 kΩ·cm and including a lower surface, a side surface and a top surface, on which the active portion of the electronic chip is formed; - An interconnect structure covering the upper surface of the substrate, the interconnect structure including an insulating layer in which conductive tracks are formed, connection pads arranged on the interconnect structure, and the conductive tracks being arranged to expose at least one side of one or more sides of the interconnect structure. - Resin, covering the interconnect structure and leaving a channel to a portion of the connection pads; as well as - A conductive coating that covers and contacts the side and bottom surfaces of the substrate of the chip and the sides of the interconnect structure to connect conductive tracks to at least one of the sides of the interconnect structure.

2. The electronic chip as described in claim 1, characterized in that, The thickness of the conductive tracks ranges from 2 to 12 μm.

3. The electronic chip as described in claim 1, characterized in that, The width of the conductive track is greater than 10 μm.

4. The electronic chip as described in claim 1, characterized in that, The conductive coating is made of silver.

5. The electronic chip as described in claim 1, characterized in that, The conductive tracks exposed on the sides of the interconnect structure have comb-shaped ends.

6. The electronic chip as described in claim 1, characterized in that, The conductive tracks are exposed on two opposite sides of the interconnect structure.

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