Packaging structure for silicon optical chip evaluation

Abstract

The utility model relates to the technical field of chip packaging, in particular to a packaging structure for silicon optical chip evaluation, which comprises a circuit board and a chip carrier. The circuit board is provided with a hollow slot; the chip carrying platform is detachably connected with the circuit board, and the chip carrying platform is provided with a boss which is inserted into the hollow slot along the direction vertical to the circuit board; the boss is provided with a bearing face parallel to the circuit board, and a silicon optical chip electrically connected with the circuit board is attached to the bearing face. According to the embodiment of the invention, the adverse effect of the warping of the circuit board on the silicon optical chip can be eliminated, the circuit board can be repeatedly used, and the test cost is effectively reduced.

Description

Technical Field

[0001] This application relates to the field of chip packaging technology, and more specifically, to a packaging structure for evaluating silicon photonic chips. Background Technology

[0002] With the rapid development of silicon photonics chip technology, its application areas have expanded from traditional optical communication to multiple emerging fields such as quantum computing, 6G communication, LiDAR, biosensing, and optical interconnects, demonstrating broad market potential. As a core driving force in optical communication, data centers, and artificial intelligence, the rapid development of silicon photonics chips places higher demands on R&D and iteration efficiency. After chip tape-out, rapid and comprehensive evaluation of chip performance becomes crucial. To obtain detailed and accurate test data, specialized on-board package (COB) structures need to be designed for different chips to ensure accurate evaluation of chip performance indicators.

[0003] Traditional packaging structures directly mount chips onto circuit boards. However, circuit boards are prone to warping after reflow soldering. For silicon photonic chips that require micron-level precision optical coupling with fiber arrays, this warping severely affects the stability and accuracy of the coupling interface. Furthermore, rework is difficult. Given the inherent failure rate in the coupling process between silicon photonic chips and fiber arrays, integrated COB packaging makes repairs challenging in case of coupling failures. This often leads to the scrapping of the entire PCB and its components, increasing testing costs and reducing overall economic efficiency. Utility Model Content

[0004] The purpose of this application is to provide a packaging structure for evaluating silicon photonic chips, which can not only eliminate the adverse effects of circuit board warping on silicon photonic chips, but also allow the circuit board to be reused repeatedly, effectively reducing testing costs.

[0005] The embodiments of this application are implemented as follows:

[0006] This application provides a packaging structure for evaluating silicon photonics chips, including a circuit board and a chip carrier; the circuit board has a cutout slot; the chip carrier is detachably connected to the circuit board, and the chip carrier has a boss that is inserted into the cutout slot along a direction perpendicular to the circuit board; the boss has a bearing surface parallel to the circuit board, and a silicon photonics chip electrically connected to the circuit board is attached to the bearing surface.

[0007] As an optional implementation, the chip stage has a stage body; the stage body is located on the side of the circuit board away from the silicon photonic chip, and the stage body has a contact surface that fits against the circuit board; the stage body is provided with a connecting part, and the circuit board is provided with a locking member, the locking member being connected to the connecting part to make the contact surface abut against the circuit board.

[0008] As an optional implementation, the circuit board is provided with positioning holes; the platform body is provided with positioning structural members, which are inserted into the positioning holes along the direction perpendicular to the circuit board.

[0009] As an optional implementation, an electrical chip is attached to the bearing surface near the silicon photonic chip, and the electrical chip is electrically connected to both the circuit board and the silicon photonic chip.

[0010] As an optional implementation, the chip stage includes a metal heat dissipation structure for dissipating heat from the electrical chip and the silicon photonic chip.

[0011] As an optional implementation, the metal heat dissipation structure has a mounting groove on the side away from the circuit board, the mounting groove has a mounting surface close to the bearing surface, and a thermoelectric cooler is attached to the mounting surface; the projection of the thermoelectric cooler on the circuit board covers the projection of the bearing surface on the circuit board.

[0012] As an optional implementation, the bearing surface is attached with an optical fiber array near the silicon photonic chip; the silicon photonic chip has multiple waveguides on the side near the optical fiber array, and the multiple waveguides correspond one-to-one with the multiple light outlets of the optical fiber array.

[0013] As an optional implementation, the silicon photonic chip has a ceramic carrier on the side facing away from the bearing surface, and a temperature detection unit electrically connected to the circuit board is provided on the ceramic carrier.

[0014] As an optional implementation, a protective cover is also included, which is snapped onto the circuit board to form a receiving cavity, and the bearing surface is located within the receiving cavity.

[0015] As an optional implementation, the bearing surface is flush with the surface of the circuit board on the side closest to the silicon photonic chip.

[0016] The beneficial effects of the embodiments of this application include:

[0017] This solution employs a detachable chip stage structure. When the coupling between the silicon photonics chip and the fiber array fails, only the chip stage or the silicon photonics chip itself needs to be replaced. Therefore, this embodiment significantly reduces the difficulty of rework and allows for the reuse of circuit boards and peripheral components in production; it effectively controls testing costs and improves economic efficiency.

[0018] This application employs a detachable chip carrier structure, where the silicon photonics chip is not directly mounted on the circuit board. Therefore, the chip and circuit board no longer require a high-temperature reflow soldering process, which not only reduces optical coupling errors caused by circuit board deformation but also improves the accuracy of the coupling interface.

[0019] This application's embodiments, through the design of bosses and bearing surfaces, ensure that the silicon photonics chip is mounted on an independent and stable platform, unaffected by circuit board deformation. Therefore, this application's embodiments improve the alignment accuracy between the chip and the fiber array, enhance coupling efficiency and system stability, and are more suitable for high-precision optical testing environments. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is one of the structural schematic diagrams of the packaging structure in an embodiment of this application;

[0022] Figure 2 This is a second schematic diagram of the packaging structure according to an embodiment of this application;

[0023] Figure 3 This is the third schematic diagram of the packaging structure in the embodiments of this application;

[0024] Figure 4 This is the fourth schematic diagram of the packaging structure in the embodiments of this application;

[0025] Figure 5 This is the fifth schematic diagram of the packaging structure in the embodiments of this application;

[0026] Figure 6 This is the sixth schematic diagram of the packaging structure in the embodiments of this application;

[0027] Figure 7 This is the seventh schematic diagram of the packaging structure in the embodiments of this application;

[0028] Figure 8 This is the eighth schematic diagram of the packaging structure in the embodiments of this application;

[0029] Figure 9 This is the ninth schematic diagram of the packaging structure in an embodiment of this application.

[0030] icon:

[0031] 100-Circuit board; 101-Chip stage; 102-Silicon photonic chip; 103-Knockout slot; 104-Boss; 105-Bearing surface; 106-Stage body; 107-Contact surface; 108-Connecting part; 109-Locking part; 110-Positioning structure; 111-Electrical chip; 112-Metal heat dissipation structure; 113-Mounting slot; 114-Mounting surface; 115-Thermoelectric cooler; 116-Fiber optic array; 117-Waveguide; 118-Lead wire; 119-Temperature detection unit; 120-Protective cover. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0033] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0034] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0035] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0036] To obtain detailed and accurate test data, specialized on-board package (COB) structures are required for different chips to ensure accurate evaluation of chip performance indicators. Traditional packaging structures directly mount the chip onto the circuit board 100. However, the circuit board 100 is prone to warping after the reflow soldering process. For the silicon photonic chip 102, which requires micron-level precision optical coupling with the fiber array 116, this warping severely affects the stability and accuracy of the coupling interface. Furthermore, rework is difficult. Given the inherent failure rate in the coupling process between the silicon photonic chip 102 and the fiber array 116, integrated COB packaging makes repair difficult in case of coupling failure, often resulting in the scrapping of the entire PCB and its components. This increases testing costs and reduces overall economic efficiency.

[0037] To address the aforementioned technical problems, this application provides a packaging structure for evaluating silicon photonics chip 102.

[0038] Reference Figure 1 , Figure 2 , Figure 3 as well as Figure 4 As shown, this application embodiment provides a packaging structure for silicon photonics chip evaluation, including a circuit board 100 and a chip stage 101; the circuit board 100 has a hollow slot 103; the chip stage 101 is detachably connected to the circuit board 100, and the chip stage 101 has a boss 104 that is inserted into the hollow slot 103 along the direction perpendicular to the circuit board 100; the boss 104 has a bearing surface 105 parallel to the circuit board 100, and the silicon photonics chip 102 is attached to the bearing surface 105 and electrically connected to the circuit board 100.

[0039] It should be noted that, in this embodiment of the application, a hollow slot 103 is provided on the circuit board 100 to provide installation space for the boss 104 on the subsequently detachable chip carrier 101, so that the boss 104 on the chip carrier 101 can be vertically inserted into the hollow slot 103 of the circuit board 100. By providing a silicon photonic chip 102 on the boss 104, the assembly effect caused by the warping of the circuit board 100 can be eliminated.

[0040] It should be noted that the chip stage 101 is not directly soldered to the circuit board 100, but rather detachably connected via a mechanical structure, such as using clips or bolts to secure the chip stage 101 to the circuit board 100. In the event of coupling failure between the silicon photonic chip 102 and the fiber array 116, the chip stage 101 can be separated from the circuit board 100, allowing the circuit board 100 to be reused. This also facilitates the replacement, maintenance, and repair of the chip stage 101 and the silicon photonic chip 102 on it, significantly improving the flexibility and maintainability of the packaging structure.

[0041] It should be noted that a flat bearing surface 105 is provided on the top of the boss 104 to support the silicon photonic chip 102. This ensures that the silicon photonic chip 102 is parallel to the circuit board 100 when it is mounted, thus meeting the high-precision flatness requirements for the optical coupling of the silicon photonic chip 102 and the fiber array 116.

[0042] It should be noted that the silicon photonics chip 102 is mounted on the bearing surface 105 of the chip stage 101 and is electrically connected to the circuit board 100 via leads 118 or other means.

[0043] The embodiments of this application can produce the following effects:

[0044] Traditional integrated COB packaging typically requires the entire circuit board 100 and related components to be scrapped if coupling fails, resulting in high costs. This solution employs a detachable chip stage 101 structure. When coupling between the silicon photonics chip 102 and the fiber array 116 fails, only the chip stage 101 or the silicon photonics chip 102 itself needs to be replaced. Therefore, this embodiment significantly reduces the difficulty of rework and allows for the reuse of the circuit board 100 and peripheral components in production; effectively controlling testing costs and improving economic efficiency.

[0045] This embodiment employs a detachable chip stage 101 structure. The silicon photonics chip 102 is not directly mounted on the circuit board 100, but is separately mounted on the bearing surface 105 of the chip stage 101. Therefore, the chip and the circuit board 100 no longer need to undergo a high-temperature reflow soldering process, which not only reduces optical coupling errors caused by the deformation of the circuit board 100, but also improves the accuracy of the coupling interface.

[0046] Because the silicon photonics chip 102 needs to be optically coupled to the fiber array 116 at the micrometer level, the requirements for chip planarity and parallelism are extremely high. This embodiment of the application, through the design of the boss 104 and the bearing surface 105, ensures that the silicon photonics chip 102 is mounted on an independent and stable platform, unaffected by deformation of the circuit board 100. Therefore, this embodiment of the application improves the alignment accuracy between the chip and the fiber array 116, enhances coupling efficiency and system stability, and is more suitable for high-precision optical testing environments.

[0047] The embodiments of this application enable modular design, facilitating batch testing and standardized production. The chip platform 101, as a standardized module, can be independently manufactured, debugged, and replaced. Therefore, the embodiments of this application can support rapid replacement of different models of silicon photonic chips 102, improving testing efficiency and equipment utilization, and contributing to the formation of standardized testing processes and packaging platforms.

[0048] Reference Figure 2 , Figure 3As shown, in one optional implementation, the chip stage 101 has a stage body 106; the stage body 106 is located on the side of the circuit board 100 away from the silicon photonic chip 102, and the stage body 106 has a contact surface 107 that fits against the circuit board 100; the stage body 106 is provided with a connecting part 108, and the circuit board 100 is provided with a locking member 109, which is connected to the connecting part 108 so that the contact surface 107 abuts against the circuit board 100.

[0049] It should be noted that, in this embodiment, the stage body 106 is located on the side of the circuit board 100 away from the silicon photonic chip 102. That is, most of the volume of the chip stage 101 is actually located on the back side of the circuit board 100, and the stage body 106 has a contact surface 107 that fits against the circuit board 100. In this embodiment, the large contact surface 107 helps to evenly distribute pressure, reduce local stress concentration, thereby protecting the circuit board 100 from damage and improving the mechanical stability of the entire packaging structure.

[0050] Furthermore, refer to Figure 1 , Figure 2 as well as Figure 3 As shown, the platform body 106 of this application embodiment is provided with a connecting part 108, and the circuit board 100 is provided with a locking member 109. The locking member 109 is connected to the connecting part 108 so that the contact surface 107 abuts against the circuit board 100.

[0051] Preferably, the bearing surface 105 is flush with the surface of the circuit board 100 on the side closest to the silicon photonic chip 102.

[0052] The design of the connector 108 and the locking element 109 provides a simple and effective fixing method to ensure that the chip stage 101 is securely mounted on the circuit board 100. In this way, even when subjected to external vibration or impact, the chip stage 101 will not easily loosen, ensuring the long-term stability of the optical coupling between the silicon photonic chip 102 and the fiber array 116.

[0053] The locking element 109 can take various forms, such as screws or clips, depending on the actual application requirements and the need for convenience. For example, the platform body 106 has a threaded hole, and the locking element 109 is a bolt that passes through the circuit board 100. The connection between the bolt and the threaded hole enables a detachable connection between the circuit board 100 and the chip platform 101.

[0054] The technical effects that the embodiments of this application can produce are as follows:

[0055] The embodiments of this application can enhance mechanical stability. By setting a large-area contact surface 107 and using locking elements 109 for reinforcement, the mechanical strength of the packaging structure can be significantly improved, making it more resistant to the influence of the external environment, such as vibration and temperature changes.

[0056] The embodiments of this application can simplify the maintenance process. Due to the detachable design, when it is necessary to replace or repair the silicon photonic chip 102, the chip stage 101 can be easily removed by simply releasing the locking member 109, which greatly simplifies the maintenance process and reduces costs.

[0057] The embodiments of this application can guarantee optical coupling accuracy. Its stable physical connection helps to maintain precise alignment between the silicon photonic chip 102 and the fiber array 116, which is crucial for maintaining efficient optical coupling.

[0058] Reference Figure 3 As shown, in one optional implementation, the circuit board 100 is provided with positioning holes; the platform body 106 is provided with positioning structure 110, which is inserted into the positioning holes along the direction perpendicular to the circuit board 100.

[0059] It should be noted that the fiber optic array 116 can be mounted on the bearing surface 105 together with the silicon photonic chip 102, or it can be mounted on the circuit board 100 as needed. When the fiber optic array 116 is mounted on the circuit board 100, the embodiments of this application can achieve high-precision alignment through the cooperation of the positioning hole and the positioning structure 110, ensuring the accuracy of the position of the silicon photonic chip 102 on the boss 104, facilitating the electrical connection between the silicon photonic chip 102 and the circuit board 100, and achieving high-precision alignment between the silicon photonic chip 102 and the fiber optic array 116, thereby improving coupling efficiency.

[0060] The positioning structure 110 can be a cylindrical pin, a square pin, or a multi-point array positioning pin, etc., which can be selected by those skilled in the art as needed.

[0061] Furthermore, the positioning structure 110 solves the problem of large positional deviations after replacing the chip stage 101. Its plug-in mechanical positioning ensures high consistency even after multiple replacements. This not only improves the stability and reliability of electrical signal connections but also enhances the credibility and engineering applicability of test results.

[0062] Reference Figure 7 As shown, in an optional implementation, the bearing surface 105 is attached with an optical fiber array 116 near the silicon photonic chip 102; the silicon photonic chip 102 has multiple waveguides 117 on the side near the optical fiber array 116, and the multiple waveguides 117 correspond one-to-one with the multiple light outlet positions of the optical fiber array 116.

[0063] This embodiment of the application significantly improves optical coupling efficiency and reduces insertion loss by directly mounting the fiber array 116 onto the carrier surface 105 and ensuring precise alignment between the waveguide 117 and the output port of the fiber array 116. Furthermore, this compact design not only saves space but also improves the integration of the entire packaging structure, allowing more functions to be implemented in a smaller volume.

[0064] Reference Figure 3 , Figure 5 , Figure 6 as well as Figure 7 As shown, in one optional implementation, an electrical chip 111 is attached to the carrier surface 105 near the silicon photonic chip 102. The electrical chip 111 is electrically connected to both the circuit board 100 and the silicon photonic chip 102. The chip stage 101 includes a metal heat dissipation structure 112, which is used to dissipate heat from the electrical chip 111 and the silicon photonic chip 102.

[0065] It should be noted that in this embodiment, an electrical chip 111 is installed on the bearing surface 105 near the silicon photonic chip 102; that is, both the silicon photonic chip 102 and the electrical chip 111 are simultaneously disposed on the top surface of the boss 104. An electrical connection is established between the electrical chip 111 and the circuit board 100 and the silicon photonic chip 102 to ensure normal electrical signal transmission. (Refer to...) Figure 8 As shown, silicon photonics chip 102 and electrical chip 111 are electrically connected to circuit board 100 via lead wire 118, and silicon photonics chip 102 and electrical chip 111 are also connected via lead wire 118.

[0066] The chip stage 101 in this embodiment includes a metal heat dissipation structure 112. A dedicated metal heat dissipation structure 112, such as a heat sink or heat dissipation fin, is integrated into the chip stage 101 or its surface. The purpose of the metal heat dissipation structure 112 is to effectively conduct away the heat generated by the electrical chip 111 and the silicon photonics chip 102 during operation, preventing overheating from affecting performance or even damaging the chip.

[0067] It should be noted that the chip stage 101 is a one-piece molded metal structure, that is, the boss 104 and the stage body 106 are integrally molded. The chip stage 101 is a heat sink with high thermal conductivity.

[0068] The conventional approach is to directly mount the electrical chip 111 and the silicon photonics chip 102 onto the circuit board 100. This method limits the heat dissipation path and leads to localized overheating. The design of this embodiment, by directly placing the electrical chip 111 and the silicon photonics chip 102 on the protrusion 104 of the metal heat dissipation structure 112, can more efficiently transfer heat from the electrical chip 111 and the silicon photonics chip 102 to the external environment, reducing the temperature rise and thus maintaining the optimal operating temperature range.

[0069] The embodiments of this application, through effective heat dissipation measures, can reduce problems such as performance degradation and increased failure rate caused by overheating, thereby improving the long-term stability and reliability of the entire packaging structure.

[0070] In addition, since the electrical chip 111 and the silicon photonics chip 102 are concentrated on a separate chip carrier 101, the entire component is more modular, which makes it easy to quickly adjust the configuration or replace chips of different specifications according to different application requirements, and also simplifies the maintenance process.

[0071] Furthermore, in this embodiment of the application, the electrical chip 111 is arranged close to the silicon photonic chip 102, which can shorten the signal transmission distance, reduce signal delay and interference, and improve data processing speed and accuracy.

[0072] In summary, this implementation addresses the heat dissipation issues of the electrical chip 111 and the silicon photonics chip 102 by introducing a metal heat dissipation structure 112, while also optimizing the electrical connection layout. This not only solves the problem of poor heat dissipation in the prior art but also improves the overall performance of the packaging structure. This is of great significance for ensuring the high precision, stability, and repeatability required during the evaluation of the silicon photonics chip 102.

[0073] Reference Figure 5 , Figure 6 As shown, as an optional implementation, the metal heat dissipation structure 112 has a mounting groove 113 on the side away from the circuit board 100. The mounting groove 113 has a mounting surface 114 close to the bearing surface 105, and a thermoelectric cooler 115 is attached to the mounting surface 114. The projection of the thermoelectric cooler 115 on the circuit board 100 covers the projection of the bearing surface 105 on the circuit board 100.

[0074] The thermoelectric cooler 115 provides precise temperature regulation, which is especially important for the silicon photonic chip 102, which requires strict control of its operating temperature. It can maintain a stable low-temperature environment, preventing performance degradation or damage caused by temperature fluctuations.

[0075] It should be noted that the embodiments of this application combine the passive heat dissipation of the metal heat dissipation structure 112 with the active cooling of the thermoelectric cooler 115 to form a highly efficient composite heat dissipation system. Not only can some heat be dissipated through natural convection and radiation, but the forced cooling by the thermoelectric cooler 115 also significantly improves the overall heat dissipation efficiency.

[0076] The embodiments of this application can improve system reliability and lifespan. By effectively controlling the operating temperature, it reduces the probability of material aging and electrical performance degradation under high-temperature environments, extends the service life of the equipment, and improves operational reliability. Furthermore, the embodiments of this application can optimize testing conditions. For the evaluation of the silicon photonics chip 102, maintaining a constant and suitable operating temperature helps to obtain more accurate and consistent test data and reduces errors caused by temperature changes.

[0077] Reference Figure 8 As shown, as an optional implementation, the silicon photonic chip 102 is provided with a ceramic carrier on the side away from the bearing surface 105, and a temperature detection unit 119 electrically connected to the circuit board 100 is provided on the ceramic carrier.

[0078] Furthermore, in this embodiment of the application, the temperature of the silicon photonic chip 102 is detected by the temperature detection unit 119 so that the thermoelectric cooler 115 can provide precise temperature regulation.

[0079] Reference Figure 9 As shown, as an optional implementation, a protective cover 120 is also included, which is snapped onto the circuit board 100 to form a receiving cavity, and the bearing surface 105 is located inside the receiving cavity.

[0080] It should be noted that the protective cover 120 can be made of metal or high-strength plastic and is securely mounted on the circuit board 100 using adhesive layers, clips, screws, or other fasteners. The protective cover 120 effectively prevents external dust, moisture, and other contaminants from entering the package, protecting sensitive electronic components from damage. Furthermore, critical components such as the silicon photonics chip 102, the electrical chip 111, and the fiber optic array 116 are housed within this protected cavity, ensuring the safety and stability of these high-precision components.

[0081] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A packaging structure for evaluating silicon photonic chips, characterized in that, The device includes a circuit board (100) and a chip carrier (101); the circuit board (100) has a cutout slot (103); the chip carrier (101) is detachably connected to the circuit board (100), and the chip carrier (101) has a boss (104) inserted into the cutout slot (103) in a direction perpendicular to the circuit board (100); the boss (104) has a bearing surface (105) parallel to the circuit board (100), and a silicon photonic chip (102) electrically connected to the circuit board (100) is attached to the bearing surface (105).

2. The packaging structure for silicon photonics chip evaluation according to claim 1, characterized in that, The chip stage (101) has a stage body (106); the stage body (106) is located on the side of the circuit board (100) away from the silicon photonic chip (102), and the stage body (106) has a contact surface (107) that fits against the circuit board (100); the stage body (106) is provided with a connecting part (108), and the circuit board (100) is provided with a locking member (109), the locking member (109) is connected to the connecting part (108) so that the contact surface (107) abuts against the circuit board (100).

3. The packaging structure for silicon photonics chip evaluation according to claim 2, characterized in that, The circuit board (100) is provided with positioning holes; the platform body (106) is provided with positioning structure (110), and the positioning structure (110) is inserted into the positioning hole in a direction perpendicular to the circuit board (100).

4. The packaging structure for silicon photonics chip evaluation according to claim 1, characterized in that, The bearing surface (105) has an electrical chip (111) attached near the silicon photonic chip (102), and the electrical chip (111) is electrically connected to the circuit board (100) and the silicon photonic chip (102).

5. The packaging structure for silicon photonics chip evaluation according to claim 4, characterized in that, The chip stage (101) includes a metal heat dissipation structure (112) for dissipating heat from the electrical chip (111) and the silicon photonic chip (102).

6. The packaging structure for silicon photonics chip evaluation according to claim 5, characterized in that, The metal heat dissipation structure (112) has a mounting groove (113) on the side away from the circuit board (100). The mounting groove (113) has a mounting surface (114) close to the bearing surface (105). A thermoelectric cooler (115) is attached to the mounting surface (114). The projection of the thermoelectric cooler (115) on the circuit board (100) covers the projection of the bearing surface (105) on the circuit board (100).

7. The packaging structure for silicon photonics chip evaluation according to any one of claims 1-6, characterized in that, The bearing surface (105) is attached with an optical fiber array (116) near the silicon photonic chip (102); the silicon photonic chip (102) has multiple waveguides (117) on the side near the optical fiber array (116), and the multiple waveguides (117) correspond one-to-one with the multiple light outlets of the optical fiber array (116).

8. The packaging structure for silicon photonics chip evaluation according to any one of claims 1-6, characterized in that, The silicon photonic chip (102) has a ceramic carrier on the side away from the bearing surface (105), and a temperature detection unit (119) electrically connected to the circuit board (100) is provided on the ceramic carrier.

9. The packaging structure for silicon photonics chip evaluation according to any one of claims 1-6, characterized in that, It also includes a protective cover (120), which is fastened to the circuit board (100) to form a receiving cavity, and the bearing surface (105) is located inside the receiving cavity.

10. The packaging structure for silicon photonics chip evaluation according to any one of claims 1-6, characterized in that, The bearing surface (105) is flush with the surface of the circuit board (100) on the side closest to the silicon photonic chip (102).

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