Array storage device and storage equipment

Abstract

The utility model discloses an array storage device and storage equipment, and relates to the technical field of data storage. The array memory device includes: a substrate; the data interface is arranged on one side of the substrate; the main control unit is arranged on the substrate and is electrically connected with the data interface; the main control unit is arranged on the substrate, the plurality of data storage units are arranged on the substrate, and the plurality of data storage units are respectively and electrically connected with the main control unit; each data storage unit is used for storing at least one AI model; wherein the main control unit is used for receiving external data input by the data interface to the plurality of data storage units and / or outputting storage data of the plurality of data storage units to the data interface. The utility model aims to improve the calling stability and speed of different AI models arranged in a plurality of data storage units.

Description

Technical Field

[0001] This utility model relates to the field of data storage technology, and in particular to an array storage device and storage equipment. Background Technology

[0002] Redundant Array of Independent Disks (RAID) is a key technology in data storage, aiming to significantly improve the performance, reliability, and data redundancy of storage systems. However, in the storage of big data AI models, traditional RAID architectures often rely on numerous interfaces for disk-array connections, which can lead to loose connections and poor contact, jeopardizing stable data transmission and causing instability in AI model usage. Furthermore, the need for external data cables for disk-array connections results in slow switching speeds when switching between different AI models stored on multiple hard drives. Utility Model Content

[0003] The main objective of this invention is to provide an array storage device and storage equipment, which aims to improve the stability and speed of calling different AI models located in multiple data storage units.

[0004] To achieve the above objectives, the present invention proposes an array storage device, the array storage device comprising:

[0005] substrate;

[0006] A data interface is disposed on one side of the substrate;

[0007] A main control unit is disposed on the substrate and electrically connected to the data interface;

[0008] Multiple data storage units are disposed on the substrate and electrically connected to the main control unit respectively; each data storage unit is used to store at least one AI model.

[0009] The main control unit is used to receive external data input from the data interface to multiple data storage units and / or output stored data from multiple data storage units to the data interface.

[0010] In one embodiment, the data interface includes a gold finger.

[0011] In one embodiment, the master control unit includes a RAID chip.

[0012] In one embodiment, the data storage unit includes:

[0013] A data storage control circuit, which is electrically connected to the main control unit;

[0014] Multiple data storage circuits, each of which is electrically connected to the data storage control circuit;

[0015] The data storage control circuit is used to receive control signals output by the main control unit and control the data storage circuit to output or store corresponding data.

[0016] In one embodiment, the data storage control circuit includes a CXL chip.

[0017] In one embodiment, the data storage circuit includes:

[0018] A plurality of first storage circuits are provided, each of which is electrically connected to the data storage control circuit; the first storage circuits are used for persistent storage of data.

[0019] Multiple second storage circuits are provided, each electrically connected to the data storage control circuit; the second storage circuits are used to improve the data storage and output speed.

[0020] In one embodiment, the first storage circuit includes a NAND chip; the second storage circuit includes a DRAM chip.

[0021] The present invention also proposes a storage device, the storage device comprising at least one array storage device as described in any of the preceding claims.

[0022] This invention employs an array storage device, effectively improving the stability and speed of calling different AI models stored in multiple data storage units. The array storage device includes a substrate, a data interface, a main control unit, and multiple data storage units. The data interface is located on one side of the substrate to output data stored in the array storage device and input external data. Furthermore, the main control unit is also located on the substrate and electrically connected to the data interface to handle data transmission. Multiple data storage units are also respectively located on the substrate and electrically connected to the main control unit via substrate traces to achieve data storage and output. Each data storage unit stores at least one AI model. By electrically connecting multiple data storage units to the main control unit on the same substrate, the stability and speed of calling different AI models stored in multiple data storage units are effectively improved. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the module of the array storage device of this utility model;

[0025] Figure 2 This is a schematic diagram of a module of an embodiment of the array storage device of this utility model;

[0026] Figure 3 This is a schematic diagram of the structure of the array storage device of this utility model.

[0027] 10. Substrate; 20. Data interface; 30. Main control unit; 40. Data storage unit; 41. Data storage control circuit; 42. First storage circuit; 43. Second storage circuit.

[0028] The realization of the purpose, functional features and advantages of this utility model will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0029] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0030] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in this utility model embodiment are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0031] Furthermore, the use of terms such as "first" and "second" in this utility model is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this utility model.

[0032] Redundant Array of Independent Disks (RAID) is a key technology in data storage, aiming to significantly improve the performance, reliability, and data redundancy of storage systems. However, in the storage of big data AI models, traditional RAID architectures often rely on numerous interfaces for disk-array connections, which can lead to loose connections and poor contact, jeopardizing stable data transmission and causing instability in AI model usage. Furthermore, the need for external data cables for disk-array connections results in slow switching speeds when switching between different AI models stored on multiple hard drives.

[0033] Therefore, this utility model proposes an array storage device, the array storage device comprising:

[0034] substrate 10;

[0035] Data interface 20, wherein the data interface 20 is disposed on one side of the substrate 10;

[0036] A main control unit 30 is disposed on the substrate 10 and electrically connected to the data interface 20;

[0037] Multiple data storage units 40 are disposed on the substrate 10 and are electrically connected to the main control unit 30 respectively; each data storage unit 40 is used to store at least one AI model.

[0038] The main control unit 30 is used to receive external data input from the data interface 20 to the plurality of data storage units 40 and / or output the stored data of the plurality of data storage units 40 to the data interface 20.

[0039] In this embodiment, the substrate 10 can be made of glass fiber reinforced epoxy resin, metal substrate 10, ceramic substrate 10, etc. The size of the substrate 10 can be correspondingly set according to the data interface 20, the main control unit 30, and the multiple data storage units 40, so that the main control unit 30 and the multiple data storage units 40 are arranged on the surface of the substrate 10. Furthermore, to further reduce the volume of the array storage device, corresponding fixing structures can be provided on the substrate 10, such as corresponding bolt through holes or snap-fit ​​structures.

[0040] In this embodiment, the data interface 20 can be implemented using methods such as gold fingers, SATA, or fiber optic interfaces. By placing the data interface 20 on one side of the substrate 10, the array storage device can be easily and quickly connected to the corresponding device. The data interface 20 is electrically connected to the main control unit 30 via the substrate 10, thereby enabling fast and stable data transmission between the data interface 20 and the main control unit 30.

[0041] In this embodiment, the main control unit 30 can be implemented using a RAID controller, a storage area network controller, or the like. Taking a RAID controller as an example, the RAID controller manages the multiple data storage units 40 connected to it and performs RAID-related operations, such as striping, mirroring, and parity calculations, to achieve different RAID levels (e.g., RAID 0, RAID 1, RAID 5, RAID 6, etc.). Each level provides different levels of performance enhancement and / or data protection measures, thereby improving data storage performance and / or providing data redundancy. It is understood that the main control unit 30 is also electrically connected to the multiple data storage units 40 via traces on the substrate 10, thereby combining the multiple data storage units 40 into a single logical storage unit to improve the performance and reliability of the storage device.

[0042] In this embodiment, multiple data storage units 40 are disposed on the substrate 10 and electrically connected to the main control unit 30 via wiring to achieve data reception and transmission. Each data storage unit 40 stores at least one IA (Information Aspect Ratio) mode. It is understood that AI models may occupy different amounts of space due to their complexity. Therefore, different AI models may need to be stored in one data storage unit 40, multiple data storage units 40, or multiple different AI models stored in a single data storage unit 40. Furthermore, the size and performance of the multiple data storage units 40 can also be different, specifically set according to the memory size occupied by different AI models, so that each data storage unit 40 corresponds to a single AI model, facilitating data storage and retrieval.

[0043] It is understood that the main control unit 30 is electrically connected to the data interface 20 and multiple data storage units 40 respectively. The main control unit 30, the data interface 20 and the multiple data storage units 40 are all disposed on the substrate 10. The main control unit 30 is connected to the data interface 20 and the multiple data storage units 40 respectively through corresponding wiring methods. This enables the main control unit 30 to receive external data to the multiple data storage units 40 through the data interface 20, or to output the stored data in the array storage device to the data interface 20 through the data storage units 40, so as to realize the interaction of data pairs.

[0044] This application employs an array storage device to effectively improve the stability and speed of calling different AI models stored in multiple data storage units 40. The array storage device includes a substrate 10, a data interface 20, a main control unit 30, and multiple data storage units 40. The data interface 20 is located on one side of the substrate 10 to output data stored in the array storage device and input external data. Furthermore, the main control unit 30 is also located on the substrate 10 and electrically connected to the data interface 20 to process data transmission. The multiple data storage units 40 are also respectively located on the substrate 10 and electrically connected to the main control unit 30 via traces on the substrate 10 to achieve data storage and output. Each data storage unit 40 stores at least one AI model. By electrically connecting multiple data storage units 40 to the main control unit 30 on the same substrate 10, the stability and speed of calling different AI models stored in the multiple data storage units 40 are effectively improved.

[0045] In one embodiment of this utility model, the data interface 20 includes a gold finger.

[0046] Understandably, the reason data interface 20 uses gold fingers for data interaction is primarily because this method provides an efficient, stable, and reliable electrical connection. The gold fingers are plated with gold, which has extremely high conductivity and low resistivity. This ensures that electrical signals encounter almost no obstruction during transmission, guaranteeing high-speed and stable data transmission. Gold is not easily oxidized or corroded, meaning that even after prolonged use, the contact points of the gold fingers maintain good conductivity, ensuring reliable data transmission. Furthermore, due to the use of high-quality materials, the gold fingers can withstand multiple insertion and removal operations without damage, which is especially important in scenarios requiring frequent hardware replacement or upgrades. Secondly, the design of the gold fingers allows for a large number of signal transmission lines to be implemented in a small space, making it ideal for space-constrained applications in modern electronic devices. Finally, gold fingers are typically used with standardized slots or sockets, a design that simplifies the manufacturing process and facilitates hardware installation and maintenance for users.

[0047] In one embodiment of this utility model, the main control unit 30 includes a RAID chip.

[0048] In this embodiment, the main control unit 30 needs to effectively coordinate the stored data in each data storage unit 40 and quickly call the stored data in the corresponding AI model's data storage unit 40 upon receiving the corresponding instruction. Furthermore, the main control unit 30 also needs to obtain the corresponding external data through the data interface 20 and store it in the corresponding data storage unit 40 for subsequent retrieval. It is understood that multiple NAND flash memory chips exist in the multiple data storage units 40 to facilitate persistent data storage. Using a RAID chip can effectively distribute data across multiple NAND flash memory chips and, using parity checking or other redundancy techniques, data can still be recovered even if one or more NAND chips fail, thereby improving system reliability and data security. In addition, RAID can distribute data across multiple NAND chips for read and write operations through striping technology, enabling parallel data processing and significantly improving read / write speed and overall performance. Secondly, the RAID chip is responsible for managing and controlling the collaborative work of multiple NAND chips, including data distribution, error detection and correction, simplifying system complexity and making storage system management and maintenance more convenient. Finally, RAID supports multiple configuration modes (such as RAID 0, RAID 1, RAID 5, etc.), allowing you to choose the appropriate RAID level according to different needs to balance performance and redundancy.

[0049] In one embodiment of this utility model, the data storage unit 40 includes:

[0050] Data storage control circuit 41, which is electrically connected to the main control unit 30;

[0051] Multiple data storage circuits are provided, and each of the multiple data storage circuits is electrically connected to the data storage control circuit 41.

[0052] The data storage control circuit 41 is used to receive control signals output by the main control unit 30 and control the data storage circuit to output or store corresponding data.

[0053] In one embodiment, the data storage control circuit 41 can be implemented using a CXL chip, an FPGA, or a CPU and GPU supporting the CXL protocol. The data storage control circuit 41 effectively optimizes the interconnection performance between multiple data storage circuits in the data storage unit 40. Through electrical connection with the main control unit 30, it effectively integrates the stored data in the multiple data storage circuits within the data storage unit 40 and interacts with the main control unit 30, thereby enabling the output of stored data in the data storage circuits or the input of external data. Taking the CXL chip as an example, the CXL (Compute Express Link) chip effectively enhances the interconnection performance between computing, memory, and storage devices, and provides more efficient resource sharing capabilities. Specifically, the CXL chip is based on the PCIe (Peripheral Component Interconnect Express) physical layer but provides a lower latency and higher bandwidth interconnection method, enabling faster data exchange between the CPU and accelerators, memory, or other devices. Secondly, the CXL chip supports cache coherency, meaning that different devices connected through the CXL chip (such as CPUs and GPUs, FPGAs, or dedicated accelerators) can share memory space and maintain consistent access to these memory regions. This significantly simplifies the programming model and improves the efficiency of collaboration between multiple devices. Furthermore, the CXL chip defines three different device types (CXL.io, CXL.cache, and CXL.mem), allowing devices to select the most appropriate communication mode as needed. For example, CXL.cache allows devices to directly cache data from main memory, while CXL.mem allows devices to access resources on other devices as if they were accessing main memory. Finally, by using the CXL chip, array storage devices can more easily pool resources across multiple data storage circuits, allowing multiple hosts to share a large memory or storage pool, improving resource utilization and flexibility.

[0054] Understandably, to meet the requirements of persistent data storage and accelerate data read / write operations, multiple data storage circuits include multiple first storage circuits 42 and multiple second storage circuits 43. The multiple first storage circuits 42 are used for persistent data storage, while the multiple second storage circuits 43 are used to improve data storage and output speed. By electrically connecting the multiple first storage circuits 42 and the multiple second storage circuits 43 to the data storage control circuit 41 respectively, rapid data interaction is achieved. The first storage circuits 42 and the second storage circuits 43 can be implemented using NAND chips and DRAM chips, respectively. NAND flash memory is non-volatile, meaning that the data stored within it will not be lost even when power is off. It consists of multiple NAND cells, each capable of storing one or more bits of data. Depending on its structure and technology, NAND flash memory can be classified into types such as SLC (single-level cell), MLC (multi-level cell), TLC (triple-level cell), and QLC (quadruple-level cell), with different types offering different performance, reliability, and cost-effectiveness. To improve data read and write speeds, the data storage unit 40 typically includes a certain number of DRAM chips. These chips temporarily store a mapping table (a data structure that maps logical addresses to physical NAND addresses) and cache frequently accessed data, thereby increasing read and write speeds. It is understood that the number of the first storage circuit 42 and the second storage circuit 43, as well as the number of NAND chips and DRAM chips, can be configured according to actual needs.

[0055] This utility model also proposes a storage device, which includes at least one array storage device as described in any of the preceding claims. It is worth noting that since the storage device of this utility model is based on the aforementioned array storage device, the embodiments of the storage device of this utility model include all the technical solutions of all the embodiments of the aforementioned array storage device, and the achieved technical effects are exactly the same, and will not be repeated here.

[0056] The above description is merely an exemplary embodiment of the present utility model and does not limit the patent scope of the present utility model. Any equivalent structural transformations made based on the technical concept of the present utility model and the contents of the present utility model specification and drawings, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present utility model.

Claims

1. An array storage device, characterized in that, The array storage device includes: substrate; A data interface is disposed on one side of the substrate; A main control unit is disposed on the substrate and electrically connected to the data interface; Multiple data storage units are disposed on the substrate and electrically connected to the main control unit; each data storage unit is used to store at least one AI model. The main control unit is used to receive external data input from the data interface to multiple data storage units and / or output stored data from multiple data storage units to the data interface.

2. The array storage device as claimed in claim 1, characterized in that, The data interface includes a gold finger.

3. The array storage device as claimed in claim 1, characterized in that, The main control unit includes a RAID chip.

4. The array storage device as claimed in claim 1, characterized in that, The data storage unit includes: A data storage control circuit, which is electrically connected to the main control unit; Multiple data storage circuits, each of which is electrically connected to the data storage control circuit; The data storage control circuit is used to receive control signals output by the main control unit and control the data storage circuit to output or store corresponding data.

5. The array storage device as claimed in claim 4, characterized in that, The data storage control circuit includes a CXL chip.

6. The array storage device as claimed in claim 4, characterized in that, The data storage circuit includes: A plurality of first storage circuits are provided, each of which is electrically connected to the data storage control circuit; the first storage circuits are used for persistent storage of data. Multiple second storage circuits are provided, each electrically connected to the data storage control circuit; the second storage circuits are used to improve the data storage and output speed.

7. The array storage device as claimed in claim 6, characterized in that, The first storage circuit includes a NAND chip; the second storage circuit includes a DRAM chip.

8. A storage device, characterized in that, The storage device includes at least one array storage device as described in any one of claims 1 to 7.

Images