Wireless receiving system and low-noise amplification circuit thereof

Abstract

The utility model discloses a wireless receiving system and a low-noise amplification circuit thereof, which are applied to the technical field of communication, and comprise a first transformer, a common-gate amplification transistor, a common-source amplification transistor, a first resistor, a first amplification circuit, a second amplification circuit and a power synthesis output matching circuit, a primary coil and a secondary coil of the first transformer are respectively connected with a source electrode and a grid electrode of the common-gate amplification transistor to perform transconductance enhancement, and a drain electrode of the common-gate amplification transistor is connected with an input end of the first amplification circuit; the source electrode of the common-source amplification transistor is grounded, and the second end of the first resistor is connected with the drain electrode of the common-source amplification transistor and the input end of the second amplification circuit; the output end of the first amplification circuit and the output end of the second amplification circuit are connected with the first input end and the second output end of the power synthesis output matching circuit respectively. By applying the scheme of the invention, the low-noise amplifier with low noise coefficient and high gain can be effectively realized.

Description

Technical Field

[0001] This utility model relates to the field of communication technology, and in particular to a wireless receiving system and its low-noise amplifier circuit. Background Technology

[0002] In many communication scenarios, wireless receiving systems are required. The front end of a wireless receiving system is usually a low-noise amplifier, which can suppress noise while amplifying the signal. Its performance indicators such as bandwidth, gain, and noise figure directly affect the performance of the entire wireless receiving system.

[0003] Noise figure is the most important performance indicator for low-noise amplifiers (LNAs), and the overall noise figure of a wireless receiving system largely depends on the noise interference from the LNA. While some current dual-path noise-cancelling LNA architectures can achieve noise cancellation to a certain extent, traditional common-gate noise cancellation and common-source noise cancellation architectures typically use an auxiliary common-source amplifier to achieve noise cancellation. However, the auxiliary common-source amplifier itself introduces noise, making it difficult to perfectly cancel the noise voltage at the output of traditional dual-path noise-cancelling LNA architectures, especially in the millimeter-wave band where the impact of device parasitics on circuit performance is significant.

[0004] In summary, how to effectively achieve a low-noise amplifier with low noise figure and high gain is a technical problem that urgently needs to be solved by those skilled in the art. Utility Model Content

[0005] The purpose of this invention is to provide a wireless receiving system and its low-noise amplifier circuit, so as to effectively realize a low-noise amplifier with low noise figure and high gain.

[0006] To solve the above-mentioned technical problems, this utility model provides the following technical solution:

[0007] In a first aspect, the present invention provides a low-noise amplifier circuit, comprising: a first transformer, a common-gate amplifier transistor, a common-source amplifier transistor, a first resistor, a first amplifier circuit, a second amplifier circuit, and a power combining output matching circuit.

[0008] The first end of the primary coil of the first transformer is grounded, and the second end of the primary coil of the first transformer is connected to the source of the common gate amplifier transistor, the first end of the first resistor and the gate of the common source amplifier transistor, and the connection end serves as the input end of the low noise amplifier circuit.

[0009] The first end of the secondary coil of the first transformer is connected to the positive terminal of the first power supply, the second end of the secondary coil of the first transformer is connected to the gate of the common-gate amplifier transistor, and the drain of the common-gate amplifier transistor is connected to the input terminal of the first amplifier circuit.

[0010] The source of the common-source amplifier transistor is grounded, and the second end of the first resistor is connected to the drain of the common-source amplifier transistor and the input terminal of the second amplifier circuit, respectively.

[0011] The output terminals of the first amplifier circuit and the second amplifier circuit are respectively connected to the first input terminal and the second input terminal of the power combining output matching circuit, and the output terminal of the power combining output matching circuit serves as the output terminal of the low-noise amplifier circuit.

[0012] In one implementation, it further includes:

[0013] A first interstage matching circuit is connected in series between the common-gate amplifying transistor and the first amplifying circuit for performing interstage matching between the common-gate amplifying transistor and the first amplifying circuit.

[0014] A second interstage matching circuit is connected in series between the common-source amplifier transistor and the second amplifier circuit to perform interstage matching between the common-source amplifier transistor and the second amplifier circuit.

[0015] In one embodiment, the first inter-stage matching circuit includes a second transformer, and the second inter-stage matching circuit includes a third transformer;

[0016] The first end of the primary coil of the second transformer serves as the input terminal of the first stage inter-stage matching circuit and is connected to the drain of the common-gate amplifier transistor; the second end of the primary coil of the second transformer is connected to the positive terminal of the second power supply.

[0017] The first end of the secondary coil of the second transformer serves as the output terminal of the first interstage matching circuit and is connected to the input terminal of the first amplifier circuit. The second end of the secondary coil of the second transformer is connected to the positive terminal of the third power supply.

[0018] The first end of the primary coil of the third transformer serves as the input terminal of the second stage interstage matching circuit and is connected to the drain of the common-source amplifier transistor. The second end of the primary coil of the third transformer is connected to the positive terminal of the fourth power supply.

[0019] The first end of the secondary coil of the third transformer serves as the output terminal of the second interstage matching circuit and is connected to the input terminal of the second amplifier circuit. The second end of the secondary coil of the third transformer is connected to the positive terminal of the fifth power supply.

[0020] In one embodiment, it further includes: a first capacitor and a first inductor;

[0021] The first terminal of the first capacitor is connected to the second terminal of the primary coil of the first transformer and the source of the common-gate amplifier transistor, respectively. The second terminal of the first capacitor is connected to the first terminal of the first inductor, and the second terminal of the first inductor is connected to the first terminal of the first resistor and the gate of the common-source amplifier transistor, respectively.

[0022] In one embodiment, the first amplifier circuit includes: a first amplifier transistor, a second amplifier transistor, a second inductor, and a second capacitor;

[0023] The first end of the first amplifying transistor is connected to the first end of the second inductor, the second end of the second inductor is grounded, and the control end of the first amplifying transistor serves as the input end of the first amplifying circuit; the second end of the first amplifying transistor is connected to the first end of the second amplifying transistor, the control end of the second amplifying transistor is connected to the first end of the second capacitor, and the connection end is connected to the positive terminal of the sixth power supply; the second end of the second capacitor is grounded, and the second end of the second amplifying transistor serves as the output end of the first amplifying circuit.

[0024] In one embodiment, the second amplifier circuit includes: a third amplifier transistor, a fourth amplifier transistor, a third inductor, and a third capacitor;

[0025] The first end of the third amplifying transistor is connected to the first end of the third inductor, the second end of the third inductor is grounded, and the control end of the third amplifying transistor serves as the input end of the second amplifying circuit; the second end of the third amplifying transistor is connected to the first end of the fourth amplifying transistor, the control end of the fourth amplifying transistor is connected to the first end of the third capacitor and the connection end is connected to the positive terminal of the seventh power supply; the second end of the third capacitor is grounded, and the second end of the fourth amplifying transistor serves as the output end of the second amplifying circuit.

[0026] In one embodiment, the power combining output matching circuit includes a fourth transformer and a fifth transformer;

[0027] The first end of the primary coil of the fourth transformer serves as the first input terminal of the power combining output matching circuit; the second end of the primary coil of the fourth transformer is connected to the first end of the primary coil of the fifth transformer, and the connection terminal is connected to the positive terminal of the eighth power supply; the second end of the primary coil of the fifth transformer serves as the second input terminal of the power combining output matching circuit.

[0028] The second end of the secondary coil of the fifth transformer is grounded, and the first end of the secondary coil of the fifth transformer is connected to the second end of the secondary coil of the fourth transformer. The first end of the secondary coil of the fourth transformer serves as the output terminal of the power combining output matching circuit.

[0029] In one embodiment, the transmission line between the common-gate amplifier transistor and the first amplifier circuit is a first phase-adjustable transmission line; the transmission line between the common-source amplifier transistor and the second amplifier circuit is a second phase-adjustable transmission line.

[0030] In one embodiment, the first phase-adjustable transmission line includes: a first connecting line, a second connecting line, a third connecting line, a fourth connecting line, a fifth connecting line, a sixth connecting line, a first switched capacitor, a second switched capacitor, a third switched capacitor, a fourth switched capacitor, a fifth switched capacitor, and a sixth switched capacitor.

[0031] The first end of the first connecting line and the first end of the first switched capacitor are both connected to the first port of the first phase-adjustable transmission line, and the first port serves as the first end of the first phase-adjustable transmission line to connect to the common-gate amplifier transistor.

[0032] The second end of the first connecting line is connected to the first end of the sixth connecting line, and the first end of the fifth connecting line and the first end of the sixth switched capacitor are both connected to the second port of the first phase-adjustable transmission line. The second end of the fifth connecting line is connected to the second end of the sixth connecting line.

[0033] The second end of the third connecting line is connected to the midpoint of the sixth connecting line; the first end of the third connecting line is connected to the first end of the third switched capacitor and the first end of the fourth switched capacitor, respectively; the second end of the second connecting line is connected to the second end of the third switched capacitor and the first end of the second switched capacitor, respectively; the second end of the second switched capacitor is connected to the first end of the first connecting line; the second end of the fourth connecting line is connected to the second end of the fourth switched capacitor and the first end of the fifth switched capacitor, respectively; the second end of the fifth switched capacitor is connected to the first end of the fifth connecting line.

[0034] The first end of the second connecting line is connected to the second end of the first switched capacitor, and the connecting end is connected to the third port of the first phase-adjustable transmission line; the first end of the fourth connecting line is connected to the second end of the sixth switched capacitor, and the connecting end is connected to the third port of the first phase-adjustable transmission line, and the third port serves as the second end of the first phase-adjustable transmission line to connect to the first amplifier circuit.

[0035] Among them, the first switched capacitor, the second switched capacitor, the third switched capacitor, the fourth switched capacitor, the fifth switched capacitor and the sixth switched capacitor are all switched capacitors with adjustable on / off states.

[0036] Secondly, this utility model provides a wireless receiving system, including the low-noise amplifier circuit described above.

[0037] The technical solution provided by this utility model embodiment effectively realizes a low-noise amplifier circuit through dual-path noise cancellation. Specifically, path 1 includes a common-gate amplifier transistor and a first amplifier circuit, and path 2 includes a common-source amplifier transistor, a first resistor, and a second amplifier circuit. The common-gate amplifier transistor itself introduces noise, and as can be seen from the characteristics of the common-gate noise cancellation structure, the noise itself is out of phase and unequal at its drain and source. That is, the noise introduced by the common-gate amplifier transistor itself is out of phase and unequal at its drain and source. Simultaneously, the noise introduced by the common-gate amplifier transistor enters path 2 and is amplified in reverse phase by the common-source amplifier transistor. Therefore, for the noise introduced by the common-gate amplifier transistor, the noise signal caused by this noise at the drain of the common-gate amplifier transistor is in phase with the noise signal caused by this noise at the drain of the common-source amplifier transistor. Therefore, by setting appropriate amplification factors for the first and second amplifier circuits, the noise signal caused by the noise introduced by the common-gate transistor at the output of the first amplifier circuit and the noise signal caused by the noise at the output of the second amplifier circuit can be of equal magnitude and in phase. In other words, the noise introduced by the common-gate transistor, after passing through path 1 and path 2, is output with equal magnitude and in phase. By differentially superimposing path 1 and path 2 through a power combining output matching circuit, the noise introduced by the common-gate transistor can be eliminated. Common-source transistors also introduce noise. As can be seen from the characteristics of common-source noise cancellation structures, common-source transistors cause their own noise to be of unequal magnitude at their drain and source. At the same time, the noise introduced by the common-source transistor enters path 1 and is amplified in phase by the common-gate transistor. Therefore, the noise introduced by the common-source transistor is equal in magnitude and in phase after passing through path 1 and path 2. After differential superposition of path 1 and path 2 by the power combining output matching circuit, the noise introduced by the common-source transistor can be eliminated.

[0038] As can be seen, the proposed solution utilizes a common-gate noise cancellation architecture combined with a common-source noise cancellation architecture to effectively achieve a low-noise amplifier circuit through dual-path noise cancellation. Furthermore, unlike traditional solutions, it does not introduce an additional auxiliary common-source amplifier, thus avoiding the problem of additional noise introduced by the auxiliary common-source amplifier that is difficult to eliminate, as is common in traditional solutions. In addition, considering the low gain of the common-gate amplifier in the driver stage, a first transformer is provided to improve the gain. The connection relationship of the first transformer indicates that it can enhance transconductance to improve the gain.

[0039] In summary, the solution proposed in this application can effectively realize a low-noise amplifier with low noise figure and high gain. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 A schematic diagram of a low-noise amplifier circuit provided in a specific embodiment of this utility model;

[0042] Figure 2 A schematic diagram of a low-noise amplifier circuit provided for another specific embodiment of this utility model;

[0043] Figure 3 A schematic diagram of the structure of a low-noise amplifier circuit provided in another specific embodiment of this utility model;

[0044] Figure 4 This is a schematic diagram of the structure of a first phase adjustable transmission line provided in a specific embodiment of the present invention. Detailed Implementation

[0045] The core of this invention is to provide a wireless receiving system and its low-noise amplifier circuit, which can effectively realize a low-noise amplifier with low noise figure and high gain.

[0046] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0047] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a low-noise amplifier circuit provided in a specific embodiment of the present invention. The low-noise amplifier circuit includes: a first transformer, a common-gate amplifier transistor M1, a common-source amplifier transistor M2, a first resistor R1, a first amplifier circuit 10, a second amplifier circuit 20, and a power combining output matching circuit 30.

[0048] The first end of the primary coil of the first transformer is grounded, and the second end of the primary coil of the first transformer is connected to the source of the common gate amplifier transistor M1, the first end of the first resistor R1 and the gate of the common source amplifier transistor M2, and the connection end serves as the input end of the low noise amplifier circuit.

[0049] The first terminal of the secondary coil of the first transformer is connected to the positive terminal of the first power supply. Figure 1 The positive terminal of the first power supply is denoted as V. G The specific voltage of the positive terminal of the first power supply can be set according to actual needs. The second end of the secondary coil of the first transformer is connected to the gate of the common-gate amplifier transistor M1, and the drain of the common-gate amplifier transistor M1 is connected to the input terminal of the first amplifier circuit 10.

[0050] The source of the common-source amplifier transistor M2 is grounded, and the second end of the first resistor R1 is connected to the drain of the common-source amplifier transistor M2 and the input of the second amplifier circuit 20.

[0051] The output terminals of the first amplifier circuit 10 and the second amplifier circuit 20 are respectively connected to the first input terminal and the second input terminal of the power combining output matching circuit 30, and the output terminal of the power combining output matching circuit 30 serves as the output terminal of the low-noise amplifier circuit.

[0052] Specifically, the low-noise amplifier circuit is effectively achieved through dual-path noise cancellation in this application. For ease of description in the following text, the path containing the common-gate amplifier transistor M1 and the first amplifier circuit 10 is referred to as path 1, while the path containing the common-source amplifier transistor M2 and the second amplifier circuit 20 is referred to as path 2.

[0053] The signal transmission and amplification process will be explained first. In practical applications, the low-noise amplifier circuit of this application can be used in wireless receiving systems and other similar applications. The input terminal of the low-noise amplifier circuit typically receives radio frequency (RF) signals, and the following description will also use RF signals as an example. The input RF signal is amplified in phase by the common-gate transistor M1. That is, the RF signal at the drain of the common-gate transistor M1 is in phase with the RF signal at the source of the common-gate transistor M1, and its amplitude is increased. Conversely, the input RF signal is amplified in phase by the common-source transistor M2. That is, the RF signal at the drain of the common-source transistor M2 is out of phase with the RF signal at the source of the common-source transistor M2, and its amplitude is increased.

[0054] Since the amplification factors of both the common-source transistor M2 and the common-gate transistor M1 are limited, a first amplifier circuit 10 and a second amplifier circuit 20 are respectively provided in path 1 and path 2. The specific structures of the first amplifier circuit 10 and the second amplifier circuit 20 can be set and adjusted as needed, but generally a consistent structure is adopted. The RF signal output from the drain of the common-gate transistor M1 is further amplified by the first amplifier circuit 10, while the RF signal output from the drain of the common-source transistor M2 is further amplified by the second amplifier circuit 20. As can be seen from the previous description, the RF signal output from the drain of the common-gate transistor M1 is out of phase with the RF signal output from the drain of the common-source transistor M2. Therefore, by setting appropriate amplification factors for the first amplifier circuit 10 and the second amplifier circuit 20, the RF signal output by the first amplifier circuit 10 can be made to be equal in magnitude and out of phase with the RF signal output by the second amplifier circuit 20. Finally, the radio frequency signal output from the first amplifier circuit 10 and the radio frequency signal output from the second amplifier circuit 20 are both transmitted to the power combining output matching circuit 30, where they can be differentially superimposed to suppress common-mode interference. It can be seen that the low-noise amplifier circuit of this application effectively achieves signal transmission and amplification.

[0055] It should also be noted that the common-gate amplifier transistor M1 itself introduces noise. Furthermore, due to the characteristics of the common-gate noise cancellation structure, this noise is out of phase and unequal at its drain and source. In other words, the noise introduced by the common-gate amplifier transistor M1 is out of phase and unequal at its drain and source. Simultaneously, the noise introduced by the common-gate amplifier transistor M1 enters path 2 and is amplified in reverse phase by the common-source amplifier transistor M2. Therefore, regarding the noise introduced by the common-gate amplifier transistor M1, the noise signal caused by this noise at the drain of the common-gate amplifier transistor M1 is in phase with the noise signal caused by this noise at the drain of the common-source amplifier transistor M2. Therefore, by setting appropriate amplification factors for the first amplifier circuit 10 and the second amplifier circuit 20, the noise signal caused by the noise introduced by the common gate amplifier transistor M1 at the output of the first amplifier circuit 10 and the noise signal caused by the noise at the output of the second amplifier circuit 20 can be of equal magnitude and in phase. After differential superposition, the noise can be eliminated.

[0056] Similarly, and based on the characteristics of the common-source noise cancellation structure, the common-source amplifier transistor M2 causes its own noise to be of unequal magnitude at its drain and source. Simultaneously, the noise introduced by the common-source amplifier transistor M2 enters path 1 and is amplified in phase by the common-gate amplifier transistor M1. Therefore, for the noise introduced by the common-source amplifier transistor M2, the noise signal caused by this noise at the drain of the common-gate amplifier transistor M1 is in phase with the noise signal caused by this noise at the drain of the common-source amplifier transistor M2. Therefore, by setting appropriate amplification factors for the first amplifier circuit 10 and the second amplifier circuit 20, the noise signal caused by this noise at the output of the first amplifier circuit 10 and the noise signal caused by this noise at the output of the second amplifier circuit 20 can be made equal in magnitude and in phase. This noise is then eliminated through differential superposition.

[0057] Furthermore, considering the low gain of the common-gate amplifier in the driver stage, this application incorporates a first transformer to enhance the gain. The primary and secondary coils of this transformer are denoted as L1 and Lgg, respectively, which enhance transconductance to improve the gain of the common-gate amplifier. The principle of transconductance enhancement lies in creating a negative voltage gain between the gate and source of the transistor, thereby indirectly increasing the voltage applied between the gate and source, thus increasing the output current of the transistor, which is equivalent to increasing the transconductance and achieving a gain increase. It should also be noted that in practical applications, the k-value (primary-secondary coupling coefficient) of the transformer composed of L1 and Lgg should not be too large, otherwise it will affect the circuit stability to some extent. Furthermore, by appropriately setting the inductance values ​​of L1 and Lgg, input matching for the common-gate amplifier can be effectively achieved; that is, for path 1, no additional input matching circuit is required.

[0058] In one specific embodiment of this utility model, please refer to... Figure 2 The first amplifier circuit 10 may include: a first amplifier transistor M3, a second amplifier transistor M4, a second inductor Ls1, and a second capacitor C2.

[0059] The first end of the first amplifier transistor M3 is connected to the first end of the second inductor Ls1, and the second end of the second inductor Ls1 is grounded. The control terminal of the first amplifier transistor M3 serves as the input terminal of the first amplifier circuit 10. The second end of the first amplifier transistor M3 is connected to the first end of the second amplifier transistor M4, and the control terminal of the second amplifier transistor M4 is connected to the first end of the second capacitor C2, with the connection terminal connected to the positive terminal of the sixth power supply. The second end of the second capacitor C2 is grounded, and the second end of the second amplifier transistor M4 serves as the output terminal of the first amplifier circuit 10.

[0060] In this embodiment, the first amplifier circuit 10 has a simple structure and high reliability. By selecting the first amplifier transistor M3 and the second amplifier transistor M4, the required amplification factor can be achieved flexibly and conveniently. Figure 2 This implementation method was adopted in [the context of the text]. Figure 2 In the diagram, the positive terminal of the sixth power supply is denoted as Vgs2, and the specific voltage can be set according to actual needs.

[0061] In one specific embodiment of this utility model, the second amplifier circuit 20 includes: a third amplifier tube M5, a fourth amplifier tube M6, a third inductor Ls2, and a third capacitor C3.

[0062] The first end of the third amplifier transistor M5 is connected to the first end of the third inductor Ls2, the second end of the third inductor Ls2 is grounded, and the control terminal of the third amplifier transistor M5 serves as the input terminal of the second amplifier circuit 20; the second end of the third amplifier transistor M5 is connected to the first end of the fourth amplifier transistor M6, the control terminal of the fourth amplifier transistor M6 is connected to the first end of the third capacitor C3 and the connection terminal is connected to the positive terminal of the seventh power supply; the second end of the third capacitor C3 is grounded, and the second end of the fourth amplifier transistor M6 serves as the output terminal of the second amplifier circuit 20.

[0063] As described above, the first amplifier circuit 10 and the second amplifier circuit 20 can usually adopt the same structure. Figure 2 The implementation method employs this design, similar to the first amplifier circuit 10 described above. The second amplifier circuit 20 also adopts this simple and highly reliable circuit structure design. By selecting the third amplifier transistor M5 and the fourth amplifier transistor M6, the required amplification factor can be flexibly and conveniently achieved. Figure 2 In this context, the seventh power supply positive terminal is also denoted as Vgs2. The specific voltage can be set as needed, and it is usually the same as the voltage of the sixth power supply positive terminal.

[0064] Next, let's take... Figure 2 Taking this as an example, we will explain the transmission of signals and the elimination of noise.

[0065] The radio frequency signal input to the low-noise amplifier circuit is denoted as RF0. RF0 will enter path 1 and path 2 respectively. When RF0 enters path 1, it will be amplified in phase by the common-gate amplifier transistor M1 to obtain RF1. Figure 2 In this diagram, the drain position of the common-gate amplifier transistor M1 is denoted as X, and the source position as Y. This means that RF1 at position Y is in phase with RF0 at position X, and due to amplification, the amplitude of RF1 is higher than that of RF0. After RF0 enters path 2, it is inverted and amplified by the common-source amplifier transistor M2 to obtain RF2. Figure 2 In the diagram, the drain position of the common-source amplifier transistor M2 is denoted as Z. That is to say, RF2 at position Z is out of phase compared to RF0 at position X, and because it is amplified, the amplitude of RF2 is higher than that of RF0.

[0066] Therefore, it can be seen that RF2 and RF1 are out of phase, and if the amplification factors of the common-gate amplifier transistor M1 and the common-source amplifier transistor M2 are the same, then RF2 and RF1 are equal in magnitude and out of phase.

[0067] RF1 is further amplified by the first amplifier circuit 10 to obtain RF3, which is the output of the first amplifier circuit 10. RF2 is further amplified by the second amplifier circuit 20 to obtain RF4, which is the output of the second amplifier circuit 20. It should also be noted that for... Figure 2The first amplifier circuit 10 shown performs inverted amplification of the signal, meaning that RF3 and RF1 are inverted signals of unequal magnitude. Similarly, for... Figure 2 The second amplifier circuit 20 shown performs inverted amplification of the signal, meaning RF4 and RF2 are out-of-phase signals of unequal magnitude. Therefore, in Figure 2 In the example, RF3 and RF4 are out of phase. By reasonably setting the amplification factors of the first amplifier circuit 10 and the second amplifier circuit 20, so that the amplification factor of path 1 is the same as that of path 2, RF3 and RF4 can be made to be of equal magnitude and out of phase. Finally, the power combining output matching circuit 30 performs differential superposition of RF3 and RF4. Furthermore, as described above, if the amplification factors of the common-gate amplifier transistor M1 and the common-source amplifier transistor M2 are the same, then RF2 and RF1 are of equal magnitude and out of phase. Therefore, the amplification factors of the first amplifier circuit 10 and the second amplifier circuit 20 can be set to the same amplification factor, thus making RF3 and RF4 of equal magnitude and out of phase.

[0068] exist Figure 2 To facilitate viewing and understanding, waveform icons for RF0, RF1, RF2, RF3, and RF4 are shown in a simplified manner. The waveform icons also indicate the phase and amplitude of the signal at the corresponding position.

[0069] The common-gate amplifier transistor M1 itself introduces noise. Specifically, the noise introduced by the common-gate amplifier transistor M1 will generate noise voltages of unequal magnitude and inverse phase at its drain and source. Figure 2 In the diagram, the noise introduced by the common-gate amplifier transistor M1 is denoted as M10 at the source (point Y) and M11 at the drain (point X). Therefore, M11 and M10 are out of phase and unequal in magnitude. Figure 2 The waveform icons for M11 and M10 also show that M11 and M10 are out of phase and unequal in size.

[0070] The noise introduced by the common-gate amplifier transistor M1 will enter path 2, that is... Figure 2 M10 will enter path 2 and be inverted by the common-source transistor M2 to obtain M12. Therefore, M12 and M10 are inverted, while M12 and M11 are in phase. That is to say, for the noise introduced by the common-gate transistor M1, the noise signal M11 caused by the noise at the drain of the common-gate transistor M1 (point X) and the noise signal M12 caused by the noise at the drain of the common-source transistor M2 (point Z) are in phase (when the amplification factors of the common-gate transistor M1 and the common-source transistor M2 are the same, then M11 and M12 are equal in magnitude and in phase).

[0071] M11 and M12 are respectively fed into the first amplifier circuit 10 and the second amplifier circuit 20, thus obtaining the amplified M13 and M14 respectively. Figure 2 In this circuit, both the first amplifier circuit 10 and the second amplifier circuit 20 are inverting amplifier circuits. Therefore, M13 and M11 are inverted, and M14 and M12 are inverted. Thus, M13 and M14 are in phase. By setting appropriate amplification factors for the first amplifier circuit 10 and the second amplifier circuit 20, M13 and M14 can be made to be of equal magnitude and in phase. Finally, through differential superposition, the cancellation of M13 and M14 is achieved, thus eliminating the noise introduced by the common-gate amplifier transistor M1. Furthermore, it can be understood that if both the first amplifier circuit 10 and the second amplifier circuit 20 are in-phase amplifier circuits, then M13 and M14 will still be in phase. Through differential superposition, the cancellation of M13 and M14 can still be achieved. In other words, whether the first amplifier circuit 10 and the second amplifier circuit 20 are both inverting amplifier circuits or both are in-phase amplifier circuits, it does not affect the implementation of this invention.

[0072] Similarly, the common-source amplifier transistor M2 itself also introduces noise. Furthermore, based on the characteristics of the common-source amplifier transistor M2, the noise introduced by it will generate unequal noise voltages at its drain and gate. Figure 2 In the diagram, the noise introduced by the common-source amplifier transistor M2 is denoted as M20 at the gate and M21 at the drain (Z point). Therefore, M21 and M20 are in phase but of different magnitudes. Figure 2 The waveform icons for M21 and M20 can also be seen.

[0073] Meanwhile, the noise M20 introduced by the common-source amplifier transistor M2 enters path 1 and is amplified in phase by the common-gate amplifier transistor M1 to obtain M22. Therefore, M22 and M20 are in phase, and M22 and M21 are also in phase. In other words, for the noise introduced by the common-source amplifier transistor M2, the noise signal M22 caused by the noise at the drain of the common-gate amplifier transistor M1 (point X) and the noise signal M21 caused by the noise at the drain of the common-source amplifier transistor M2 (point Z) are in phase (when the amplification factors of the common-gate amplifier transistor M1 and the common-source amplifier transistor M2 are the same, then M21 and M22 are equal in magnitude and in phase).

[0074] M21 and M22 are respectively fed into the first amplifier circuit 10 and the second amplifier circuit 20, thus obtaining the amplified M23 and M24 respectively. Figure 2In this circuit, both the first amplifier circuit 10 and the second amplifier circuit 20 are inverting amplifier circuits. Therefore, M23 and M21 are inverted, and M24 and M22 are inverted, while M23 and M24 are in phase. By setting appropriate amplification factors for the first amplifier circuit 10 and the second amplifier circuit 20, M23 and M24 can be made to be of equal magnitude and in phase. Finally, through differential superposition, the elimination of M23 and M24 is achieved, which also eliminates the noise introduced by the common-source amplifier transistor M2. Furthermore, it can be understood that if both the first amplifier circuit 10 and the second amplifier circuit 20 are in-phase amplifier circuits, then M23 and M24 will still be in phase. Through differential superposition, the elimination of M23 and M24 can still be achieved. That is, whether the first amplifier circuit 10 and the second amplifier circuit 20 use inverting amplifier circuits or both use in-phase amplifier circuits, it does not affect the implementation of this utility model.

[0075] In one specific embodiment of this utility model, it may further include: a first capacitor C1 and a first inductor Lin;

[0076] The first terminal of the first capacitor C1 is connected to the second terminal of the primary coil of the first transformer and the source of the common-gate amplifier transistor M1, respectively. The second terminal of the first capacitor C1 is connected to the first terminal of the first inductor Lin, and the second terminal of the first inductor Lin is connected to the first terminal of the first resistor R1 and the gate of the common-source amplifier transistor M2, respectively.

[0077] In this embodiment, the input matching of common-source amplification can be effectively achieved through the first capacitor C1 and the first inductor Lin, resulting in a simple structure and high reliability. Figure 3 The input matching shown includes input matching for common-source amplification and input matching for common-gate amplification, and as described above, input matching for common-gate amplification can be achieved by the first transformer. Figure 3 The common-gate amplifier driving stage shown in the diagram may specifically include the common-gate amplifier transistor M1 and the first transformer in the driving stage. Figure 3 The common-source amplifier of the driving stage shown in the figure may specifically include the common-source amplifier transistor M2 and the first resistor R1 of the driving stage.

[0078] In one specific embodiment of this utility model, please refer to... Figure 3 It may also include:

[0079] A first interstage matching circuit 40 is connected in series between the common gate amplifier transistor M1 and the first amplifier circuit 10 to perform interstage matching between the common gate amplifier transistor M1 and the first amplifier circuit 10.

[0080] A second interstage matching circuit 50 is connected in series between the common-source amplifier transistor M2 and the second amplifier circuit 20 to perform interstage matching between the common-source amplifier transistor M2 and the second amplifier circuit 20.

[0081] In this implementation method, please refer to Figure 3 By setting the first-stage matching circuit 40 and the second-stage matching circuit 50, the signal transmission efficiency can be effectively improved, the energy loss can be reduced, and the signal quality can be improved. Specifically, the first-stage matching circuit 40 realizes the impedance matching between the common-gate amplifier transistor M1 and the first amplifier circuit 10, while the second-stage matching circuit 50 realizes the impedance matching between the common-source amplifier transistor M2 and the second amplifier circuit 20.

[0082] The specific structures of the first-stage matching circuit 40 and the second-stage matching circuit 50 can be set and adjusted according to actual needs, as long as they can effectively achieve impedance matching between stages. For example, in one specific embodiment of this utility model, please refer to... Figure 2 The first-stage inter-matching circuit 40 includes a second transformer, and the second-stage inter-matching circuit 50 includes a third transformer;

[0083] The first end of the primary coil of the second transformer serves as the input terminal of the first interstage matching circuit 40 and is connected to the drain of the common-gate amplifier transistor M1. The second end of the primary coil of the second transformer is connected to the positive terminal of the second power supply. The first end of the secondary coil of the second transformer serves as the output terminal of the first interstage matching circuit 40 and is connected to the input terminal of the first amplifier circuit 10. The second end of the secondary coil of the second transformer is connected to the positive terminal of the third power supply.

[0084] The first end of the primary coil of the third transformer serves as the input terminal of the second-stage interstage matching circuit 50 and is connected to the drain of the common-source amplifier transistor M2. The second end of the primary coil of the third transformer is connected to the positive terminal of the fourth power supply. The first end of the secondary coil of the third transformer serves as the output terminal of the second-stage interstage matching circuit 50 and is connected to the input terminal of the second amplifier circuit 20. The second end of the secondary coil of the third transformer is connected to the positive terminal of the fifth power supply.

[0085] Figure 2In this embodiment, the first-stage matching circuit 40 is composed of a second transformer, whose primary and secondary coils are denoted as L2 and L3, respectively. The positive terminals of the second and third power supplies are denoted as Vdd and Vgs1, respectively, and their specific values ​​can be set and adjusted according to actual needs. The second-stage matching circuit 50 is composed of a third transformer, whose primary and secondary coils are denoted as L4 and L5, respectively. The positive terminals of the fourth and fifth power supplies are denoted as Vdd and Vgs1, respectively, and their specific values ​​can be set and adjusted according to actual needs. It can be seen that in this embodiment, the first-stage matching circuit 40 and the second-stage matching circuit 50 are conveniently implemented using two transformers, resulting in a simple structure and high reliability. Furthermore, it can be understood that the second and third transformers in this embodiment serve as impedance matching devices, therefore signal amplification / attenuation is unnecessary, meaning that neither the second nor the third transformer affects the signal amplitude.

[0086] The power combining output matching circuit 30 can combine the signal from path 1 and the signal from path 2. Specifically, it can differentially superimpose the signal from path 1 and the signal from path 2, and can also play the role of output matching. There are many specific circuit implementation methods. For example, in one specific embodiment of this utility model, the power combining output matching circuit 30 includes a fourth transformer and a fifth transformer.

[0087] The first end of the primary coil of the fourth transformer serves as the first input terminal of the power combining output matching circuit 30. The second end of the primary coil of the fourth transformer is connected to the first end of the primary coil of the fifth transformer, and the connection terminal is connected to the positive terminal of the eighth power supply. The second end of the primary coil of the fifth transformer serves as the second input terminal of the power combining output matching circuit 30.

[0088] The second end of the secondary coil of the fifth transformer is grounded, and the first end of the secondary coil of the fifth transformer is connected to the second end of the secondary coil of the fourth transformer. The first end of the secondary coil of the fourth transformer serves as the output terminal of the power combining output matching circuit 30.

[0089] exist Figure 2 This implementation method was used in the example, which makes the structure of the power combining output matching circuit 30 simple and highly reliable. Figure 2 In this diagram, the primary and secondary coils of the fourth transformer are denoted as L6 and L8, respectively, and the primary and secondary coils of the fifth transformer are denoted as L7 and L9, respectively. The positive terminal of the eighth power supply is... Figure 2 The voltage is denoted as Vdd, and its specific value can be set according to actual needs. It's understandable that in practical applications, it's usually calculated according to... Figure 2The implementation method sets the voltage at the corresponding location; that is, the voltage set for locations with the same marking is usually the same. Furthermore... Figure 2 The input Vin and its equivalent resistance Rs are shown at the input terminal of the low-noise amplifier circuit, and the output Vout is shown at the output terminal of the low-noise amplifier circuit.

[0090] In one specific embodiment of this utility model, the transmission line between the common-gate amplifier transistor M1 and the first amplifier circuit 10 is a first phase-adjustable transmission line 60; the transmission line between the common-source amplifier transistor M2 and the second amplifier circuit 20 is a second phase-adjustable transmission line 70.

[0091] This implementation takes into account that, due to process deviations, simulation model errors, etc., the amplitude and phase consistency of the signals in path 1 and path 2 may deteriorate, resulting in poor noise cancellation and reduced signal quality. Therefore, phase-adjustable transmission line structures are added to path 1 and path 2 respectively. For details, please refer to [link to relevant documentation]. Figure 3 The transmission line between the common-gate amplifier transistor M1 and the first amplifier circuit 10 uses a first phase-adjustable transmission line 60, while the transmission line between the common-source amplifier transistor M2 and the second amplifier circuit 20 uses a second phase-adjustable transmission line 70.

[0092] The first phase-adjustable transmission line 60 and the second phase-adjustable transmission line 70 can respectively achieve phase fine-tuning of the signal of path 1 and the signal of path 2, thereby correcting the performance degradation caused by factors such as process and simulation.

[0093] The specific structures of the first phase adjustable transmission line 60 and the second phase adjustable transmission line 70 can be set and adjusted as needed. Their structural principles can be the same or different. Of course, in practical applications, for ease of design, they usually adopt the same structural principle.

[0094] For example, in one specific embodiment of this utility model, see [reference needed]. Figure 4 The first phase-adjustable transmission line 60 includes: a first connecting line R41, a second connecting line R42, a third connecting line R43, a fourth connecting line R44, a fifth connecting line R45, a sixth connecting line R46, a first switched capacitor C41, a second switched capacitor C42, a third switched capacitor C43, a fourth switched capacitor C44, a fifth switched capacitor C45, and a sixth switched capacitor C46. The second phase-adjustable transmission line 70 can also use... Figure 4 The structure is as follows. In this embodiment, the first port and the third port are respectively used as the first end and the second end of the first phase adjustable transmission line 60. In other embodiments, the second port and the third port can also be selected as the first end and the second end of the first phase adjustable transmission line 60.

[0095] In this embodiment, the first end of the first connecting line R41 and the first end of the first switched capacitor C41 are both connected to the first port of the first phase adjustable transmission line 60, and the first port serves as the first end of the first phase adjustable transmission line 60 to connect to the common gate amplifier transistor M1.

[0096] The second end of the first connecting line R41 is connected to the first end of the sixth connecting line R46. The first end of the fifth connecting line R45 and the first end of the sixth switched capacitor C46 are both connected to the second port of the first phase adjustable transmission line 60. The second end of the fifth connecting line R45 is connected to the second end of the sixth connecting line R46.

[0097] The second end of the third connecting line R43 is connected to the midpoint of the sixth connecting line R46. The first end of the third connecting line R43 is connected to the first end of the third switched capacitor C43 and the first end of the fourth switched capacitor C44. The second end of the second connecting line R42 is connected to the second end of the third switched capacitor C43 and the first end of the second switched capacitor C42. The second end of the second switched capacitor C42 is connected to the first end of the first connecting line R41. The second end of the fourth connecting line R44 is connected to the second end of the fourth switched capacitor C44 and the first end of the fifth switched capacitor C45. The second end of the fifth switched capacitor C45 is connected to the first end of the fifth connecting line R45.

[0098] The first end of the second connecting line R42 is connected to the second end of the first switched capacitor C41, and the connecting end is connected to the third port of the first phase-adjustable transmission line 60; the first end of the fourth connecting line R44 is connected to the second end of the sixth switched capacitor C46, ​​and the connecting end is connected to the third port of the first phase-adjustable transmission line 60, and the third port serves as the second end of the first phase-adjustable transmission line 60 to connect to the first amplifier circuit 10.

[0099] Among them, the first switched capacitor C41, the second switched capacitor C42, the third switched capacitor C43, the fourth switched capacitor C44, the fifth switched capacitor C45, and the sixth switched capacitor C46 are all switched capacitors with adjustable on / off states.

[0100] In this embodiment, the phase-shifting characteristics of the first phase-adjustable transmission line 60 can be determined by adjusting the on / off states of each switched capacitor, effectively achieving fine-tuning of the phase. It can be understood that during phase shifting, the phase accuracy depends on the capacitance values ​​of each switched capacitor in its on and off states. Furthermore, this embodiment uses six switched capacitors, and through effective combination, the first phase-adjustable transmission line 60 can have a large number of phase-shifting positions, which helps ensure flexibility in practical applications.

[0101] The technical solution provided by this utility model embodiment effectively realizes a low-noise amplifier circuit through dual-path noise cancellation. Specifically, path 1 includes a common-gate amplifier transistor and a first amplifier circuit, and path 2 includes a common-source amplifier transistor, a first resistor, and a second amplifier circuit. The common-gate amplifier transistor itself introduces noise, and as can be seen from the characteristics of the common-gate noise cancellation structure, the noise itself is out of phase and unequal at its drain and source. That is, the noise introduced by the common-gate amplifier transistor itself is out of phase and unequal at its drain and source. Simultaneously, the noise introduced by the common-gate amplifier transistor enters path 2 and is amplified in reverse phase by the common-source amplifier transistor. Therefore, for the noise introduced by the common-gate amplifier transistor, the noise signal caused by this noise at the drain of the common-gate amplifier transistor is in phase with the noise signal caused by this noise at the drain of the common-source amplifier transistor. Therefore, by setting appropriate amplification factors for the first and second amplifier circuits, the noise signal caused by the noise introduced by the common-gate transistor at the output of the first amplifier circuit and the noise signal caused by the noise at the output of the second amplifier circuit can be of equal magnitude and in phase. In other words, the noise introduced by the common-gate transistor, after passing through path 1 and path 2, is output with equal magnitude and in phase. By differentially superimposing path 1 and path 2 through a power combining output matching circuit, the noise introduced by the common-gate transistor can be eliminated. Common-source transistors also introduce noise. As can be seen from the characteristics of common-source noise cancellation structures, common-source transistors cause their own noise to be of unequal magnitude at their drain and source. At the same time, the noise introduced by the common-source transistor enters path 1 and is amplified in phase by the common-gate transistor. Therefore, the noise introduced by the common-source transistor is equal in magnitude and in phase after passing through path 1 and path 2. After differential superposition of path 1 and path 2 by the power combining output matching circuit, the noise introduced by the common-source transistor can be eliminated.

[0102] As can be seen, the proposed solution utilizes a common-gate noise cancellation architecture combined with a common-source noise cancellation architecture to effectively achieve a low-noise amplifier circuit through dual-path noise cancellation. Furthermore, unlike traditional solutions, it does not introduce an additional auxiliary common-source amplifier, thus avoiding the problem of additional noise introduced by the auxiliary common-source amplifier that is difficult to eliminate, as is common in traditional solutions. In addition, considering the low gain of the common-gate amplifier in the driver stage, a first transformer is provided to improve the gain. The connection relationship of the first transformer indicates that it can enhance transconductance to improve the gain.

[0103] In summary, the solution proposed in this application can effectively realize a low-noise amplifier with low noise figure and high gain.

[0104] Corresponding to the embodiments of the low-noise amplifier circuit above, this utility model embodiment also provides a wireless receiving system, which may include the low-noise amplifier circuit as in any of the above embodiments, and can be referred to in correspondence with the above.

[0105] It should also be noted that, in this application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, article, or apparatus that includes said element.

[0106] This application uses specific examples to illustrate the principles and implementation methods of this utility model. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solution and core ideas of this utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made to this utility model without departing from the principles of this utility model, and these improvements and modifications also fall within the protection scope of this utility model.

Claims

1. A low-noise amplifier circuit, characterized in that, include: The system includes a first transformer, a common-gate amplifier transistor, a common-source amplifier transistor, a first resistor, a first amplifier circuit, a second amplifier circuit, and a power combining output matching circuit. The first end of the primary coil of the first transformer is grounded, and the second end of the primary coil of the first transformer is connected to the source of the common gate amplifier transistor, the first end of the first resistor and the gate of the common source amplifier transistor, and the connection end serves as the input end of the low noise amplifier circuit. The first end of the secondary coil of the first transformer is connected to the positive terminal of the first power supply, the second end of the secondary coil of the first transformer is connected to the gate of the common-gate amplifier transistor, and the drain of the common-gate amplifier transistor is connected to the input terminal of the first amplifier circuit. The source of the common-source amplifier transistor is grounded, and the second end of the first resistor is connected to the drain of the common-source amplifier transistor and the input terminal of the second amplifier circuit, respectively. The output terminals of the first amplifier circuit and the second amplifier circuit are respectively connected to the first input terminal and the second input terminal of the power combining output matching circuit, and the output terminal of the power combining output matching circuit serves as the output terminal of the low-noise amplifier circuit.

2. The low-noise amplifier circuit according to claim 1, characterized in that, Also includes: A first interstage matching circuit is connected in series between the common-gate amplifying transistor and the first amplifying circuit for performing interstage matching between the common-gate amplifying transistor and the first amplifying circuit. A second interstage matching circuit is connected in series between the common-source amplifier transistor and the second amplifier circuit to perform interstage matching between the common-source amplifier transistor and the second amplifier circuit.

3. The low-noise amplifier circuit according to claim 2, characterized in that, The first interstage matching circuit includes a second transformer, and the second interstage matching circuit includes a third transformer; The first end of the primary coil of the second transformer serves as the input terminal of the first stage inter-stage matching circuit and is connected to the drain of the common-gate amplifier transistor; the second end of the primary coil of the second transformer is connected to the positive terminal of the second power supply. The first end of the secondary coil of the second transformer serves as the output terminal of the first interstage matching circuit and is connected to the input terminal of the first amplifier circuit. The second end of the secondary coil of the second transformer is connected to the positive terminal of the third power supply. The first end of the primary coil of the third transformer serves as the input terminal of the second stage interstage matching circuit and is connected to the drain of the common-source amplifier transistor. The second end of the primary coil of the third transformer is connected to the positive terminal of the fourth power supply. The first end of the secondary coil of the third transformer serves as the output terminal of the second interstage matching circuit and is connected to the input terminal of the second amplifier circuit. The second end of the secondary coil of the third transformer is connected to the positive terminal of the fifth power supply.

4. The low-noise amplifier circuit according to claim 1, characterized in that, Also includes: The first capacitor and the first inductor; The first terminal of the first capacitor is connected to the second terminal of the primary coil of the first transformer and the source of the common-gate amplifier transistor, respectively. The second terminal of the first capacitor is connected to the first terminal of the first inductor, and the second terminal of the first inductor is connected to the first terminal of the first resistor and the gate of the common-source amplifier transistor, respectively.

5. The low-noise amplifier circuit according to claim 1, characterized in that, The first amplifier circuit includes: a first amplifier transistor, a second amplifier transistor, a second inductor, and a second capacitor; The first end of the first amplifying transistor is connected to the first end of the second inductor, the second end of the second inductor is grounded, and the control end of the first amplifying transistor serves as the input end of the first amplifying circuit; the second end of the first amplifying transistor is connected to the first end of the second amplifying transistor, the control end of the second amplifying transistor is connected to the first end of the second capacitor, and the connection end is connected to the positive terminal of the sixth power supply; the second end of the second capacitor is grounded, and the second end of the second amplifying transistor serves as the output end of the first amplifying circuit.

6. The low-noise amplifier circuit according to claim 1, characterized in that, The second amplifier circuit includes: a third amplifier transistor, a fourth amplifier transistor, a third inductor, and a third capacitor; The first end of the third amplifying transistor is connected to the first end of the third inductor, the second end of the third inductor is grounded, and the control end of the third amplifying transistor serves as the input end of the second amplifying circuit; the second end of the third amplifying transistor is connected to the first end of the fourth amplifying transistor, the control end of the fourth amplifying transistor is connected to the first end of the third capacitor and the connection end is connected to the positive terminal of the seventh power supply; the second end of the third capacitor is grounded, and the second end of the fourth amplifying transistor serves as the output end of the second amplifying circuit.

7. The low-noise amplifier circuit according to claim 1, characterized in that, The power combining output matching circuit includes a fourth transformer and a fifth transformer; The first end of the primary coil of the fourth transformer serves as the first input terminal of the power combining output matching circuit; the second end of the primary coil of the fourth transformer is connected to the first end of the primary coil of the fifth transformer, and the connection terminal is connected to the positive terminal of the eighth power supply; the second end of the primary coil of the fifth transformer serves as the second input terminal of the power combining output matching circuit. The second end of the secondary coil of the fifth transformer is grounded, and the first end of the secondary coil of the fifth transformer is connected to the second end of the secondary coil of the fourth transformer. The first end of the secondary coil of the fourth transformer serves as the output terminal of the power combining output matching circuit.

8. The low-noise amplifier circuit according to any one of claims 1 to 7, characterized in that, The transmission line between the common-gate amplifier transistor and the first amplifier circuit is a first phase-adjustable transmission line; the transmission line between the common-source amplifier transistor and the second amplifier circuit is a second phase-adjustable transmission line.

9. The low-noise amplifier circuit according to claim 8, characterized in that, The first phase-adjustable transmission line includes: a first connecting line, a second connecting line, a third connecting line, a fourth connecting line, a fifth connecting line, a sixth connecting line, a first switched capacitor, a second switched capacitor, a third switched capacitor, a fourth switched capacitor, a fifth switched capacitor, and a sixth switched capacitor. The first end of the first connecting line and the first end of the first switched capacitor are both connected to the first port of the first phase-adjustable transmission line, and the first port serves as the first end of the first phase-adjustable transmission line to connect to the common-gate amplifier transistor. The second end of the first connecting line is connected to the first end of the sixth connecting line, and the first end of the fifth connecting line and the first end of the sixth switched capacitor are both connected to the second port of the first phase-adjustable transmission line. The second end of the fifth connecting line is connected to the second end of the sixth connecting line. The second end of the third connecting line is connected to the midpoint of the sixth connecting line; the first end of the third connecting line is connected to the first end of the third switched capacitor and the first end of the fourth switched capacitor, respectively; the second end of the second connecting line is connected to the second end of the third switched capacitor and the first end of the second switched capacitor, respectively; the second end of the second switched capacitor is connected to the first end of the first connecting line; the second end of the fourth connecting line is connected to the second end of the fourth switched capacitor and the first end of the fifth switched capacitor, respectively; the second end of the fifth switched capacitor is connected to the first end of the fifth connecting line. The first end of the second connecting line is connected to the second end of the first switched capacitor, and the connecting end is connected to the third port of the first phase-adjustable transmission line; the first end of the fourth connecting line is connected to the second end of the sixth switched capacitor, and the connecting end is connected to the third port of the first phase-adjustable transmission line, and the third port serves as the second end of the first phase-adjustable transmission line to connect to the first amplifier circuit. Among them, the first switched capacitor, the second switched capacitor, the third switched capacitor, the fourth switched capacitor, the fifth switched capacitor and the sixth switched capacitor are all switched capacitors with adjustable on / off states.

10. A wireless receiving system, characterized in that, Includes the low-noise amplifier circuit as described in any one of claims 1 to 9.

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