Current sampling circuit based on depletion transistor structure
By employing a current sampling circuit based on a depletion-mode NMOS transistor and a first enhancement-mode NMOS transistor, the problems of area and complex connections in traditional current sampling circuits are solved, achieving a smaller circuit size and a simpler connection structure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- NANJING ZHIXING ENERGY TECH CO LTD
- Filing Date
- 2025-07-24
- Publication Date
- 2026-05-12
AI Technical Summary
In traditional current sampling circuits, enhancement-mode NMOS transistors have large areas and sizes and complex connection structures, requiring a simpler current sampling circuit structure.
The high-voltage transistor design employs depletion-mode NMOS transistors and first enhancement-mode NMOS transistors, simplifying the circuit connection structure and retaining only the depletion-mode NMOS transistors and first enhancement-mode NMOS transistors as high-voltage transistors.
This resulted in smaller circuit size, simpler connection structure, and reduced circuit complexity.
Smart Images
Figure CN224231851U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of integrated circuit technology, and specifically relates to a current sampling circuit based on a power dissipation structure. Background Technology
[0002] In switching power supply applications, traditional current sampling circuits, such as Figure 1 As shown, it includes: a start-up resistor 102, an enhancement-mode NMOS transistor 103, an enhancement-mode NMOS transistor 100, an enhancement-mode NMOS transistor 101, a sampling resistor 104, a control module 106, and a power supply capacitor 105. The control module 106 controls the enhancement-mode NMOS transistor 103 to complete the start-up and power supply. The control module 106 outputs high and low levels through the DRV signal to realize the conduction and turn-off of the enhancement-mode NMOS transistors 100 and 101.
[0003] Figure 2 The waveform of a conventional current sampling circuit operating in a discontinuous state is shown. It is assumed that the current flowing into the VIN terminal is Iin, the on-resistance of enhancement-mode NMOS transistor 100 is R1, the on-resistance of enhancement-mode NMOS transistor 101 is R2, and the resistance of sampling resistor 104 is R3.
[0004] Therefore, the relationship between Iin and CS is:
[0005] In this circuit, enhancement-mode NMOS transistors 103, 100, and 101 are high-voltage transistors with relatively large areas and dimensions.
[0006] Therefore, a more concise current sampling circuit is needed. Summary of the Invention
[0007] The purpose of this invention is to provide a new current sampling circuit based on a depletion-mode NMOS transistor; this circuit only has a depletion-mode NMOS transistor and a first enhancement-mode NMOS transistor, resulting in a smaller circuit size and a simpler connection structure.
[0008] To achieve the above objectives, this utility model provides a current sampling circuit based on a depletion-mode NMOS transistor, which includes a depletion-mode NMOS transistor, a first enhancement-mode NMOS transistor, a second enhancement-mode NMOS transistor, a control module, and a power supply capacitor. The control module is electrically connected to the depletion-mode NMOS transistor, the first enhancement-mode NMOS transistor, and the second enhancement-mode NMOS transistor. One end of the power supply capacitor is grounded, and the other end is connected to the VCC terminal of the control module. The control module charges and supplies power to the power supply capacitor by controlling the gate and source terminals of the depletion-mode NMOS transistor.
[0009] Preferably, the drain of the depletion-type NMOS transistor is connected to the input voltage VIN, the gate of the depletion-type NMOS transistor is connected to the control module, the source of the depletion-type NMOS transistor is connected to the control module, and the source of the depletion-type NMOS transistor is connected to the drain of the second enhancement-type NMOS transistor.
[0010] Preferably, the gate terminal of the second enhancement-mode NMOS transistor is connected to the control module, and the signal is DRV1; the source terminal signal of the second enhancement-mode NMOS transistor is CS.
[0011] Preferably, the drain of the first enhancement-mode NMOS transistor is connected to the input voltage VIN, the source of the first enhancement-mode NMOS transistor is grounded, and the gate of the first enhancement-mode NMOS transistor is connected to the control module, with the signal being DRV.
[0012] Preferably, the gate and source terminals of the depletion-type NMOS transistor are connected by a resistor 302.
[0013] Preferably, a field-effect transistor is used instead of a depletion-type NMOS transistor.
[0014] Compared with the prior art, the present invention has the following beneficial effects:
[0015] The current sampling circuit based on the depletion-mode structure disclosed in this utility model has only high-voltage transistors, namely the depletion-mode NMOS transistor and the first enhancement-mode NMOS transistor, resulting in a smaller circuit size and a simpler connection structure. Attached Figure Description
[0016] Figure 1 This illustrates a conventional current sampling circuit in the background art;
[0017] Figure 2 The operating waveform of a conventional current sampling circuit in the background art is shown;
[0018] Figure 3 This invention illustrates a current sampling circuit based on a dissipative structure.
[0019] Figure 4 The working waveform of the current sampling circuit based on the dissipation structure in this invention is shown.
[0020] Figure label:
[0021] The components include a depletion-type NMOS transistor 300, a first enhancement-type NMOS transistor 301, a resistor 302, a second enhancement-type NMOS transistor 303, a control module 305, and a power supply capacitor 304. Detailed Implementation
[0022] To make the objectives, technical solutions, and advantages of this utility model clearer, the technical solutions of this application will be clearly and completely described below in conjunction with the accompanying drawings.
[0023] like Figure 3 As shown, this utility model discloses a current sampling circuit based on a depletion-mode NMOS transistor structure, which includes a depletion-mode NMOS transistor 300, a first enhancement-mode NMOS transistor 301, a second enhancement-mode NMOS transistor 303, a control module 305, and a power supply capacitor 304. The control module 305 is electrically connected to the depletion-mode NMOS transistor 300, the first enhancement-mode NMOS transistor 301, and the second enhancement-mode NMOS transistor 303, respectively. One end of the power supply capacitor 304 is grounded, and the other end is connected to the VCC terminal of the control module 305. The control module 305 completes the charging and supplying of the power supply capacitor 304 by controlling the gate and source terminals of the depletion-mode NMOS transistor 300.
[0024] In this current sampling circuit, only the depletion-mode NMOS transistor 300 and the first enhancement-mode NMOS transistor 301 are high-voltage transistors, therefore compared to Figure 1 The circuit shown is smaller and has a simpler connection.
[0025] In the current sampling circuit, the drain of the depletion-type NMOS transistor 300 is connected to the input voltage VIN, the gate of the depletion-type NMOS transistor 300 is connected to the control module 305, and the source of the depletion-type NMOS transistor 300 is also connected to the control module 305. The source of the depletion-type NMOS transistor 300 is connected to the drain of the second enhancement-type NMOS transistor 303, and the gate of the second enhancement-type NMOS transistor 303 is connected to the control module 305. This signal is defined as DRV1, and the source of the second enhancement-type NMOS transistor 303 is defined as CS. The drain of the first enhancement-type NMOS transistor 301 is connected to the input voltage VIN, the source of the first enhancement-type NMOS transistor 301 is grounded, and the gate of the first enhancement-type NMOS transistor 301 is connected to the control module 305. This signal is defined as DRV.
[0026] The current sampling circuit works as follows: the control module 305 controls the gate and source terminals of the depletion-type NMOS transistor 300 to charge and supply power to the power supply capacitor 304.
[0027] The operating waveform of the current sampling circuit is as follows Figure 4 As shown.
[0028] Specifically, when the control module 305 outputs a high level (DRV), the first enhancement-mode NMOS transistor 301 is turned on. Assume the current flowing into the first enhancement-mode NMOS transistor 301 from the VIN terminal is Iin. The on-state internal resistance of the first enhancement-mode NMOS transistor 301 is R1, then the on-state voltage drop of the first enhancement-mode NMOS transistor 301 is... Normally, this voltage is around 1V. However, due to the gate and source resistors 302, the depletion-type NMOS transistor 300 has a Vgs≈0V, which is greater than its negative turn-on threshold. Therefore, the depletion-type NMOS transistor 300 is in a fully conducting state, and its source voltage is almost equal to its drain voltage, V1. Since signals DRV1 and DRV are in phase and frequency, the second enhancement-type NMOS transistor 303 is also in a fully conducting state. Therefore, its source voltage is almost equal to its drain voltage, CS=V1.
[0029] When the DRV and DRV1 outputs of the control module 305 are low, the first enhancement-mode NMOS transistor 301 and the second enhancement-mode NMOS transistor 303 are turned off. The CS voltage is almost zero.
[0030] The depletion-type NMOS transistor 300 can be replaced by a field-effect transistor, and the specific connection method can also refer to the connection method disclosed in this utility model.
[0031] The above are merely preferred embodiments of this utility model and are not intended to limit the scope of this utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this utility model should be included within the protection scope of this utility model.
Claims
1. A current sampling circuit based on a dissipative structure, characterized in that, The system includes a depletion-type NMOS transistor (300), a first enhancement-type NMOS transistor (301), a second enhancement-type NMOS transistor (303), a control module (305), and a power supply capacitor (304). The control module (305) is electrically connected to the depletion-type NMOS transistor (300), the first enhancement-type NMOS transistor (301), and the second enhancement-type NMOS transistor (303). One end of the power supply capacitor (304) is grounded, and the other end is connected to the VCC terminal of the control module (305). The control module (305) charges and supplies power to the power supply capacitor (304) by controlling the gate and source terminals of the depletion-type NMOS transistor (300).
2. The current sampling circuit based on a dissipative structure according to claim 1, characterized in that, The drain of the depletion-type NMOS transistor (300) is connected to the input voltage VIN, the gate of the depletion-type NMOS transistor (300) is connected to the control module (305), and the source of the depletion-type NMOS transistor (300) is connected to the control module (305); the source of the depletion-type NMOS transistor (300) is connected to the drain of the second enhancement-type NMOS transistor (303).
3. A current sampling circuit based on a dissipative structure according to claim 2, characterized in that, The gate terminal of the second enhancement-type NMOS transistor (303) is connected to the control module (305), and the signal is DRV1; the source terminal signal of the second enhancement-type NMOS transistor (303) is CS.
4. A current sampling circuit based on a dissipative structure according to claim 3, characterized in that, The drain of the first enhancement-type NMOS transistor (301) is connected to the input voltage VIN, the source of the first enhancement-type NMOS transistor (301) is grounded, and the gate of the first enhancement-type NMOS transistor (301) is connected to the control module (305). The signal is DRV.
5. A current sampling circuit based on a dissipative structure according to claim 4, characterized in that, The gate and source terminals of the depletion-type NMOS transistor (300) are connected by a resistor (302).
6. A current sampling circuit based on a dissipative structure according to claim 5, characterized in that, The depletion-type NMOS transistor (300) is replaced by a field-effect transistor.