Functional detection and verification platform for RISC-V architecture

Abstract

The utility model provides a functional detection and verification platform used for an RISC-V framework. The RISC-V processor comprises an RISC-V processor, an HPCA connector and an HPCB connector are arranged on the RISC-V processor, the HPCA connector is connected with a FLASH memory and an SRAM memory, and the HPCB connector is connected with a CAN bus, a QSPI interface, an NAND memory, an SPACE WIRE bus, an IIC bus, a UART transmitter, a PWM, a 1553B bus and an SPI interface. The utility model relates to the technical field of integrated circuit design verification platforms.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuit design verification platform technology, and in particular to a functional testing and verification platform for RISC-V architecture. Background Technology

[0002] As an open instruction set architecture, RISC-V allows anyone to use, modify, and implement it. This openness fosters numerous innovations, particularly in flexible design for academic research and commercial applications. Compared to traditional proprietary architectures, RISC-V's design is relatively simple, making its implementation easier and suitable for education and experimentation. Hardware verification is a crucial step in ensuring design correctness, especially in integrated circuit design, where the complexity of verification is directly proportional to the design complexity. For RISC-V architectures, hardware verification platforms need to meet the following requirements: ensuring all instructions and functions function as expected, including basic operations, memory access, and interrupt handling; verifying the design's performance under different workloads, including timing, power consumption, and throughput metrics; and compatibility verification: ensuring the new design's compatibility with the existing RISC-V ecosystem, including different extensions and variants. The verification platform needs to detect potential security vulnerabilities to ensure the design is protected against attacks. As the RISC-V architecture continues to expand, the complexity of the design also increases. This includes multi-core processors, accelerators, and various peripheral interfaces. To ensure design correctness and performance, developing efficient hardware verification platforms is particularly important.

[0003] Existing technologies for RISC-V interface hardware verification platforms have several drawbacks, primarily including: insufficient interface standardization: although the RISC-V instruction set itself is open, its standardization with other peripherals and interfaces is low, potentially leading to compatibility issues between different implementations; in RISC-V systems, interface integration testing can be challenging, especially in multi-core or complex systems, requiring additional work to verify the interactivity and stability between different modules. These shortcomings may affect the efficiency and effectiveness of RISC-V interface hardware verification platforms. Utility Model Content

[0004] To address the problems existing in the prior art, this invention proposes a functional testing and verification platform for the RISC-V architecture. The aim is to verify the compatibility of the RISC-V processor with various peripherals.

[0005] To achieve the above objectives, the technical solution adopted by this utility model is: a functional testing and verification platform for RISC-V architecture, including a RISC-V processor, wherein the RISC-V processor is provided with an HPC_A connector and an HPC_B connector, the HPC_A connector is connected to a FLASH memory and an SRAM memory, and the HPC_B connector is connected to a CAN bus, a QSPI interface, a NAND memory, a SPACE WIRE bus, an IIC bus, a UART transmitter, a PWM, a 1553B bus, and an SPI interface.

[0006] Furthermore, the FLASH memory (3) includes an 8-bit FLASH memory, a 16-bit FLASH memory, and a 32-bit FLASH memory, and the SRAM memory includes an 8-bit SRAM memory, a 16-bit SRAM memory, and a 32-bit SRAM memory.

[0007] Furthermore, the chip model of the 8-bit FLASH memory is SST39LF, the chip model of the 16-bit FLASH memory is S29GL01GS, the chip model of the 32-bit FLASH memory is SST39VF6401, and the chip model used for the 8-bit SRAM memory, 16-bit SRAM memory and 32-bit SRAM memory is IS61WV20488ALL.

[0008] Furthermore, the NAND memory includes 8-bit NAND memory and 16-bit NAND memory.

[0009] In summary, this invention enables functional verification, performance testing, compatibility checks, and system integration testing of the RISC-V architecture. Functional verification ensures the processor can correctly communicate with peripherals, execute instructions, and process data, verifying whether the hardware design meets expected functionalities. Performance testing primarily evaluates the impact of different peripherals on system performance, including data transfer rates, response times, and processing speed, thereby optimizing the system design. Compatibility checks verify the compatibility of the RISC-V architecture with various peripherals, ensuring seamless collaboration, especially under different data formats and protocols. This invention effectively promotes the research and application of RISC-V-related technologies, improving system reliability and efficiency.

[0010] To more clearly illustrate the above-mentioned features of this utility model and the objectives it aims to achieve, the present utility model will be further described below in conjunction with the accompanying drawings and specific embodiments. Attached Figure Description

[0011] Figure 1This is a schematic diagram illustrating the connection between the HPC_A connector of this utility model and an external device.

[0012] Figure 2 This is a schematic diagram showing the connection between the HPC_B connector of this utility model and an external device.

[0013] Reference numerals: HPC_A connector 1; HPC_B connector 2; FLASH memory 3; SRAM memory 4; CAN bus 5; QSPI interface 6; NAND memory 7; SPACE WIRE bus 8; IIC bus 9; UART transmitter 10; 1553B bus 11; SPI interface 12; 8-bit FLASH memory 13; 16-bit FLASH memory 14; 32-bit FLASH memory 15; 8-bit SRAM memory 16; 16-bit SRAM memory 17; 32-bit SRAM memory 18; 8-bit NAND memory 19; 16-bit NAND memory 20. Detailed Implementation

[0014] like Figure 1 As shown, a functional testing and verification platform for a RISC-V architecture includes a RISC-V processor. The RISC-V processor is equipped with an HPC_A connector 1 and an HPC_B connector 2. The HPC_A connector 1 is connected to a FLASH memory 3 and an SRAM memory 4. The HPC_B connector 2 is connected to:

[0015] CAN bus 5 is used to perform data transmission and reception tests to confirm that the received data is consistent with the transmitted data, thereby ensuring that data in the CAN network can be reliably transmitted; at the same time, errors (such as bit errors) can be deliberately introduced to observe whether the system can detect and report errors, thus verifying the error detection capability of the CAN protocol.

[0016] QSPI interface 6 is used to verify the integrity and correctness of data during data transmission, ensuring that the received data is consistent with the sent data; at the same time, it checks whether the timing of the signals meets the requirements of the QSPI protocol, including clock signals, data validity and delay, to ensure that QSPI interface 6 can correctly execute various instructions and operations, such as reading, writing and erasing data, in accordance with the QSPI protocol specification.

[0017] NAND memory 7 is used to verify whether the interface between the RISC-V processor and the NAND memory 7 is correctly configured and can communicate normally, and to verify the integrity and consistency of data, ensuring that the RISC-V processor can correctly perform read and write operations on the NAND memory 7; and to evaluate the read and write speed and response time of the NAND memory 7 to ensure that it meets the performance requirements of the system.

[0018] The SPACE WIRE bus 8 utilizes the RISC-V processor to perform a series of data read and write tests on the SPACE WIRE bus 8 to verify the consistency between the transmitted and received data. This ensures that the RISC-V processor can accurately send and receive data through the SPACE WIRE bus 8.

[0019] IIC bus 9 is used to perform read and write tests to check whether the sent data and received data are consistent, ensuring that the RISC-V processor can accurately exchange data with peripherals through the IIC bus 9; at the same time, it connects multiple devices to verify whether each device can be correctly identified and accessed, ensuring that multiple IIC peripherals can be correctly addressed and accessed.

[0020] UART transmitter 10 is used to test various baud rate settings to ensure stable data transmission under each condition and to verify the communication capability of UART transmitter 10 at different baud rates. Data transmission in full-duplex and half-duplex modes is tested; the ability of UART transmitter 10 to support full-duplex or half-duplex modes is verified.

[0021] PWM: Check whether the frequency and duty cycle of the PWM output meet the preset values ​​to ensure that the RISC-V processor can generate PWM signals correctly. By adjusting the duty cycle, observe the change in LED brightness to ensure its linear response. Multiple LEDs can be connected at the same time to test the independence and simultaneity of PWM signals from different channels.

[0022] The 1553B bus 11 is used to verify the accuracy of data transmission between the RISC-V processor and the 1553B peripherals, including the sending and receiving of commands and data frames, to ensure that the processor can meet the requirements of the 1553B protocol, and to verify whether the data format, frame structure and timing conform to the standard; to evaluate the system's performance in real-time applications, and to ensure that data transmission latency and response time meet the requirements.

[0023] The SPI interface 12 is used to ensure that the RISC-V processor can correctly send and receive data through the SPI interface 12, and to verify the integrity and consistency of the data; at the same time, it verifies the timing requirements of SPI communication, including the stability of the clock signal, the validity of data, etc., and ensures the compatibility between the RISC-V processor's SPI interface 12 and external devices (such as sensors, memory, etc.) so that they can communicate normally.

[0024] Preferably, the FLASH memory (3) includes an 8-bit FLASH memory 13, a 16-bit FLASH memory 14, and a 32-bit FLASH memory 15. The 8-bit FLASH memory 13 is controlled using chip select CS0 and chip select CS3, while the 16-bit FLASH memory 14 and the 32-bit FLASH memory 15 are controlled using chip select CS0. This verifies whether the RISC-V processor's read and write operations on the FLASH memory 3 are correct, including address decoding and data transmission. Simultaneously, it verifies whether the process of booting the system from the FLASH memory 3 is smooth, ensuring that firmware loading and execution are error-free. The SRAM memory 4 includes an 8-bit SRAM memory 16, a 16-bit SRAM memory 17, and a 32-bit SRAM memory 18. Connecting the SRAM memory 4 verifies the correctness of the processor's data read and write operations, ensuring that the processor can correctly read data from and write data to the SRAM memory 4. Multiple read and write tests can also check the availability of all addresses, ensuring that the actual capacity of the SRAM memory 4 meets the design requirements. In addition, by introducing intentionally erroneous data, the system's ability to correctly identify and correct these errors can be tested, thus verifying the system's handling capabilities when storage errors occur.

[0025] Preferably, the 8-bit FLASH memory 13 uses a chip model of SST39LF, the 16-bit FLASH memory 14 uses a chip model of S29GL01GS, the 32-bit FLASH memory 15 uses a chip model of SST39VF6401, and the 8-bit SRAM memory 16, the 16-bit SRAM memory 17 and the 32-bit SRAM memory 18 all use a chip model of IS61WV20488ALL.

[0026] Preferably, the NAND memory 7 includes an 8-bit NAND memory 19 and a 16-bit NAND memory 20.

[0027] The above description is only the optimal solution embodiment of this utility model and is not intended to limit this utility model. Various modifications or substitutions made by those skilled in the art to this utility model without departing from the essence and protection scope of this utility model should also be within the protection scope of this utility model.

Claims

1. A functional testing and verification platform for RISC-V architecture, comprising a RISC-V processor, characterized in that, The RISC-V processor is equipped with an HPC_A connector (1) and an HPC_B connector (2). The HPC_A connector (1) is connected to a FLASH memory (3) and an SRAM memory (4). The HPC_B connector (2) is connected to a CAN bus (5), a QSPI interface (6), a NAND memory (7), a SPACE WIRE bus (8), an IIC bus (9), a UART transmitter (10), a PWM, a 1553B bus (11), and an SPI interface (12).

2. The functional testing and verification platform for RISC-V architecture according to claim 1, characterized in that: The FLASH memory (3) includes an 8-bit FLASH memory (13), a 16-bit FLASH memory (14), and a 32-bit FLASH memory (15), and the SRAM memory (4) includes an 8-bit SRAM memory (16), a 16-bit SRAM memory (17), and a 32-bit SRAM memory (18).

3. A functional testing and verification platform for RISC-V architecture according to claim 2, characterized in that: The chip model of the 8-bit FLASH memory (13) is SST39LF, the chip model of the 16-bit FLASH memory (14) is S29GL01GS, the chip model of the 32-bit FLASH memory (15) is SST39VF6401, and the chip model used in the 8-bit SRAM memory (16), 16-bit SRAM memory (17) and 32-bit SRAM memory (18) is IS61WV20488ALL.

4. A functional testing and verification platform for RISC-V architecture according to claim 1, characterized in that: The NAND memory (7) includes an 8-bit NAND memory (19) and a 16-bit NAND memory (20).

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