Operational amplifier and chip
By introducing a second current unit and a control unit into the operational amplifier, the problem of the current mirror not working properly under high common-mode conditions was solved, and the stability and normal function of the operational amplifier under high output voltage were achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- 3PEAK INC
- Filing Date
- 2025-04-17
- Publication Date
- 2026-05-12
AI Technical Summary
When the output voltage of an existing transistor operational amplifier is too high under high common-mode conditions, the current mirror cannot function properly, resulting in abnormal circuit function.
A second current unit and a control unit are introduced into the operational amplifier. Current replication is achieved through the current mirror of the second current unit, ensuring normal operation even when the output voltage increases.
提高了运算放大器在高共模条件下的鲁棒性，确保电路在高输出电压下正常工作，避免了电流镜功能失效。
Smart Images
Figure CN224233652U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of integrated circuit technology, specifically relating to an operational amplifier and chip. Background Technology
[0002] Most bipolar junction transistor (BJT) operational amplifiers use a similar output stage. Figure 1 The complementary emitter follower shown.
[0003] Transistors Q3 and Q4 act as PNP current mirrors (with a current mirror ratio of 1:m). The forward output current is provided by NPN transistor Q1, and the reverse output current is provided by PNP transistor Q2. The base of transistor Q5 is connected to the output of the preceding stage. When there is no signal output (i.e., the output current is zero), the emitter currents flowing through transistors Q3 and Q4 are equal.
[0004]
[0005] Among them, V BE_Q1 and V BE_Q2 V represents the base-emitter voltage of transistors Q1 and Q2, respectively. D1 and V D2 These represent the forward conduction voltages of diodes D1 and D2, respectively, and R1 and R2 represent the resistance values of the first resistor R1 and the second resistor R2, respectively. In most operational amplifiers, R1+R2 is approximately 10Ωs-100Ωs, and the no-load current is in the range of hundreds of µA to several mA.
[0006] When the output stage operates under high common-mode conditions, the voltage at the first node A is V. OUT +I*R1+V BE_Q1 Ignoring the voltage drop across the first resistor R1, the voltage at the first node A is VOUT + V. BE_Q1 The current mirror formed by transistors Q3 and Q4 needs to ensure that the emitter-collector voltage V of transistor Q4 is within acceptable limits. EC_Q4 The (emitter-collector) needs to be greater than a certain threshold Vmarg to ensure the current mirror works properly. This means the collector current of transistor Q4 is m*I1 (ignoring the small amplification factor beta and the early base width modulation effect). If the output voltage VOUT increases, causing V... EC_Q4 If the current is less than Vmarg, the collector current of transistor Q4 will be less than m*I1 or even non-existent. Consequently, transistors Q3 and Q4 will be unable to provide the correct current, leading to abnormal circuit function. Therefore, Figure 1 Output voltage V under structure OUTThe maximum voltage, assuming correct functionality, is AVDD-Vmarg-V. BE_Q1 This can be limited in some high common-mode operational amplifier applications.
[0007] The information disclosed in this background section is intended only to enhance the understanding of the overall background of this utility model and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Utility Model Content
[0008] The purpose of this invention is to provide an operational amplifier and chip that can improve the robustness of the circuit under high common-mode operating conditions.
[0009] To achieve the above objectives, a specific embodiment of this utility model provides the following technical solution: an operational amplifier, including an output stage; the output stage includes a first transistor, a second transistor, a bias unit, a first current unit, a second current unit, and a control unit; the first current unit is connected to the control terminal of the first transistor to form a first node; the control unit is connected to the control terminal of the second transistor to form a second node; the bias unit is connected to the first node and the second node; the second terminal of the first transistor is connected to a power supply voltage; the second terminal of the second transistor is connected to ground voltage; the first terminal of the first transistor and the first terminal of the second transistor are connected to form the output terminal of the operational amplifier; the second current unit is connected to the second node to inject current into the second node.
[0010] In one or more embodiments of the present invention, the first current unit includes a first current mirror and a first current source, wherein the first current mirror is connected to the control terminal of the first current source and the first transistor.
[0011] In one or more embodiments of the present invention, the first current mirror includes a third transistor and a fourth transistor. The first terminals of the third transistor and the fourth transistor are connected to the power supply voltage. The control terminals of the third transistor, the second terminals of the third transistor, and the fourth transistor are connected to the first current mirror. The second terminal of the fourth transistor is connected to the control terminal of the first transistor.
[0012] In one or more embodiments of the present invention, the second current unit includes a second current mirror and a second current source, wherein the second current mirror is connected to the second current source and the second node.
[0013] In one or more embodiments of the present invention, the second current mirror includes a fifth transistor and a sixth transistor. The first terminal of the fifth transistor and the first terminal of the sixth transistor are connected to the power supply voltage. The control terminal of the fifth transistor, the second terminal of the fifth transistor, and the control terminal of the sixth transistor are connected to the second current mirror. The second terminal of the sixth transistor is connected to the second node.
[0014] In one or more embodiments of this utility model, the biasing unit includes a first diode and a second diode, the anode of the first diode is connected to a first node, the anode of the second diode is connected to the cathode of the first diode, and the cathode of the second diode is connected to a second node.
[0015] In one or more embodiments of the present invention, the control unit includes a seventh transistor, the second terminal of the seventh transistor is connected to the control terminal of the second transistor, the first terminal of the seventh transistor is connected to ground voltage, and the control terminal of the seventh transistor is connected to the stage preceding the output stage to receive control signals.
[0016] In one or more embodiments of the present invention, the output stage further includes a first resistor and a second resistor, the first end of the first resistor is connected to the first end of the first transistor, the first end of the second resistor is connected to the first end of the second transistor, and the second end of the first resistor and the second end of the second resistor are connected to form the output terminal of the operational amplifier.
[0017] In one or more embodiments of this utility model, both the first transistor and the second transistor are triodes.
[0018] This utility model also discloses a chip, including the aforementioned operational amplifier.
[0019] Compared with the prior art, the operational amplifier and chip of this invention, through the second current unit, can still ensure that the second current unit can correctly replicate and generate current when the output voltage rises and the first current unit cannot correctly replicate and generate current, so that the control unit can work normally, thereby ensuring the normal operation of the entire operational amplifier, and increasing the upper limit of the operational amplifier's operation, which can ensure that the operational amplifier works normally under high common-mode operating conditions. Attached Figure Description
[0020] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0021] Figure 1 This is a circuit schematic of an operational amplifier in the prior art.
[0022] Figure 2 This is a circuit diagram of an operational amplifier in one embodiment of the present invention. Detailed Implementation
[0023] To enable those skilled in the art to better understand the technical solutions of this utility model, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this utility model.
[0024] The terms "coupled," "connected," or "linked" in this specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in utility models, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.
[0025] In the detailed description of this specification, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein exemplary embodiments are shown by way of example that may be implemented. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this application. Therefore, the following detailed description should not be considered limiting.
[0026] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.
[0027] For the purposes of this application, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this application, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
[0028] Various components and devices may be referred to or shown in the singular (e.g., “MOS transistor”, “transistor”, “switch”, etc.) in this document, but only for the convenience of discussion, and any element referred to in the singular may include multiple such elements as taught herein.
[0029] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used in relation to embodiments of this application are synonymous.
[0030] like Figure 2 As shown, an operational amplifier in one embodiment of the present invention includes an output stage; the output stage includes a first transistor Q1, a second transistor Q2, a first resistor R1, a second resistor R2, a bias unit 10, a first current unit 20, a second current unit 30, and a control unit 40.
[0031] The first current unit 20 is connected to the control terminal of the first transistor Q1 to form a first node A. The control unit 40 is connected to the control terminal of the second transistor Q2 to form a second node B. The bias unit 10 is connected to the first node A and the second node B. The second terminal of the first transistor Q1 is connected to the power supply voltage AVDD, and the second terminal of the second transistor Q2 is connected to the ground voltage. The first terminal of the first resistor R1 is connected to the first terminal of the first transistor Q1, and the first terminal of the second resistor R2 is connected to the first terminal of the second transistor Q2. The second terminals of the first resistor R1 and the second terminal of the second resistor R2 are connected to form the output terminal of the operational amplifier to generate the output voltage VOUT. The second current unit 30 is connected to the second node B. In other embodiments, the first resistor R1 and the second resistor R2 may not be provided.
[0032] like Figure 2 As shown, the bias unit 10 includes a first diode D1 and a second diode D2. The anode of the first diode D1 is connected to the first node A, the anode of the second diode D2 is connected to the cathode of the first diode D1, and the cathode of the second diode D2 is connected to the second node B.
[0033] like Figure 2 As shown, the first current unit 20 includes a first current mirror and a first current source I1. The first current mirror is connected to the control terminal of the first current source I1 and the first transistor Q1.
[0034] The first current mirror includes a third transistor Q3 and a fourth transistor Q4. The first terminal of the third transistor Q3 and the first terminal of the fourth transistor Q4 are connected to the power supply voltage AVDD. The control terminal of the third transistor Q3, the second terminal of the third transistor Q3, and the control terminal of the fourth transistor Q4 are connected to the first current mirror. The second terminal of the fourth transistor Q4 is connected to the control terminal of the first transistor Q1.
[0035] like Figure 2 As shown, the control unit 40 includes a fifth transistor Q5. The second terminal of the fifth transistor Q5 is connected to the control terminal of the second transistor Q2, and the first terminal of the fifth transistor Q5 is connected to ground. The control terminal of the fifth transistor Q5 is connected to the stage preceding the output stage to receive control signals. The stage preceding the output stage can be the input stage of an operational amplifier.
[0036] like Figure 2 As shown, the second current unit 30 includes a second current mirror and a second current source I2, and the second current mirror is connected to the second current source I2 and the second node B.
[0037] The second current mirror includes a sixth transistor Q6 and a seventh transistor Q7. The first terminal of the sixth transistor Q6 and the first terminal of the seventh transistor Q7 are connected to the power supply voltage AVDD. The control terminal of the sixth transistor Q6, the second terminal of the sixth transistor Q6, and the control terminal of the seventh transistor Q7 are connected to the second current mirror. The second terminal of the seventh transistor Q7 is connected to the second node B.
[0038] In one embodiment, the first transistor Q1 and the seventh transistor Q7 are NPN transistors; the second transistor Q2, the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5, and the sixth transistor Q6 are PNP transistors. In other embodiments, the first transistor Q1 and the seventh transistor Q7 are PNP transistors; the second transistor Q2, the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5, and the sixth transistor Q6 are NPN transistors.
[0039] The first terminals of the first transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5, the sixth transistor Q6, and the seventh transistor Q7 are emitters. The second terminals of the first transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5, the sixth transistor Q6, and the seventh transistor Q7 are collectors. The control terminals of the first transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5, the sixth transistor Q6, and the seventh transistor Q7 are bases.
[0040] exist Figure 1 Based on this, a second current mirror consisting of a sixth transistor Q6 and a seventh transistor Q7 is added, with the collector of the seventh transistor Q7 connected to the second node B, and the voltage V at the second node B... B Controlled by the output voltage VOUT, i.e.
[0041] V B =VOUT-V BE_Q2 (1)
[0042] At this time, the voltage V at the first node A A =VOUT+V BE_Q1 Assume the voltage V at the first node A is... A Just as the fourth transistor Q4 enters the saturation region critical point (the point where the current replication function fails), the threshold voltage of the fourth transistor Q4 is Vmarg, and the output voltage VOUT is exactly [value missing].
[0043] VOUT = AVDD - Vmarg - V BE_Q1 (2)
[0044] Substituting equation (2) into equation (1), the voltage V at the second node B is then... B for
[0045] V B =AVDD-Vmarg-V BE_Q1 -V BE_Q2 (3)
[0046] Then the emitter-base voltage V of the seventh transistor Q7 EC_Q7 for
[0047] V EC_Q7 =Vmarg+V BE_Q1 +V BE_Q2 (4)
[0048] Assume that the minimum V required to guarantee the correct operation of the seventh transistor Q7 EC_Q7 Also Vmarg, we can use formula (4) to deduce that when the fourth transistor Q4 is at the critical point of saturation, the seventh transistor Q7 still has a relatively large margin from the saturation region. In other words, when the fourth transistor Q4 cannot correctly replicate the current, the seventh transistor Q7 can still correctly replicate the current, thus ensuring that there is enough current flowing into the fifth transistor Q5 to ensure the correct function of the operational amplifier.
[0049] In summary, the addition of the second current mirror ensures that even when the output voltage VOUT increases, causing the fourth transistor Q4 to enter the saturation region and fail to correctly replicate the current, the seventh transistor Q7 can still correctly replicate the current in the amplification region, allowing the fifth transistor Q5 to continue operating normally, thus guaranteeing the normal operation of the entire operational amplifier. In other words, the second current unit 30 can increase the upper limit of the operational amplifier's operation, ensuring that the operational amplifier operates normally under high common-mode conditions.
[0050] This invention also provides a chip, including the above-described operational amplifier.
[0051] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims.
[0052] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
Claims
1. An operational amplifier, characterized in that, The system includes an output stage; the output stage includes a first transistor, a second transistor, a bias unit, a first current unit, a second current unit, and a control unit. The first current unit is connected to the control terminal of the first transistor to form a first node. The control unit is connected to the control terminal of the second transistor to form a second node. The bias unit is connected to the first node and the second node. The second terminal of the first transistor is connected to the power supply voltage. The second terminal of the second transistor is connected to the ground voltage. The first terminal of the first transistor and the first terminal of the second transistor are connected to form the output terminal of the operational amplifier. The second current unit is connected to the second node.
2. The operational amplifier according to claim 1, characterized in that, The first current unit includes a first current mirror and a first current source, and the first current mirror is connected to the control terminal of the first current source and the first transistor.
3. The operational amplifier according to claim 2, characterized in that, The first current mirror includes a third transistor and a fourth transistor. The first terminals of the third transistor and the fourth transistor are connected to the power supply voltage. The control terminals of the third transistor, the second terminals of the third transistor, and the fourth transistor are connected to the first current mirror. The second terminal of the fourth transistor is connected to the control terminal of the first transistor.
4. The operational amplifier according to claim 1, characterized in that, The second current unit includes a second current mirror and a second current source, and the second current mirror is connected to the second current source and the second node.
5. The operational amplifier according to claim 4, characterized in that, The second current mirror includes a fifth transistor and a sixth transistor. The first terminals of the fifth transistor and the sixth transistor are connected to the power supply voltage. The control terminals of the fifth transistor, the second terminals of the fifth transistor, and the control terminals of the sixth transistor are connected to the second current mirror. The second terminal of the sixth transistor is connected to the second node.
6. The operational amplifier according to claim 1, characterized in that, The bias unit includes a first diode and a second diode. The anode of the first diode is connected to a first node, the anode of the second diode is connected to the cathode of the first diode, and the cathode of the second diode is connected to a second node.
7. The operational amplifier according to claim 1, characterized in that, The control unit includes a seventh transistor, the second terminal of which is connected to the control terminal of the second transistor, the first terminal of which is connected to ground voltage, and the control terminal of the seventh transistor is connected to the stage preceding the output stage to receive control signals.
8. The operational amplifier according to claim 1, characterized in that, The output stage further includes a first resistor and a second resistor. The first end of the first resistor is connected to the first end of the first transistor, the first end of the second resistor is connected to the first end of the second transistor, and the second end of the first resistor and the second end of the second resistor are connected to form the output terminal of the operational amplifier.
9. The operational amplifier according to claim 1, characterized in that, Both the first transistor and the second transistor are bipolar transistors.
10. A chip, characterized in that, Includes the operational amplifier as described in any one of claims 1 to 9.