MIPI-LVDS video signal conversion bridging board card based on FPGA

Abstract

The utility model discloses an FPGA-based MIPI-LVDS video signal conversion bridging board card, and the board card comprises a video interface which is used for receiving and transmitting an external video source signal; the video source processing SOC is connected with the video interface and is used for processing a video signal and outputting an LVDS (Low Voltage Differential Signaling) signal; the FPGA bridging system is connected with the video source processing SOC and is used for converting the LVDS signal into an MIPI (Mobile Industry Processor Interface) signal; the video serializer is used for converting the MIPI signal into a serial signal and outputting the serial signal to equipment to be tested; the SDRAM module is used for caching video data; the Ethernet transceiver is used for remote control and program upgrading; a crystal oscillator; and a power management module. Through the cooperation of the FPGA bridging system and by utilizing the programmable characteristic of the FPGA bridging system, the compatibility of various interface standards can be realized, the problem that the interface standards among different devices are not uniform is solved, the bridging board card can be seamlessly connected with heterogeneous devices such as a camera and a display module, the compatibility and integration efficiency of an automobile electronic system are remarkably improved, and the application prospect is wide. Therefore, the test process is simplified.

Description

Technical Field

[0001] This utility model relates to the field of signal conversion technology, and in particular to an FPGA-based MIPI-LVDS video signal conversion bridge board. Background Technology

[0002] With the rapid development of autonomous driving technology, vehicles are increasingly reliant on visual perception systems. As a core support for autonomous driving technology, the performance and compatibility of automotive electronics directly affect the stability and safety of the entire autonomous driving system. Among the many components of automotive electronics, cameras and display modules play a crucial role. They are responsible for capturing information about the external environment and presenting it intuitively to the driver or autonomous driving system, thereby enabling accurate perception and decision-making regarding the vehicle's surroundings.

[0003] In automotive electronics, cameras and display modules widely adopt MIPI and LVDS interface standards. MIPI interfaces, due to their low power consumption and high bandwidth, are widely used in mobile devices and automotive cameras; while LVDS interfaces, with their strong anti-interference capabilities and long transmission distances, have become the preferred standard for automotive displays and sensors. However, as the functions of automotive electronic products become increasingly rich and diverse, the inconsistency in interface standards between different devices is becoming increasingly prominent. This not only increases the difficulty of system integration but also makes the testing process complex and time-consuming, thus affecting the product's time-to-market and market competitiveness.

[0004] In existing technologies, system integration typically relies on dedicated ASIC (Application-Specific Integrated Circuit) bridge chips to achieve MIPI and LVDS signal conversion. These chips implement specific functions through fixed circuit designs, and while they can meet basic requirements in specific scenarios, their limitations are also significant. First, ASIC chips have fixed functions, poor flexibility, and difficulty adapting to diverse interface requirements and rapidly changing technical standards. This means that once the design is completed, ASIC chips are difficult to adjust or upgrade based on market demands or technological evolution. Second, ASIC design and manufacturing costs are high, requiring substantial initial investment, and they cannot adapt to small-batch production or customized needs. In the automotive electronics field, different vehicle models or testing systems have significantly different requirements for interface specifications, making it difficult for ASIC solutions to provide cost-effective solutions. Summary of the Invention

[0005] This invention overcomes the shortcomings of the prior art and provides an FPGA-based MIPI-LVDS video signal conversion bridge board.

[0006] To achieve the above objectives, the technical solution adopted by this utility model is: an FPGA-based MIPI-LVDS video signal conversion bridge board, comprising:

[0007] The video interface is used to send and receive signals from external video sources.

[0008] The video source processing SOC is connected to the video interface and is used to process video signals and output LVDS signals;

[0009] An FPGA bridging system, connected to the video source processing SOC, is used to convert LVDS signals into MIPI signals;

[0010] A video serial deserializer, connected to the FPGA bridging system, is used to convert MIPI signals into serial signals and output them to the device under test.

[0011] The SDRAM module is connected to the video source processing SOC and the FPGA bridging system and is used to cache video data;

[0012] An Ethernet transceiver, connected to the video source processing SOC and the FPGA bridging system, is used for remote control and program upgrades;

[0013] A crystal oscillator provides a clock reference for the video source processing SOC and the FPGA bridging system;

[0014] The power management module is used to provide stable power to all components.

[0015] In a preferred embodiment of this invention, the FPGA bridging system includes an adaptive level shifting circuit for dynamically matching the electrical characteristic differences between the MIPID-PHY and LVDS.

[0016] In a preferred embodiment of this invention, the adaptive level conversion circuit includes a dynamic termination matching module that automatically adjusts the termination resistance value according to the high-speed mode or the low-power mode.

[0017] In a preferred embodiment of this utility model, the FPGA bridging system employs multi-channel data processing to achieve protocol conversion and data synchronization between the four MIPI data channels and LVDS.

[0018] In a preferred embodiment of this utility model, the FPGA bridging system adopts a modular logic design, including:

[0019] MIPICSI-2 / DSI protocol parsing module;

[0020] LVDS data encapsulation module;

[0021] Image processing module.

[0022] In a preferred embodiment of this utility model, the video interface is a DisplayPort or HDMI interface.

[0023] In a preferred embodiment of this invention, the video serializer / deserializer supports GMSL signal transmission and is connected to the device under test via a coaxial cable.

[0024] In a preferred embodiment of this utility model, the Ethernet transceiver is a gigabit Ethernet interface, used for remote programming of FPGA programs and transmission of SOC control commands.

[0025] In a preferred embodiment of this invention, the video source processing SOC uses a multi-protocol support chip, compatible with LVDS, DisplayPort, and HDMI inputs.

[0026] In a preferred embodiment of this utility model, an automated testing platform is also included for automated verification of the signal integrity, timing synchronization, and protocol conversion functions of the bridging board.

[0027] This utility model solves the defects existing in the background technology, and has the following beneficial effects:

[0028] (1) This utility model provides a MIPI-LVDS video signal conversion bridge board based on FPGA. With the cooperation of the FPGA bridging system, the programmable characteristics of the FPGA can achieve compatibility with multiple interface standards, avoiding the difficulty of adapting to diverse interface requirements due to the fixed functions of traditional ASIC chips. Furthermore, the FPGA bridging system solves the problem of inconsistent interface standards between different devices by dynamically configuring logic units, enabling the bridge board to seamlessly connect heterogeneous devices such as cameras and display modules, significantly improving the compatibility and integration efficiency of automotive electronic systems, thereby simplifying the testing process.

[0029] (2) In this utility model, the modular logic design inside the FPGA bridging system is used to support real-time scaling, cropping, format conversion and other processing of images. Flexible algorithm deployment is achieved through programmable logic to solve the diverse requirements of image processing in automotive vision systems, ensure that video signals maintain high quality during conversion, and meet the real-time and accuracy requirements in autonomous driving scenarios.

[0030] (3) In this utility model, compared with the long cycle design and high cost investment of traditional ASIC chips, the FPGA solution greatly shortens the development cycle through field programmability, supports rapid iteration, and only needs to update the configuration file to achieve functional optimization, significantly reducing the development cost of automotive electronic automated testing system, thus making it suitable for the rapidly evolving field of autonomous driving, enabling products to respond to market changes in a timely manner.

[0031] (4) In this utility model, with the cooperation of the Ethernet transceiver, the system can be dynamically maintained, support remote firmware updates, solve the adaptation problem of subsequent technology evolution and standard changes, and combined with modular design, system maintenance and function expansion are more convenient, extending the life cycle of the bridge board and thus reducing long-term operation and maintenance costs. Attached Figure Description

[0032] The present invention will be further described below with reference to the accompanying drawings and embodiments;

[0033] Figure 1 This is a block diagram of a bridge board system according to a preferred embodiment of the present invention. Detailed Implementation

[0034] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. These drawings are simplified schematic diagrams, which are only used to illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0035] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "setup," and "connection" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this application based on the specific circumstances.

[0036] like Figure 1 As shown, an FPGA-based MIPI-LVDS video signal conversion bridge board includes:

[0037] The video interface is used to send and receive signals from external video sources.

[0038] It should be noted that the video interface is a DisplayPort or HDMI interface, which supports high-bandwidth video data transmission and can input video signals into the bridge card in digital form.

[0039] The video source processing SOC connects to the video interface and is used to process video signals and output LVDS signals.

[0040] It should be noted that the video source processing SOC uses a multi-protocol support chip, compatible with LVDS, DisplayPort, and HDMI inputs.

[0041] Specifically, select a chip that supports LVDS output (such as TI's DS90UB series) to process video signals and output LVDS data streams. It is responsible for receiving video signals from the interface, supports multiple video protocols (such as LVDS, DisplayPort, HDMI), can decode and process input video signals, and output LVDS format video data streams. It can adapt to multiple video input sources and output LVDS signals that meet the requirements.

[0042] An FPGA bridging system, connected to a video source processing SOC, is used to convert LVDS signals to MIPI signals.

[0043] It should be noted that the FPGA bridging system uses Xilinx Zynq UltraScale+ZU5EV (integrated ARM core, supports 4-channel MIPID-PHY), and supports multiple interface standards through programming, including MIPI CSI-2, DSI, LVDS, etc.

[0044] Specifically, the FPGA bridging system includes an adaptive level shifting circuit for dynamically matching the electrical characteristics differences between the MIPID-PHY and LVDS; the adaptive level shifting circuit includes a dynamic termination matching module that automatically adjusts the termination resistance value according to high-speed mode or low-power mode to ensure stable signal transmission between different interfaces.

[0045] The level conversion circuit uses the SN65LVDS391 chip, which automatically switches the terminating resistor (100Ω / 150Ω) according to the operating mode (high speed / low power).

[0046] Furthermore, the FPGA bridging system employs a modular logic design, including: a MIPI CSI-2 / DSI protocol parsing module; an LVDS data encapsulation module; and an image processing module (supporting scaling, cropping, and format conversion), which are responsible for protocol parsing, data encapsulation, and image processing tasks, respectively.

[0047] A video serializer / deserializer, connected to an FPGA bridging system, is used to convert MIPI signals into serial signals for output to the device under test.

[0048] It should be noted that the video serializer supports GMSL signal transmission and connects to the device under test via a coaxial cable; it uses the MAX96705 chip to convert the MIPI signal output by the FPGA into a GMSL serial signal; the video serializer converts parallel data into serial data, thus meeting the needs of long-distance transmission.

[0049] The SDRAM module connects to the video source processing SOC and FPGA bridging system to cache video data.

[0050] It should be noted that the SDRAM module uses Micron's MT41K256M16 chip. During video processing, SDRAM serves as a temporary storage medium, alleviating data transmission pressure and ensuring the continuity and stability of video data.

[0051] Ethernet transceivers connect to video source processing SOCs and FPGA bridging systems for remote control and program upgrades.

[0052] It should be noted that the Ethernet transceiver has a gigabit Ethernet interface and is used for remote programming of FPGA programs and transmission of SOC control commands. Through the Ethernet transceiver, users can remotely access the bridging board to perform operations such as programming, parameter configuration, and troubleshooting, which improves the maintainability and flexibility of the system.

[0053] Crystal oscillators provide a clock reference for video source processing SOC and FPGA bridging systems.

[0054] Specifically, by setting the crystal oscillator, the synchronous operation of various components within the system is ensured, avoiding signal distortion or data errors caused by clock deviation.

[0055] The power management module is used to provide stable power to all components.

[0056] Specifically, the power management module is responsible for providing stable and reliable power to the various components in the bridge board. Through measures such as voltage conversion, current limiting, and protection circuits, it ensures that each component operates within its normal operating voltage and current range, thereby improving the stability and reliability of the system.

[0057] It also includes an automated testing platform for automated verification of the signal integrity, timing synchronization, and protocol conversion functions of the bridging board.

[0058] Specifically, by using pre-set test cases and automated scripts, comprehensive testing of the bridging board is conducted to improve testing efficiency and accuracy, thereby ensuring product quality.

[0059] FPGA bridging system resource optimization configuration includes:

[0060] Logic unit allocation: 60% for protocol conversion, 30% for image processing, and 10% for control logic;

[0061] Memory blocks are preferentially allocated to video frame buffers to meet the storage requirements of high-resolution video data.

[0062] Specifically, this optimized configuration method can maximize the saving of FPGA resources and improve the system's integration and reliability while ensuring system performance.

[0063] Workflow:

[0064] Video input mode:

[0065] 1. Input the DisplayPort or HDMI video source to the video source processing SOC for processing;

[0066] 2. The video source processing SOC buffers the processed data into the SDRAM module and outputs the LVDS signal to the FPGA bridging system;

[0067] 3. The FPGA bridging system converts the LVDS signal into a MIPI CSI-2 signal;

[0068] 4. The video serializer converts the MIPI signal into a GMSL signal and outputs it to the device under test via a coaxial cable.

[0069] Video output mode:

[0070] 1. The GMSL signal of the device under test is input to the video serializer and deserializer, and converted into a MIPI signal;

[0071] 2. The FPGA bridging system converts MIPI signals into LVDS signals;

[0072] 3. The video source processing SOC reads LVDS data, caches it to the SDRAM module, and then outputs it for display via DisplayPort or HDMI.

[0073] Based on the above description and the preferred embodiments of this utility model, it will be apparent to those skilled in the art that this utility model is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this utility model. Therefore, the embodiments should be considered exemplary and non-limiting in all respects. The scope of this utility model is defined by the appended claims rather than the foregoing description, and thus all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this utility model. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0074] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A MIPI-LVDS video signal conversion bridge board based on FPGA, characterized in that, include: The video interface is used to send and receive signals from external video sources. The video source processing SOC is connected to the video interface and is used to process video signals and output LVDS signals; An FPGA bridging system, connected to the video source processing SOC, is used to convert LVDS signals into MIPI signals; A video serial deserializer, connected to the FPGA bridging system, is used to convert MIPI signals into serial signals and output them to the device under test. The SDRAM module is connected to the video source processing SOC and the FPGA bridging system and is used to cache video data; An Ethernet transceiver, connected to the video source processing SOC and the FPGA bridging system, is used for remote control and program upgrades; A crystal oscillator provides a clock reference for the video source processing SOC and the FPGA bridging system; The power management module is used to provide stable power to all components.

2. The FPGA-based MIPI-LVDS video signal conversion bridge board according to claim 1, characterized in that: The FPGA bridging system includes an adaptive level shifting circuit for dynamically matching the electrical characteristic differences between the MIPID-PHY and LVDS.

3. The FPGA-based MIPI-LVDS video signal conversion bridge board according to claim 2, characterized in that: The adaptive level conversion circuit includes a dynamic termination matching module that automatically adjusts the termination resistance value according to the high-speed mode or the low-power mode.

4. The FPGA-based MIPI-LVDS video signal conversion bridge board according to claim 1, characterized in that: The FPGA bridging system employs multi-channel data processing to achieve protocol conversion and data synchronization between the four MIPI data channels and LVDS.

5. The FPGA-based MIPI-LVDS video signal conversion bridge board according to claim 1, characterized in that: The FPGA bridging system employs a modular logic design, including: MIPI CSI-2 / DSI protocol parsing module; LVDS data encapsulation module; Image processing module.

6. The FPGA-based MIPI-LVDS video signal conversion bridge board according to claim 1, characterized in that: The video interface is either DisplayPort or HDMI.

7. The FPGA-based MIPI-LVDS video signal conversion bridge board according to claim 1, characterized in that: The video serializer / deserializer supports GMSL signal transmission and connects to the device under test via a coaxial cable.

8. The FPGA-based MIPI-LVDS video signal conversion bridge board according to claim 1, characterized in that: The Ethernet transceiver has a gigabit Ethernet interface and is used for remote programming of FPGA programs and transmission of SOC control commands.

9. The FPGA-based MIPI-LVDS video signal conversion bridge board according to claim 1, characterized in that: The video source processing SOC uses a multi-protocol support chip, compatible with LVDS, DisplayPort, and HDMI inputs.

10. The FPGA-based MIPI-LVDS video signal conversion bridge board according to claim 1, characterized in that: It also includes an automated testing platform for automated verification of the signal integrity, timing synchronization, and protocol conversion functions of the bridging board.

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