Clock signal synchronization method, transceiver and transmitter

Abstract

The invention relates to a method for synchronizing a clock signal (CLK) with a reference clock (RCLK), wherein the clock signal is obtained on the basis of a local master clock and an adjustable frequency multiplication factor. The method utilizes a master clock signal to synchronize a frequency multiplication factor to compensate for frequency deviation. In a data packet gap of communication standards such as Bluetooth, corresponding signals are transmitted and received.

Description

[0001] This application claims priority to Danish application PA 2023 70393, filed on 2 August 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to a method for synchronizing a clock signal with a reference clock. This application also relates to transceivers and transmitter devices. Background Technology

[0003] In certain applications, particularly those involving communication between master and slave devices, time synchronization between the master clock and the slave device's internal clock can be critical for providing smooth functionality and data communication. Typically, this synchronization may involve the exchange of special data packets, known as time synchronization packets, between the master and slave devices. Furthermore, some data communication protocols include features to compensate for delays between communication signals, enabling error-free data communication.

[0004] For example, in some media applications, such as during audio or video recording, the actual sound or video capture can be performed by multiple different devices, which are independent of each other. For instance, spatially separated devices can be used to record signals from one or more sound sources. Each device records sound, but there is a certain delay depending on its distance from the one or more sound sources.

[0005] The recorded material can then be processed to obtain certain functions, such as identifying the location of a sound source to generate a complete sound environment. When using video material, the recorded video and audio portions can be synchronized. Therefore, in addition to synchronizing data communication in such applications, the actual recording time is also required, including internal timestamps for recording audio or video data. This synchronization becomes even more important when the distance between the devices recording audio or video is considerable. For example, due to the relatively slow speed of sound propagation, various devices at different distances from one or more sound sources will record sound at different times. To align the various recorded audio signals in time, cross-correlation can be used. However, this cross-correlation is still not completely error-free. Furthermore, in addition to the aforementioned delays, each device must have the same sampling rate, especially when recording for extended periods. Finally, all devices should rely on a common recording start and end time to perform the aforementioned cross-correlation and alignment processing on the different recorded signals.

[0006] While these issues can be addressed with certain hardware solutions (such as OCXOs), these solutions are expensive and cannot be guaranteed to function perfectly over a long lifespan. However, this problem persists in master-slave configurations.

[0007] Therefore, the purpose of this application is to provide a method for synchronizing a clock signal with a reference clock, which can compensate for time or frequency deviations even in environments where communication between devices is discontinuous and may be interrupted. Summary of the Invention

[0008] This objective, and others, are addressed by the subject matter of each independent claim. The dependent claims describe the features and further aspects of the proposed principle.

[0009] The inventors propose a new and improved method for synchronizing a device's clock signal with a reference clock, wherein the reference clock is decoupled from the actual device's clock signal. This configuration is similar to a master-slave configuration, where the master device includes a reference clock for synchronizing the slave device's clock.

[0010] A reference clock is typically provided as a global master clock to synchronize other clock signals within the system, especially in master-slave configurations. Other clock signals are usually derived from a local master clock, which is a subset of the slave device's clock.

[0011] However, unlike traditional systems that adjust the local master clock of slave devices, the inventors proposed to perform synchronization by adjusting the multiplication factor, thereby obtaining an adjusted clock signal from the local master clock, while keeping the actual master clock unchanged and without adjustment.

[0012] The advantage of this method is that one or more clock signals can be adjusted independently. For example, if the slave device includes a master clock and several other clock signals derived from that master clock (for different functions), the proposed method can adjust one or more of these clock signals without affecting any other clock signals. This can be advantageous if other synchronization mechanisms exist, such as time synchronization via communication protocols. Therefore, the proposed method is applicable without affecting other available mechanisms.

[0013] Therefore, the proposed method can compensate for the frequency deviation between the clock signal and the global reference clock without taking into account deviations over time or changes in the local master clock in the device.

[0014] Furthermore, the proposed method can be used in situations where multiple slave devices communicate with a corresponding master device that provides a reference clock.

[0015] In some aspects, the inventors have proposed a method in which a first data packet is received via a wireless communication interface, the first data packet including a first value corresponding to a relative time value derived based on a reference clock. The first data packet including the first value corresponding to the relative time value is typically provided by a master device. Once the first data packet is received, the method includes: triggering a timer to begin counting events based on a clock signal or a local master clock or derived from such a local clock signal. Typically, these events are pulses from one of the aforementioned clocks. Furthermore, the first data packet can be recorded to obtain the first value, and optionally, the first value can be temporarily stored.

[0016] After a period of time, a second data packet is received via the wireless communication interface. The second data packet includes a second value, which corresponds to a relative time derived based on a reference clock provided by the master device. According to the proposed principle, the second value and the first value should be different, and their difference substantially corresponds to the time elapsed since the first and second values, or the first and second data packets, were generated respectively. Once the second data packet is received, the timer is triggered again to store the count of events since the timer was last triggered. In other words, upon receiving the second data packet, the counted number of events is temporarily stored. These events correspond to the time elapsed since the first trigger of the local clock domain. The second data packet can also be decoded to obtain the second value.

[0017] To determine potential time or frequency deviations, the number of events counted between the receipt of the first and second data packets is compared to the difference between a first and a second value. The counted number of events corresponds to the elapsed time in the local clock domain. The difference between the first and second values ​​corresponds to the elapsed time in the reference clock domain. Ideally, the two clock domains should operate in sync, meaning there should be no time delay (positive or negative). Therefore, the frequency and elapsed time given by the counted events should also be the same. Thus, if there is no significant difference between the difference between the first and second values ​​and the counted number of events, it indicates that no frequency deviation has occurred.

[0018] However, if there is a significant discrepancy between the difference between the first and second values ​​and the count event, then it can be assumed that there is a frequency deviation between the reference clock signal and the clock signal. Therefore, the multiplication factor is adjusted according to the obtained frequency deviation to align the clock signal and the reference clock signal accordingly.

[0019] Therefore, the frequency of the clock signal is adjusted to the frequency of the reference clock signal to align the two frequencies.

[0020] In this application, "reference clock signal" and "frequency of reference clock signal" are synonyms. Similarly, throughout the application, the terms "clock signal" and "clock signal frequency" are synonyms.

[0021] The proposed method has the advantage of being independent of any data communication or network protocol and can be used in a variety of applications, including synchronization between typical master-slave configurations. However, it is not limited to simple master-slave communication; it can also synchronize various different clock signals generated by the slave device with a common global reference clock provided by the master device.

[0022] In some respects, the start and end points of each counting event are crucial for reducing inherent errors that may exist during the adjustment process.

[0023] Therefore, even if the data packet has not been fully received, the counting time for the corresponding event can be considered to be triggered very early. In other words, the timer will fire while the data packet is still being received. This is possible if the data packet contains a header or identifier that, upon proper demodulation, will serve as the starting point for the trigger. Typically, this approach is implemented at a very basic hardware level, such as Level 1 or Level 2 in the OSI model. This prevents any potential delays that may occur when processing data packets according to the communication protocol stack or any higher-level protocol.

[0024] Therefore, the step of triggering a timer upon receiving the first or second data packet may include triggering the timer during the receipt of the first or second data packet. More specifically, the timer may be triggered once a sub-part or subset of the first or second data packet is received, demodulated, and identified as part of the first or second data packet. This allows the corresponding timer to count events to be triggered even before the association is fully restricted or the corresponding data packet is received. This may be applicable if the received data packets are quite long, or if the frequency of the event counter is quite high (e.g., within or higher of the received data rate). In other aspects, the timer may be triggered after the first or second data packet is received.

[0025] Several aspects involve packet identification and its alignment with the corresponding slave device. This may be suitable if multiple slave devices need to be synchronized. Therefore, a subset of the first and second packets can be demodulated, and a timer can be triggered in response to a comparison of the demodulated subset with a reference pattern. In other words, the timer is only triggered when a subset in the received packets indicates the correct identifier. This allows event counters in different slave devices to be triggered individually. Conversely, the subset might indicate the slave device to be synchronized or a specific clock within the slave device. Thus, the proposed solution is capable of adjusting various different clock signals in the slave devices, identified by the contents of the first subset.

[0026] On the other hand, the timer can be triggered after the first or second data packet is received, and after these data packets have been fully received and the presence of transmission errors has been evaluated. Of course, if the first and second data packets are not received completely and correctly, the event counter can be reset, and event counting can also be stopped.

[0027] In this respect, the events being counted may correspond to pulses of a clock signal or a signal derived therefrom. Alternatively, these events may correspond to pulses provided by a local master clock located in the slave device. On the other hand, these events may correspond to pulses of the local master clock or a clock signal with an adjustable multiplication factor. Simply put, the number of events counted over a period of time corresponds to the frequency of the corresponding clock signal. Therefore, it can also be said that counting events is equivalent to measuring the frequency of the corresponding clock signal, the local master clock signal, or the signal derived from that local master clock signal.

[0028] As stated above, the proposed method does not rely on any underlying data communication protocol. More specifically, the method can also be used with certain data communication protocols without interfering with or utilizing any of their functions. Therefore, in some aspects, the method can also include receiving one or more data packets according to wireless and packet-oriented communication standards. Wireless and packet-oriented communication standards employ time-division multiplexing, where the communication standard defines time slots for sending or receiving one or more data packets. These time slots can be continuous or spaced out by time intervals during which no data packets are sent or received. Therefore, within such time intervals, data packets can be sent or received according to the proposed principles without interfering with the communication protocol or blocking the transceiver hardware.

[0029] In this regard, for example, a first data packet and a second data packet can be received between time slots designated or scheduled for sending and receiving one or more data packets. However, it is not necessary to receive these data packets in every time slot. Instead, one or more data packets may be sent or received before the first or second data packet is received. In some respects, the sending and / or receiving of the first and second data packets is scheduled at certain time intervals, such as approximately every 500 milliseconds or once per second. In this case, sending and receiving can be scheduled over a period of time during which no sending or receiving is performed according to the communication protocol. This scheduling method also has advantages because it allows the hardware power to be turned off when not needed, thereby reducing the overall power consumption of the slave device.

[0030] Wireless packet communication standards may include, for example, Blue Cruise, Sickly, and the 802.11 standard, although the proposed methods are not limited to these.

[0031] On the other hand, the first and second data packets may each contain a first data subset with a first pattern or bit length, and a second data subset with a second length. The first and second data subsets may each contain values ​​corresponding to different timestamps. Therefore, in some aspects of the proposed principle, different timestamps may correspond to different time periods, such as microseconds or milliseconds, but they may also correspond to and be used to adjust different clock signals in the slave device, which is where the proposed method is used. Furthermore, the first and second lengths may differ. However, in some aspects, at least one bit length may correspond to 10 bits, thus enabling the provision of a count of events between 1 and 1024.

[0032] Some aspects are related to the estimation step, namely obtaining the frequency deviation between the global reference clock and the clock signal to be adjusted.

[0033] Therefore, the step of evaluating the first and second values ​​may include calculating the difference between the second and first values. This difference corresponds to a time interval, more specifically, to the time interval elapsed between the delivery of the first and second data packets from the perspective of a reference clock. The difference can then be compared with stored count events or values ​​derived therefrom to obtain possible time deviations between the global master clock and the reference clock signal, thereby obtaining possible frequency deviations.

[0034] Some aspects relate to adjusting for potential frequency deviations. Situations may arise where the frequency deviation is so small that adjusting the multiplier is either impossible or not worthwhile at the moment. For example, slight fluctuations usually compensate for themselves over time. However, clock signal drift requires compensation because it accumulates over time.

[0035] Therefore, in some respects, the frequency deviation can be compared to a threshold to identify potential drift. For the above comparison, if the frequency deviation is less than the threshold, the multiplication factor can be kept constant. If the frequency deviation is between the threshold and the second threshold, the multiplication factor is adjusted in one step to minimize the frequency deviation between the master reference clock and the clock signal.

[0036] In some cases, the frequency deviation may be quite large, potentially exceeding a certain value, which may be significantly greater than a threshold or even a second threshold. In such situations, adjusting the multiplier factor in a single step may not offer much benefit and could potentially cause interruptions or other adverse effects on slave devices or circuitry using the clock signal during the adjustment process. Therefore, if the frequency deviation exceeds the second threshold, the multiplier factor can be adjusted in multiple smaller steps to minimize any adverse effects on the circuitry while minimizing the deviation. The adjustment may also be performed over a period of time to further reduce any potential adverse effects.

[0037] In some cases, a flag can be set to indicate the presence of frequency deviation. This flag can be set if the deviation is below a threshold. The state of this flag can then be used to extend the measurement time, or to evaluate the deviation over a longer period using longer counts and more data groups. In some cases, for example, a first value can be stored, and a new first value can be used to replace the stored first value, then the counted events can be stored as intermediate counts, thus extending the counting time for the corresponding events. Alternatively, in this case, the event counter can simply continue counting.

[0038] In subsequent steps, the replaced stored first value and the continued counting event are used to evaluate the frequency deviation of the master clock reference and clock signal over a longer time range.

[0039] On the other hand, a transceiver is disclosed. This transceiver includes a local master clock generator for generating a local master clock. The transceiver also includes an adjustable clock generator for generating a clock signal based on an adjustable multiplication factor of the local master clock. This clock signal is used to provide to one or more modules, components, etc., of the transceiver, for example, for recording certain data, such as sound or visual information.

[0040] The transceiver also includes a communication interface configured to receive one or more data packets according to a wireless packet communication standard. This standard may include, but is not limited to, Bluetooth, ZigBee, and 802.11 and their derivatives. The communication interface is also configured to receive a first data packet including a first value corresponding to a relative time value derived from a reference clock. Once the first data packet is received, a timer is triggered to count events originating from a clock signal or a local master clock.

[0041] The communication interface is also configured to receive a second data packet within a certain period after the first data packet is received. The second data packet includes a second value corresponding to a relative time value derived based on a reference clock. Once the second data packet is received, the timer is triggered again, stopping the event counting. The counted events can then be stored in memory, for example, as the number of pulses corresponding to a clock signal or a signal derived from that clock signal. Thus, the counted events refer to the elapsed time between the receipt of the first data packet and the receipt of the second data packet. The first and second data packets can also be decoded and demodulated to obtain the first and second values. The first and second data packets are provided by the master device.

[0042] Based on the proposed principle, the transceiver also includes a control unit configured to detect a frequency deviation between a reference clock and a clock signal based on a first value, a second value, and stored count events. The first and second reference value information are based on a reference clock. The difference between the first and second values ​​corresponds to the time or frequency of the reference clock. As previously stated, the difference between the first and second values ​​and the difference between the count events corresponds to the drift of the reference clock relative to the master clock. The control unit adjusts the frequency multiplication factor based on the detected frequency deviation between the reference clock signal and the clock signal. The adjustment factor does not change the local master clock, but only the clock for which the deviation needs to be minimized.

[0043] In this regard, it should be noted that the communication interface is configured to receive data packets conforming to the communication standard, as well as multiple data packets, which are typically different from data packets that may conform to any proprietary standard. In other words, the first and second data packets do not correspond to the data packets specified by the communication standard. This provides a proprietary data packet generation and reception method independent of the underlying communication standard. More specifically, these data packets do not need to be demodulated and processed exactly according to the communication standard to trigger timers, thereby bypassing any faults or time delays that may be caused by the higher layers of the OSI model during the processing of data packets and packets. Furthermore, processing data packets according to the proposed principles independently of the communication standard can be implemented directly at the underlying hardware.

[0044] The communication interface can be configured to trigger a timer during the reception of a first and second data packet, specifically before all of these data packets have been received. In some respects, the communication interface triggers after a subset of the corresponding first and second data packets has been received. This bypasses delays that may occur during error correction or other processing, allowing for rapid timer triggering largely independent of further processing. Alternatively, a subset of the first and second data packets can be demodulated to derive an identifier from that subset. The timer then triggers based on the identifier, starting an event counter. This allows for adjusting the clock signals of multiple different receivers / slave devices, or adjusting different clock signals within the same receiver / slave device.

[0045] In some respects, communication standards define time slots for sending or receiving one or more data packets. However, the first and second data packets are typically not received during these time slots, but rather between these time slots (i.e., between time slots dedicated to or scheduled for sending or receiving). This ensures that the reception of the first and second data packets does not interfere with the sending or receiving of data packets according to the communication standard. Therefore, the transceiver / slave functionality is unaffected, and the clock signals in the transceiver / slave can be adjusted.

[0046] In some respects, the control unit is configured to detect frequency deviation by calculating the difference between a second value and a first value. This difference corresponds to the time interval between the generation or reception of the corresponding value. If the number of the value itself is associated with or corresponds to the pulses or frequency of a reference clock, then the difference directly corresponds to the time interval of the reference clock. The difference can then be compared with a stored count event or a value derived therefrom. If the difference between the stored count event and the difference between the first and second values ​​is very small, the frequency deviation is also small. In response to this frequency deviation, the multiplication factor can be kept constant or only slightly adjusted. In some respects, if the frequency deviation is large (i.e., exceeds a certain threshold), adjustments can be performed in several small steps to avoid malfunctions in any circuitry using the clock signal.

[0047] Other aspects relate to a transmitter. In some aspects, the transmitter includes a reference clock generator for generating a reference clock. A data packet generator is coupled to the reference clock generator for providing a plurality of subsequent data packets, wherein each data packet includes a value based on or derived from the reference clock. This value corresponds to a timestamp. Therefore, subsequent data packets correspond to the time interval between the generation times of each data packet.

[0048] The transmitter also includes a communication interface configured to send or receive data packets according to a packet-oriented communication standard. The packet-oriented communication standard may be one of Bluetooth, ZigBee, and 802.11 standards or their derivatives. Based on the proposed principles, the transmitter's communication interface is also configured to receive multiple subsequent data packets provided by a data packet generator. Unlike data packets, these data packets may be dedicated packets and may differ in some respects from the data packets used for sending or receiving the data packets.

[0049] The communication interface is configured to transmit data packets from among two or more consecutive data packets between receiving them, according to a packet-oriented communication standard. Alternatively, data packets from among two or more subsequent data packets can be transmitted between sending them, according to a packet-oriented communication standard. Furthermore, the data packets can be transmitted between receiving one data packet and sending another, or between sending and receiving data packets, according to a packet-oriented communication standard. Attached Figure Description

[0050] Further aspects and embodiments based on the proposed principles will become apparent from the various embodiments and examples described in detail with reference to the accompanying drawings, wherein: Figure 1 shows an example of transceiver arrangement in a master-slave configuration to outline some aspects of the proposed principle; Figure 2 shows a flowchart of various data packets and data packages to outline some aspects of the proposed principle; Figure 3 shows a time diagram illustrating several data packets and data packages based on some aspects of the proposed principle; Figure 4 shows the structure of an exemplary data group; Figure 5 illustrates further aspects of the proposed principle; Figure 6 shows a partial example of a transceiver based on some aspects of the proposed principles; Figure 7 shows an example of an exemplary method for synchronizing a clock signal with a reference clock, based on some aspects of the proposed principles; Figure 8 illustrates some aspects of an example method for synchronizing a clock signal with a reference clock based on the proposed principle; Figure 9 illustrates further aspects of an exemplary method for synchronizing a clock signal with a reference clock; Figure 10 illustrates further aspects of an exemplary method for synchronizing a clock signal with a reference clock; Figure 11 shows the time deviation diagram after adjusting the frequency multiplication factor according to certain aspects; Figure 12 shows another time deviation diagram of the clock signal including the correction signal; Figure 13 shows a schematic diagram illustrating an application that can use the proposed method and transceiver. Detailed Implementation

[0051] The following embodiments and examples disclose multiple aspects and combinations thereof based on the proposed principles. These embodiments and examples are not always drawn to scale. Similarly, different elements may be enlarged or reduced to highlight individual aspects. It goes without saying that the various aspects of the embodiments and examples shown in the figures can be arbitrarily combined with each other without departing from the principles of the invention. Some aspects exhibit regular structures or forms. It should be noted that slight differences and deviations from the ideal form may occur in practice, but this does not contradict the inventive concept.

[0052] Furthermore, the dimensions of individual graphics and details may not be entirely accurate, nor may the proportions between elements be perfectly precise. Some aspects may be highlighted by magnification. However, terms such as "above," "above," "below," "under," "larger," and "smaller" are correctly represented in relation to the elements in the drawing. Therefore, such relationships between elements can be inferred from the attached drawing.

[0053] Figure 13 illustrates a typical application in which this method and a transceiver based on the proposed principles can be used. In this particular application, the recording device MD is set up as the master device in a specific spatial environment to record multiple sound signals from multiple sound sources SS1 and SS2.

[0054] Two or more sound sources SS1, SS2 are positioned at a certain distance from the recording device MD, which corresponds to a reference point in terms of location and environment. The two or more sound sources may include conversations between two or more people. Their speech will be recorded; this is called the useful signal. Typically, there will also be other sound sources SS3, such as background voices and other sources emitting sound signals. However, unlike the useful signal, these signals are undesirable and are often referred to as noise. In this respect, one or more sound sources can be stationary, although this is not required by the proposed application. Sound sources may move around or be mobile, and noise sources may also move, thus creating a dynamic sound environment.

[0055] One or more sound sources (or at least some of them), such as loudspeakers, also include a local microphone device that acts as slave devices SD1, SD2. The local microphone devices SD1, SD2 are respectively positioned close to their respective sound sources SS, SS2 and assigned to their respective sound sources.

[0056] Each local microphone device (slave device) and recording device (master device) will now record speech or any other sound signals in the environment. However, due to their varying distances from each other, the microphone devices and recording devices will record the corresponding sound signals from the sound source at different times.

[0057] For example, local microphone device SD1 will first record the sound signal from sound source SS1. Due to the speed of sound, local microphone device SD2 and recording device MD will record their respective sound signals slightly later. The centrally located recording device MD will record sound signals from the two sound sources SS1 and SS2, as well as noise. Similarly, local devices will record the sound signals emitted by the sound sources assigned to them, but will also record speech from other sound sources with a certain delay, or the sound of their own sound reflected in the environment; this phenomenon is called crosstalk. The delay time for recording each sound signal corresponds to the distance from the sound source to the central reference point (e.g., the location of the recording device).

[0058] In subsequent processing, the various audio signals recorded by the local microphone devices LD1 and LD2 and the recording device MD can be combined, for example, to eliminate noise or other imperfections. Furthermore, the distance to the sound source can be calculated by evaluating the delays of the various recorded audio signals. This requires not only a certain degree of correlation (e.g., the audio signals should not be distorted or lost during transmission) but also a thorough understanding of the temporal events recorded by the individual microphone devices LD1, LD2, and the recording device MD. Moreover, all three signals need to be recorded at the same, or at least a defined and known, rate to prevent artifacts and mismatches in subsequent alignment and processing algorithms.

[0059] These problems can typically be addressed in several ways. For example, the corresponding device might include a highly accurate timer or local master clock generator synchronized with a common reference clock. However, such a clock is not readily available in lower-priced devices due to cost considerations. In addition to cost, the clock generator can drift and misalign over time, causing delays or gaps between different clock frequencies across various devices.

[0060] Current methods suggest using the recording device's frequency as the master device's clock frequency and periodically synchronizing the individual clock frequencies of each microphone and slave device. It has been found that synchronizing the clock frequency used in the slave devices to perform certain functions (i.e., actually recording the sound signal) is sufficient. While it's possible to synchronize a local master clock signal, this can also be done without adjustment. This approach is advantageous because it doesn't affect the master clock, which typically provides clock signals for multiple circuits. Therefore, other circuits won't experience any faults that could disrupt the application, and no additional circuitry is needed to correct errors or prevent such interruptions. Furthermore, while the local master clocks in microphone and recording devices are typically synchronized at frequencies of several megahertz, the clock frequency for recording sound signals (or other applications requiring synchronized clocks) is usually lower, for example, in the range of several hundred kilohertz.

[0061] For recording, a clock signal of only a few hundred kHz is sufficient to satisfy the Nyquist criterion and allows for a high sampling rate. Therefore, a frequency deviation of a few milliseconds in the clock frequency can affect the recorded signal, leading to the aforementioned adverse effects. Thus, time synchronization must exceed this value to minimize and reduce its drawbacks.

[0062] Figure 1 illustrates a master-slave configuration according to the present invention, which is suitable for sending and receiving data packets with time synchronization content, allowing the slave device to adjust its clock frequency to a common time reference.

[0063] The transmitter or master device 11 includes one or more antennas 200 and 201 adapted to communicate with the slave device 10 according to one or more wireless communication protocols. The wireless communication protocol is a time-division multiplexing and packet-oriented protocol, meaning that communication is performed by sending or receiving defined data packets using antennas 200 and 201 via a wireless communication interface. Time intervals may occur between the transmission or reception of data packets. Examples of packet-oriented data packets with such time intervals include Bluetooth, ZigBee, and 802.11. The transmitter 11 also includes a corresponding communication interface 101 coupled to antenna 201. Communication interface 101 is connected to a packet generator 170, which generates one or more data packets according to the communication protocol. This enables the master device to communicate with the slave device according to the communication protocol.

[0064] Communication interface 101 is also connected to data packet generator 160 for receiving data packets according to the proposed principles. These data packets are generated by data packet generator 160 using a global reference clock from reference clock generator 150. Reference clock generator 150 provides a signal with a reference clock frequency, which, according to the proposed principles, is synchronized with the clock frequency of the device, more specifically, the device's clock frequency.

[0065] Reference clock generator 150 also provides all necessary clock signals to multiple components of the transmitter. For this purpose, the output 151 of reference clock generator 150 is connected to the clock input of communication interface 101 to provide a clock signal to the communication interface. The reference clock generator is also connected to the input 162 of packet generator 160. Using the reference clock, packet generator 160 provides a first data packet and a second data packet by generating a value corresponding to the reference clock, according to the proposed principles. These data packets are sent to the slave device via the communication interface.

[0066] Device 10 includes two or more antennas 200 connected to a communication controller 502. The communication controller 502 is connected to a control unit 430. The control unit 430, communication controller 502, and antennas constitute the communication interface 100 of transceiver 10. The communication controller 502 is also connected to a control device 501. The control device 501 is connected to a recording device 500, which in turn is connected to an input device 310 (e.g., a microphone). When the transceiver is in operation, the microphone 310 records an audio signal using the recording device 500 and forwards the signal to the control device 501. The recorded audio signal is then transmitted to transmitter 11 via communication controller 502 using a data packet-oriented communication protocol.

[0067] The clock frequency provided by the adjustable clock generator 410 is supplied to the recording device 500. The adjustable clock generator 410 utilizes the local clock signal provided by the local master clock generator 400 and employs an adjustable multiplication factor. Therefore, the clock frequency supplied to the recording device 500 is obtained by changing the multiplication factor or the multiplication factor of the local master clock generator 400. Thus, the clock signal can be adjusted.

[0068] Transceiver 10 also includes a timer or counter 420, whose input is connected to either an adjustable clock generator 410 or a local master clock generator 400. The timer or counter 420 is used to count pulses of one of the clock signals provided by generators 400 and 410, thereby simply measuring their respective frequencies. The timer or counter 420 is controlled by a control device 430.

[0069] Based on the proposed principle, transmitter 11 sends out a first data packet and a second data packet, which are then received by transceiver 10 and used to adjust the multiplication factor of adjustable clock generator 410. This process is shown in Figure 2.

[0070] In this configuration, transceiver 11 acts as the master device and typically communicates with transceiver 10 using a packet-oriented communication protocol. This packet-oriented communication protocol could include, for example, Bluetooth, in which transceiver 11 sends Bluetooth data packets to transceiver 10. Similarly, transceiver 10 records audio signals and transmits the recorded audio signals to transceiver 11 via Bluetooth for further processing.

[0071] Based on the proposed principle, after transceiver 11 identifies transceiver 10 using the Bluetooth communication protocol, it will send a clock synchronization signal, Clksync, to provide a common time reference for transceiver 11 and transceiver 10 when needed. In some respects, the Clksync synchronization signal is used to adjust the local master clock generator within transceiver 10. Furthermore, Clksync will provide a common starting point for transceiver 11 and transceiver 10 for subsequent recording of audio signals.

[0072] In subsequent steps, transceiver 11 and transceiver 10 exchange one or more Bluetooth data packets BP1, BP2, and BPn. For example, transceiver 11 can send multiple Bluetooth data packets to transceiver 10, including settings for subsequent recording sessions. Similarly, transceiver 11 can initiate a recording session by sending a start signal via Bluetooth data packets and a packet-oriented communication protocol. Likewise, transceiver 10 can send multiple Bluetooth data packets to transceiver 11, including recorded audio.

[0073] At some point in time, as shown in the attached document Figure 2Between multiple transmissions of the Bluetooth data packets shown, transceiver 11 sends a data packet DP1 to transceiver 10. This data packet DP1 includes a first value corresponding to a value provided by the packet generator and originating from a signal from the reference clock generator 150 in transceiver 11. When this particular data packet (which does not conform to the Bluetooth standard but is transmitted between Bluetooth data packets) is received, transceiver 10 triggers a timer and counter 420 to count events from the adjustable clock generator or the local master generator. In other words, these counted events correspond to pulses (and thus represent frequencies) of a clock signal in transceiver 10. In subsequent processing steps, the value included in data packet DP1 is acquired and stored as a temporary value VAL1.

[0074] Then, transceiver 10 and transceiver 11 can continue to send and receive one or more data packets BPx according to the Bluetooth standard. Transceiver 11 will send a second data packet DP2 after a certain time T according to the proposed principle, which includes a second value derived from the reference clock generator and its reference clock. This value corresponds to the time elapsed between the first value VAL1 and the second value VAL2, and substantially corresponds to the frequency of the reference clock.

[0075] Upon receiving the second data packet DP2, transceiver 10 stops or restarts timer and counter 410, and stores the events counted so far in temporary memory. The counted events represent or correspond to the frequency of the clock generator or local clock generator in transceiver 10 to some extent. Furthermore, the received second data packet is demodulated to obtain the value VAL2.

[0076] Subsequently, one or more data packets BPy can be sent or received between master device 11 and slave device 10 without processing the contents of the data packets.

[0077] The difference between the two obtained values, VAL1 and VAL2, is now calculated and compared with the count event. This step is, in some way, equivalent to or at least similar to, obtaining the frequency of the signal provided by an adjustable clock generator or a local master clock generator and comparing the obtained frequency with the frequency given by the difference between the two obtained values.

[0078] Ideally, these two results will correspond to each other and roughly indicate that there is no deviation between the clock frequency and the reference clock (neither in frequency nor in time interval). However, if a deviation occurs, the two results will differ from each other, with the sign of the difference indicating the direction of the clock signal offset from the device. Accordingly, in a subsequent step, transceiver 10 now adjusts the multiplication factor of the clock generator to minimize this deviation.

[0079] As previously described, upon receiving the second data packet, the timer or counter restarts. After another specified time period T, another data packet Dp3 is received, triggering the timer to stop counting events, store the event, and restart. The third value VAL3 included in data packet DP3 is obtained by demodulating the data packet. Transceiver 10 then compares the third value VAL3 with the second value VAL2 to obtain a difference representing the reference clock frequency, and compares these differences with newly counted events representing the clock frequency of the local clock in the slave device. Therefore, another possible deviation can be adjusted. After another specified time period, this process can be repeated to periodically adjust the clock frequency deviation and minimize the frequency difference between the reference clock and the local clock.

[0080] The proposed principle is not limited to adjusting a single clock, but can also be used in a variety of different applications.

[0081] For example, Figure 5 illustrates a possible scenario where a master device communicates with multiple slave devices 10A, 10B, and 10C. Identifiers ID1, ID2, and ID3 can be used to distinguish individual data packets. Upon receiving a signal, a slave device demodulates the identifier and triggers the corresponding timer. In this way, each slave device can individually adjust its clock frequency using the identifier header in the data packet. When the correct header is received to begin event counting, the timer is triggered, while data packets with different identifiers are simply ignored.

[0082] As shown in Figure 5, this process can also be implemented in a single slave device, which requires adjusting multiple different clocks and their respective adjustable multipliers. For this purpose, the corresponding identifier does not identify the slave device itself, but rather a dedicated clock or adjustment factor within that specific slave device. Upon receiving the corresponding identifier, a timer for the corresponding clock is triggered to count events.

[0083] As shown in Figure 2, data packets are transmitted between the sending and receiving of one or more Bluetooth data packets (i.e., sending or receiving), or more generally, according to a data packet-oriented communication standard. Figure 3 illustrates a possible embodiment where one or more Bluetooth data packets BPx are sent, each of which may be the same or different in length, as shown. However, the Bluetooth data packets are not sent continuously, but at regular time intervals, during which no sending or receiving occurs between corresponding Bluetooth data packets BPx.

[0084] As shown in Figure 3, certain time intervals on the timeline illustrate this. Bluetooth data packets are transmitted at specific times T, and the length of each packet may vary depending on the data content to be sent or received. However, data packets DP1 and DB2 are sent between time intervals T, especially in the middle of the intervals, during which no transmission or reception occurs. Furthermore, because the content of data packets DP1 and DP2 is finite, their packet length is also finite and does not correspond to the length of Bluetooth data packets. This is also because complex error correction, whether bit correction or block correction, is not possible. Instead, the content of data packets DP1 and DB2 transmitted from the master device to the slave device can be demodulated in a simple way without significant error correction, and then processed at a low hardware level according to the OSI model. Data packets DP1 and DB2 are typically processed at layer 0 or 1 of the OSI model and generally do not extend to higher layers. The advantage of this is that this low-level processing can quickly trigger any hardware counters, thereby reducing overhead and avoiding potential delays or failures caused by processing at higher OSI layers. More specifically, these underlying processes can be performed in real time or near real time without any noticeable delay.

[0085] The data packets being transmitted, DP1 and DB2, may include the bit pattern shown in Figure 4. Each packet contains a header or identifier ID of a specific bit length. The purpose of choosing the bit length is, on the one hand, to enable the demodulator to detect the correct identifier of the packet and distinguish it from noise that may be demodulated. As shown in Figure 5, this identifier can identify one of multiple slave devices. Alternatively, the identifier ID can be used to identify or select a specific clock frequency and multiplication factor to be adjusted in a specific slave device. The identifier may also have no other meaning and be used only to trigger a counter and indicate the reception of a packet. The identifier is usually located at the beginning of the corresponding packet, but it can also be located at the end or in the middle.

[0086] In this example, the data packet contains two additional subsets, referred to as Pattern1 and Pattern2, each with a specific bit length. As shown, both subsets contain the same bit length. These subsets contain values ​​corresponding to events, pulses, or any other characteristics of the reference clock, based on which the clock frequency will be adjusted. For example, subset Pattern1 might include a first value representing the number of milliseconds elapsed since a certain start time. Subset Pattern2 might include time values ​​in microseconds. Therefore, each data packet contains a value composed of the number of milliseconds and microseconds calculated from the reference clock since a certain start time. In this regard, the bit length of subset Pattern2 could be set to 10 bits, corresponding to a maximum value of 1024, meaning one thousand microseconds correspond to one millisecond. Dividing the data packet into two subsets is beneficial for subsequent processing. Furthermore, these two subsets can also be used to adjust different clock signals within the same slave device identified by the identifier ID in the data packet.

[0087] Figure 6 illustrates another embodiment of the transceiver based on the proposed principles. Transceiver 10 includes an antenna section 200 connected to a low-noise amplifier 106. Antenna 200 is configured to receive various signals via a wireless air interface. These signals may correspond to packet-oriented communication protocols such as Bluetooth, ZigBee, 802.11, and similar protocols. Antenna 200 is also configured to receive data packets DP1 and DB2 according to the proposed principles. These data packets do not correspond to data packets defined by the underlying communication protocol. These data packets are demodulated at a low hardware layer, and their contents are processed at that layer to avoid processing at higher layers of the OSI model, thereby avoiding potential latency during processing.

[0088] The antenna 200 of transceiver 10 is connected to a low-noise amplifier 106, the output of which is connected to an IQ demodulator 107. While the current example uses an IQ demodulator 170, other demodulation units such as OFDM demodulators are also applicable. The IQ demodulator includes a local oscillator signal input (not shown), which is coupled to a local master clock oscillator 400. The output of the demodulator is connected to a preprocessing unit 108, which is in turn connected to a memory 109. The preprocessing unit 108 receives multiple clock signals (not shown) from a local master generator. Furthermore, the preprocessing unit is connected to a timer circuit or counter 420 and a comparator unit 601, and also receives data from the local memory 600. The output of the preprocessing unit 108 is connected to the memory 109 for storing the contents of data packets received according to the proposed principles. The output of memory 109 is connected to comparator 431, which in turn is connected to adjustment circuit 433 to provide an adjustment signal at output 433. Possible deviations are adjusted by changing the multiplication factor (not shown) of the clock signal, which is also driven by local master clock generator 400.

[0089] In a possible exemplary operation of the transceiver, data packets are received via antenna 200 and amplified by low-noise amplifier 106. IQ demodulator 107 demodulates the received signal and provides a bit sequence to preprocessing unit 108. The preprocessing unit uses the first bit of the sequence corresponding to a possible header and forwards these bits to comparator 601. Comparator 601 compares the received bit sequence with a stored sequence provided by memory 600, which corresponds to an identification tag. If the bit sequences are not equal, the comparator signals to ignore the remainder of the received message.

[0090] Once correctly identified, comparator 601 triggers timer or counter 420 to start the event counter. Preprocessing unit 108 also receives the corresponding positive identification feedback and continues demodulating the remainder of the received data packet. The remaining bits are stored in temporary memory as a pattern, where each pattern corresponds to a value.

[0091] After a period of time, a new data packet is received via antenna 200. The received signal is amplified and demodulated again by demodulator 17. Preprocessing unit 108 provides the first few bits corresponding to the header to comparator 601, which compares them again with the sequence stored in memory 600 to evaluate the identifier. After correct identification, the content of the received data packet is processed, and a second value is obtained by preprocessing unit 108. This value is stored in memory 109.

[0092] Furthermore, once correctly identified, the comparator triggers timer and counter 420 to stop event counting. By now, the counter has counted the number of pulses of the local reference clock provided by the master clock generator 400 between the two trigger events (i.e., between the receipt of the first and second data packets). The counted pulses are forwarded to comparator 431, which also receives both values ​​from temporary memory 109. These results are compared to estimate the possible time interval or frequency deviation between the received value in the data packet and the counted pulses between the received data packets. Any possible interval or deviation is forwarded to adjustment circuit 433, which adjusts the multiplication factor and provides the adjusted multiplication factor at output 433.

[0093] This process can then be continued or repeated to process another data packet, which is subsequently demodulated, preprocessed, and stored in the memory area. Therefore, when receiving subsequent data packets, potential time or frequency deviations can be estimated (given by the difference between the counting pulse and the value in the received data packet). This will cause the adjustment coefficients to be updated periodically.

[0094] Figure 7 illustrates a possible embodiment of a method for synchronizing a clock signal with a reference clock, wherein the clock signal is derived based on a local master clock and an adjustable correction factor. In step S1, a first data packet is received via a wireless communication interface. The first data packet includes a first value corresponding to a relative time value derived based on a reference clock provided by a master device. Furthermore, once the first data packet is received, in step S2, a timer or counter is triggered to count events or pulses derived based on the clock signal to be adjusted or the local master clock signal, which is derived based on the local master clock signal.

[0095] The method continues with step S3, where the first data packet is fully decoded to obtain a first value, which is then temporarily stored. After a period of time, a second data packet is received via the wireless communication interface. The second data packet includes a second value, which corresponds to a relative time value derived based on a reference clock provided by the master device.

[0096] Receiving the first and second data packets wirelessly often involves using proprietary protocols, rather than adhering to dedicated communication protocols. Notably, it is independent of packet-oriented communication protocols such as ZigBee, Bluetooth, or 802.11, avoiding the need for protocol-based processing, correction, and error handling of these data packets, thus significantly improving the speed of triggering timers. More specifically, the advantage of avoiding bit and block error correction according to complex communication standard protocols is that near real-time processing can be performed at the underlying hardware architecture without using higher layers in the OSI model. In some cases, these higher layers may delay complete decoding and reception, introducing or increasing uncertainty when triggering timers and counters.

[0097] The method then proceeds to step S5, where, upon receiving the second data packet, the timer is triggered again to store the events and pulses counted since the last timer trigger. In other words, the pulses of the clock signal or local master clock signal are counted between two triggered events corresponding to or associated with the frequency of the corresponding clock signal or local master clock.

[0098] In step S6, the second data packet is also fully decoded to obtain the second value. The obtained first and second values ​​are then evaluated and compared with stored count events to obtain the deviation, gap, or difference between these results in step S7. Any possible difference may specifically correspond to the frequency deviation between the clock signal on the slave device and the reference clock on the master device. For such an evaluation deviation between the clock signal and the reference clock, the process either stops and restarts from step S1 or continues to step S8. In step S8, the multiplication factor is adjusted to minimize the deviation. This step can be performed selectively, i.e., only when the frequency deviation exceeds a certain threshold.

[0099] Figure 9 illustrates a possible extension. As shown in Figure 9, step S7 includes comparing the first and second values ​​with stored count events to obtain the frequency deviation. To do this, the difference between the first and second values ​​is first calculated in step S71, which corresponds to the count of the reference clock between the generation of the first and second data packets. This difference is then compared with the counted events in step S72. The result of step S73 is either 0 or close to 0, or contains a sign indicating a forward or backward deviation between the reference clock and the local clock.

[0100] Ideally, if there is no frequency deviation, the count value is the value corresponding to the count event of the clock signal or local master clock, and has a certain correction factor. In this respect, the correction factor itself should be constant and essentially reflect the difference between the frequencies of the reference clock and the clock signal or local master clock in the hardware. Therefore, if there is no gap between the difference between the first and second values ​​and the count event, and it is assumed in step S74 that there is no frequency deviation, the method can continue to step S1.

[0101] However, if a frequency deviation is possible, the process continues as shown in Figure 9, and an evaluation is performed in step S75 to check if the frequency deviation is higher than a second threshold. If this is not the case, meaning the frequency deviation is less than the first threshold, the multiplication factor can be maintained, and certain operations can be performed, such as setting a flag or storing the second value as the first value and replacing the old second value with the new value when a new data packet is received. Similarly, counted events can be stored as an intermediate count and then added to that count. Alternatively, event counting may continue. Some or all of these steps are also performed in step S10, as shown in Figure 10.

[0102] In this way, when re-estimating the first and second values ​​in subsequent steps, the set flag or the stored second value can be used.

[0103] However, if the frequency deviation is between the first threshold and the second threshold (“Y”), the multiplication factor is adjusted in step S8 to minimize the frequency deviation. Finally, if the frequency deviation is greater than the second threshold (“Y’”), the process continues to step S8’. In this step, the adjustment coefficient is adjusted in several incremental steps to minimize the overall frequency deviation. These incremental steps are chosen to avoid and reduce potential faults and errors in the circuitry using the clock signal. This allows recording to continue uninterrupted, for example, because there are no significant jumps in the sampling rate or clock signal.

[0104] Figure 10 illustrates steps S10, S1', and S2', where more additional data packets are received and demodulated and decoded accordingly, the second value is stored as the first value, and the second value is replaced with the new value. Steps S1' and S2' represent one possible way of repeating the method, utilizing previously received data packets. While it is possible to employ an approach where subsequent packets are considered to follow immediately after the first or second packet (i.e., the third packet contains the new first value, the fourth packet contains the new second value, and so on), a more continuous adjustment can also be provided by restarting the counter after the second packet is received (i.e., this means the third packet contains the new second value, while the previous second value becomes the new first value, and so on).

[0105] In the latter case, potential frequency deviations are identified and corrected each time a data packet is received; in the former case, potential frequency deviations are corrected only once every two data packets. If the time interval between data packets is within 500 milliseconds, which is small compared to the possible offset, different options can be selected.

[0106] Figure 11 shows the time deviation of the clock signal over time. As shown, curve C1, representing the frequency deviation on the x-axis, essentially fluctuates around the average value. Curve C2 represents the adjustment factor applied to the frequency multiplication factor to compensate for any frequency deviation that may occur over time. As illustrated in this paper, the overall deviation ranges within tens of microseconds.

[0107] Figure 12 shows a similar graph depicting the deviation of the local clock signal and the corresponding adjustment factor over a time period of approximately 3000 seconds. Curve C1 shows the change in the local clock counter offset over time. The straight line C2 represents the delay between the signal recorded by the local microphone (slave device) and the signal recorded by the reference microphone in the master device. As shown, this delay increases over time due to the frequency drift of the clock signal, if not corrected with the appropriate adjustment factor. Curve C2', marked by a cross, represents the assessed difference. Finally, curve C3 represents the calculated adjustment factor used to compensate for the drift of the local clock signal given by curve C1.

[0108] List of reference numerals 10 transceivers Launcher No. 11 100 communication interfaces 101 communication interface 102 clock inputs 106 amplifier 107 Demodulator 108 Preprocessing 109 memory 103 Data Packet Input 150 Reference Clock Generator 151 output 160 packet generator 161 output 162 Reference Clock Input 170 packet generator 200 and 201 antennas 310 microphone, input device 400 Local Master Clock Generator 410 Adjustable Clock Generator 420 timer 430 control unit 431 comparator 432 Adjustment Circuit 433 Adjustable Output 500 Recording Device 501 Control Device 502 Communication Controller 600ID memory 601 comparator RCLK Reference Clock CLK clock LCLK Local Reference Clock DP1 and DP2 data groups VAL1 and VAL2 values

Claims

1. A method for synchronizing a clock signal (CLK) with a reference clock (RCLK), wherein the clock signal (CLK) is obtained based on a local master clock (LCLK) and an adjustable multiplication factor; the method includes the following steps: A first data packet (DP1) is received via a wireless communication interface (100), the first data packet including a first value, the first value corresponding to a relative time value obtained based on a reference clock (RCLK); Once the first data packet (DP1) is received, a timer (420) is triggered to count events originating from the clock signal (CLK) or the local master clock (LCLK); Decode the first data packet to obtain the first value (VAL1); A second data packet (DP2) is received via a wireless communication interface (100). The second data packet (DP2) includes a second value (VAL2), which corresponds to a relative time value obtained based on a reference clock. Once the second data packet is received, a timer (420) is triggered to store count events since the last time the timer was triggered; Decode the second data packet (DP2) to obtain the second value (VAL2); The first and second values ​​are estimated against the stored count events to obtain the deviation, particularly the frequency deviation between the reference clock and the clock signal (CLK); In response to the frequency deviation between the reference clock and the clock signal (CLK): If the frequency deviation exceeds a threshold, the frequency multiplication factor is adjusted to minimize the frequency deviation.

2. The method according to claim 1, wherein, Once the first data packet and / or the second data packet are received, the steps to trigger the timer include: A timer is triggered during the reception of the first data packet and / or the second data packet, and after the reception of a first subset of the first data packet and / or the second data packet; and / or Demodulate a subset of the first and second data packets, and trigger a timer in response to a comparison result between the subset and a reference mode; or The timer is triggered after the first and / or second data packets are fully received.

3. The method according to any one of the preceding claims, The event corresponds to a pulse of a clock signal; or to a signal obtained based on a clock signal pulse; or The event corresponds to a pulse of the local master clock (LCLK) and an adjustable multiplier.

4. The method according to any one of the preceding claims further includes: According to a wireless, packet-oriented communication standard, particularly one of Bluetooth, Zigbee and 802.11, one or more data packets are sent and received, wherein the communication standard defines time slots for sending or receiving the one or more data packets; in The step of receiving the first data packet and / or the second data packet is performed between time slots dedicated to or scheduled for sending and receiving the one or more data packets.

5. The method according to any one of the preceding claims, wherein, The first data packet and the second data packet each include a first data subset with a first bit length and a second data subset with a second bit length, wherein the first data subset and the second data subset each include values ​​corresponding to different timestamps, specifically one of µs and ms.

6. The method according to claim 5, wherein, The length of the first bit and the length of the second bit are different; and / or where... At least one of the first bit length and the second bit length corresponds to at least 10 bits.

7. The method according to any one of the preceding claims, wherein, The steps for estimating the first and second values ​​include: A difference is formed between the second value and the first value, the difference corresponding to a time interval; The difference is compared with a stored count event or a value derived from the count event.

8. The method according to any one of the preceding claims, wherein, In response to the frequency deviation between the reference clock and the clock signal: The frequency deviation is compared with a threshold. In response to comparing the frequency deviation with a threshold: If the frequency deviation is less than the threshold, the frequency multiplication factor remains unchanged; or If the frequency deviation is between the threshold and the second threshold, then the frequency multiplication factor is adjusted in one step to minimize the frequency deviation; If the frequency deviation is greater than the second threshold, the frequency multiplication factor is adjusted in steps to minimize the frequency deviation.

9. The wireless communication method according to claim 8, further comprising at least one of the following steps: Set a flag to indicate the frequency deviation; Store the second value as the first value and replace the second value with the new value; and / or store the counting event as an intermediate count and add the intermediate count to the newly stored counting event; and In subsequent steps, the first and second values ​​are estimated using the set flag or the second value stored as a replacement and the newly stored count event.

10. A transceiver, comprising: Local master clock generator (400) is used to generate the local master clock (LCLK). An adjustable clock generator (410) is used to generate a clock signal (CLK) based on a local master clock (LCLK) and an adjustable multiplication factor (MF). The communication interface (100) is configured to send and receive data packets according to a data packet-oriented communication standard, particularly one of Bluetooth, Zigbee and 802.11; The communication interface (100) is also configured as follows: Receive a first data packet, the first data packet including a first value, the first value corresponding to a relative time value obtained based on a reference clock (RCLK); Once the first data packet (DP1) is received, a timer (420) is triggered to count events originating from the clock signal (CLK) or the local master clock (LCLK); Decode the first data packet (DP1) to obtain the first value (VAL1). Receive a second data packet (DP2), the second data packet (DP2) includes a second value (VAL2), the second value corresponds to a relative time value obtained based on a reference clock (RCLK); Once the second data packet (DP2) is received, a timer (420) is triggered to store events counted since the last timer was triggered; Decode the second data packet (DP) to obtain the second value (VAL2); The control unit (430) is configured to Based on the first and second values ​​(VAL1, VAL2) and the stored count events, detect the frequency deviation between the reference clock (RCLK) and the clock signal (CLK); In response to the detection of a frequency deviation between the reference clock signal and the clock signal (CLK): Adjust the multiplication factor (MF) to minimize the frequency deviation.

11. The transceiver of claim 10, wherein the communication interface is configured as follows: A timer is triggered during the reception of the first data packet and / or the second data packet, and after the reception of a first subset of the first data packet and / or the second data packet; and / or Demodulate a subset of the first and second data packets, and trigger a timer in response to a comparison result between the subset and a reference mode; or The timer is triggered after the first and / or second data packets are fully received.

12. The transceiver according to any one of claims 9 to 11, wherein, A packet-oriented communication standard defines time slots for sending or receiving one or more data packets; wherein the communication interface is configured as follows: The first data packet and / or the second data packet are received between time slots dedicated to or scheduled for sending or receiving the one or more data packets.

13. The transceiver according to any one of claims 9 to 12, wherein The event corresponds to a pulse of a clock signal; or to a signal obtained based on a clock signal pulse; or The event corresponds to a pulse of the local master clock and an adjustable multiplier.

14. The transceiver according to any one of claims 9 to 13, wherein, The first data packet and the second data packet each include a first data subset having a first bit length and a second data subset having a second bit length, wherein at least one of the first bit length and the second bit length corresponds to at least 10 bits.

15. The transceiver according to any one of claims 9 to 14, wherein the control unit detects the frequency deviation by means of the following steps: A difference is formed between the second value and the first value, the difference corresponding to a time interval; The difference is compared with a stored count event or a value derived from the count event.

16. The transceiver according to any one of claims 9 to 15, wherein, In response to a frequency deviation between the reference clock signal and the clock signal (CLK), the control unit is configured to: The frequency deviation is compared with a threshold. In response to comparing the frequency deviation with a threshold: If the frequency deviation is less than the threshold, the frequency multiplication factor remains unchanged; or If the frequency deviation is between the threshold and the second threshold, then the frequency multiplication factor is adjusted in one step to minimize the frequency deviation; If the frequency deviation is greater than the second threshold, the frequency multiplication factor is adjusted through multiple steps to minimize the frequency deviation.

17. The transceiver according to any one of claims 9 to 15, wherein the control unit is further configured to perform at least one of the following steps: Set a flag to indicate the frequency deviation; Store a first value, replace the new first value with the stored first value, store the counted events as an intermediate count, and add the intermediate count to the newly stored counted events; and Frequency deviations are detected using the set flag or the first value of the replaced storage and the event of the new storage count.

18. A transmitter, comprising: Reference clock generator (150) is used to generate a reference clock (RCLK); A data packet generator (160) is coupled to a reference clock transmitter (150) for providing multiple subsequent data packets (CLKP), each data packet including a value based on or derived from the reference clock and corresponding to a timestamp; The communication interface (101) is configured to send or receive data packets in accordance with a data packet-oriented communication standard, particularly one of Bluetooth, Zigbee and 802.11; The communication interface (101) is configured as follows: Receive multiple subsequent data packets provided by the data packet generator; and Send one of the plurality of data packets between one of the following items: Receive two consecutive data packets according to the data packet-oriented communication standard; Send two consecutive data packets according to the packet-oriented communication standard; or Receive and send data packets according to data packet-oriented communication standards; and Send and receive data packets according to data packet-oriented communication standards.

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