Pixel sensor array

Abstract

The utility model provides a pixel sensor array. The pixel sensor array comprises a photodiode in a substrate, a deep trench isolation structure laterally surrounding the photodiode in the substrate, a diffusion structure in a recess in the substrate, and a doped implantation region in the substrate. The deep trench isolation structure includes a conformal liner, a dielectric layer over the conformal liner, and an elongated metal insert in the dielectric layer. A diffusion structure is over the photodiode and within an inner perimeter of the deep trench isolation structure, and a doped implant region is between the photodiode and the diffusion structure. The diffusion structure can be formed to distribute incident light for a particular optical wavelength and / or a wider range of optical bandwidths, which can improve the quantum effect of the pixel sensor.

Description

Technical Field

[0001] Embodiments of this utility model relate to a semiconductor structure, and more particularly to a pixel sensor array. Background Technology

[0002] Complementary metal-oxide-semiconductor (CMOS) image sensors use photosensitive CMOS circuits to convert light energy (such as photons) into electrical energy. The photosensitive CMOS circuits may include photodiodes formed in a silicon substrate. When a photodiode is exposed to light, a charge (called photocurrent) is induced in it. The photodiode can be coupled to a switching transistor, which samples the charge in the photodiode. Color can be determined by placing a filter on top of the photosensitive CMOS circuit. Utility Model Content

[0003] Embodiments of this utility model provide a pixel sensor array including a photodiode in a substrate, a deep trench isolation structure laterally surrounding the photodiode in the substrate, a diffusion structure in a recess in the substrate, and a doped implantation region in the substrate. The deep trench isolation structure includes a conformal liner, a dielectric layer above the conformal liner, and an elongated metal insert in the dielectric layer. The diffusion structure is above the photodiode and within the inner perimeter of the deep trench isolation structure, and the doped implantation region is between the photodiode and the diffusion structure.

[0004] Based on the above, embodiments of this invention form a metal insert after forming the diffusion structure to prevent the material of the metal insert from limiting the size and / or shape of the diffusion structure, which provides greater manufacturing flexibility when forming the diffusion structure. This greater flexibility in selecting the size and / or shape of the diffusion structure allows it to be formed to distribute incident light for a specific optical wavelength and / or a wider range of optical bandwidths. This can improve the quantum effect of the pixel sensor. Additionally and / or alternatively, forming the metal insert by planarization instead of etching allows the use of metals with high reflectivity for the metal insert. This can improve the reflectivity of the deep trench isolation structure, which can enhance the optical isolation provided by the deep trench isolation structure. Furthermore, completely filling the recess with a dielectric material results in fewer semiconductor processing operations compared to partially filling the recess with a dielectric layer and then completely filling it after forming the metal insert, which can reduce the cost, complexity, and / or time required to manufacture the pixel sensor.

[0005] To make the above features and advantages of the embodiments of this utility model more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0006] Figure 1 This is a diagram of an example of the pixel sensor described in this article.

[0007] Figure 2A-2C This is a diagram of an example of the image sensor device described herein.

[0008] Figures 3A-3E This is a diagram of an example of a pixel sensor that may be included in the pixel sensor array of the image sensor device described herein.

[0009] Figures 4A-4E This is a diagram of an example of a pixel sensor that may be included in the pixel sensor array of the image sensor device described herein.

[0010] Figures 5A-5E This is a diagram illustrating an exemplary embodiment of the circuit die (or a portion thereof) described herein.

[0011] Figures 6A-6F This is a diagram illustrating an exemplary embodiment of the sensor die (or a portion thereof) described herein.

[0012] Figure 7A and Figure 7B This is a diagram illustrating an exemplary embodiment of the image sensor device (or a portion thereof) described herein.

[0013] Figure 8A-8I This is a diagram of an exemplary embodiment of a pixel sensor array forming the sensor die (or a portion thereof) described herein.

[0014] Figure 9A-9I This is a diagram of an exemplary embodiment of a pixel sensor array forming the sensor die (or a portion thereof) described herein.

[0015] Figure 10 This is a flowchart of an example process related to forming the pixel sensor array described herein.

[0016] Figure 11 This is a flowchart of an example process related to forming the pixel sensor array described herein. Detailed Implementation

[0017] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to limit the scope of this disclosure. For example, in the following description, the first feature being formed "on" or "on" a second feature may include embodiments where the first and second features are formed in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features are not in direct contact. Furthermore, component numbers and / or letters may be repeated in various examples of this disclosure. Such repetition is for simplification and clarity of description of this disclosure, and is not intended to limit the relationship between various embodiments and / or configurations.

[0018] Furthermore, for ease of explanation, spatially relative terms such as "below," "under," "lower," "above," and "upper" may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. In addition to the orientations depicted in the figures, these spatially relative terms also cover different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used therein can be interpreted in the same manner.

[0019] In some cases, a diffusion structure (also known as a high absorption (HA) structure) can be incorporated between the photodiode and microlens of a pixel sensor. The diffusion structure distributes incident light across the photodiode to reduce the likelihood of optical saturation in specific regions of the photodiode, which can improve the quantum efficiency (QE) of the pixel sensor. However, the size and / or shape of the diffusion structure can be limited by the type of material incorporated into the pixel sensor and the surrounding structures. For example, a metal insert can be formed in a deep trench isolation (DTI) structure that laterally surrounds the photodiode, and the etching of the metal layer used to form the metal insert can limit the width and / or depth at which the diffusion structure can be formed. Specifically, if a recess is formed for a large diffusion structure and a metal layer is formed within the recess, the dielectric layer of the diffusion structure on which the metal layer is formed within the recess may be damaged by etching the metal layer due to variations in the thickness of the metal layer caused by the size of the recess. This can limit the ability of the diffusion structure to distribute specific wavelengths of light, potentially resulting in a lower QE for the pixel sensor. Furthermore, because the metal layer is etched to form the metal insert, some metals with high reflectivity (such as copper) are not suitable for use as metal inserts, as etching these metals is impractical.

[0020] In some embodiments described herein, a metal insert is formed within a DTI structure that laterally surrounds the photodiode of a pixel sensor, and instead of etching a metal layer to form the metal insert, the metal insert is formed by forming and planarizing the metal layer. Instead of partially filling the recess with a dielectric layer and then forming a metal layer on top of the dielectric layer, a recess for the diffusion structure is formed and then completely filled with a dielectric material. In this way, the diffusion structure has a substantially flat top surface on which the metal layer is then formed, allowing the metal layer to be planarized rather than etched to form the metal insert.

[0021] Forming a metal insert after the diffusion structure prevents the material of the metal insert from limiting the size and / or shape of the diffusion structure, providing greater manufacturing flexibility during diffusion structure formation. This greater flexibility in choosing the size and / or shape of the diffusion structure allows it to be formed to distribute incident light with optical bandwidths for specific optical wavelengths and / or a wider range. This improves the QE of the pixel sensor. Additionally and / or alternatively, forming the metal insert by planarization instead of etching allows the use of metals with high reflectivity (e.g., copper) for the metal insert. This improves the reflectivity of the DTI structure, which enhances the optical isolation provided by the DTI structure. Furthermore, completely filling the recess with a dielectric material results in fewer semiconductor processing operations compared to partially filling the recess with a dielectric layer and then completely filling it after forming the metal insert, which reduces the cost, complexity, and / or time required to manufacture the pixel sensor.

[0022] Figure 1 This is an example diagram of the pixel sensor 100 described herein. The pixel sensor 100 may include a front-side pixel sensor (e.g., a pixel sensor configured to receive photons of light from the front side of a sensor die), a rear-side pixel sensor (e.g., a pixel sensor configured to receive photons of light from the back side of a sensor die), and / or other types of pixel sensors. The pixel sensor 100 may be electrically connected to a supply voltage (V). dd 102 and electrical grounding 104.

[0023] The pixel sensor 100 includes a sensing area 106 configured to sense and / or accumulate incident light (e.g., light rays directed towards the pixel sensor 100). The pixel sensor 100 also includes a control circuitry area 108. The control circuitry area 108 is electrically connected to the sensing area 106 and configured to receive a photocurrent 110 generated by the sensing area 106. Furthermore, the control circuitry area 108 is configured to transmit the photocurrent 110 from the sensing area 106 to downstream circuitry, such as an amplifier or an analog-to-digital (AD) converter, or other examples.

[0024] Sensing area 106 includes a photodiode 112. The photodiode 112 absorbs and accumulates photons of incident light and generates a photocurrent 110 based on the absorbed photons. The magnitude of the photocurrent 110 is based on the amount of light collected in the photodiode 112. Therefore, the accumulation of photons in the photodiode 112 produces a charge accumulation representing the intensity or brightness of the incident light (e.g., a larger amount of charge corresponds to a larger intensity or brightness, and a smaller amount of charge corresponds to a smaller intensity or brightness).

[0025] Photodiode 112 is electrically connected to the source of transfer gate 114 in control circuit region 108. Transfer gate 114 is configured to control the transmission of photocurrent 110 from photodiode 112. Based on selectively switching the gate of transfer gate 114, photocurrent 110 is supplied from the source of transfer gate 114 to the drain of transfer gate 114. This can be achieved by adjusting the transfer voltage (V... tx A transmission voltage 116 is applied to the transmission gate 114 to selectively switch the gate of the transmission gate 114. In some embodiments, applying the transmission voltage 116 to the transmission gate 114 causes a conductive path to be formed between the source and drain of the transmission gate 114, allowing the photocurrent 110 to move along the conductive path from the source to the drain. In some embodiments, removing the transmission voltage 116 from the transmission gate 114 (or the absence of the transmission voltage 116) causes the conductive path to be removed, preventing the photocurrent 110 from flowing from the source to the drain.

[0026] The control circuit region 108 also includes a reset gate 118. The reset gate 118 is electrically connected to the supply voltage 102. The reset gate 118 can be powered by a reset voltage (V). rst )120 control. The transfer gate 114 and the reset gate 118 may be electrically coupled to the floating diffusion node 122. The reset voltage 120 may be applied to the reset gate 118 to pull the drain of the transfer gate 114 to a high voltage (e.g., to the supply voltage 102) to "reset" the floating diffusion node 122 (e.g., by draining any residual charge in the floating diffusion node 122) before activating the transfer gate 114 to transfer the photocurrent 110 from the photodiode 112 to the floating diffusion node 122.

[0027] Photocurrent 110 can be used to adjust the floating diffusion voltage (V) fd The source follower gate 124 is applied to the control circuit region 108. This allows the photocurrent 110 to be observed without removing or discharging the photocurrent 110 from the floating diffusion node 122. The reset gate 118 can alternatively be used to remove or discharge the photocurrent 110 from the floating diffusion node 122.

[0028] The source follower gate 124 is used as a high-impedance amplifier for the pixel sensor 100. The source follower gate 124 provides voltage-to-current conversion for the floating diffusion voltage. The output of the source follower gate 124 is electrically connected to a column select gate 126, which is configured to control the flow of photocurrent 110 to external circuitry. This is achieved by selectively applying a selection voltage (V... di A photocurrent 110 is applied to the gate of column select gate 126 to control column select gate 126. This allows photocurrent 110 to flow to the output 130 of pixel sensor 100.

[0029] As mentioned above, providing Figure 1 As an example. Other examples can be found with... Figure 1 The descriptions are different.

[0030] Figure 2A-2C This is a figure of example 200 of the image sensor device described herein. Figure 2A As shown, an image sensor device can be formed by bonding a circuit die 202 and a sensor die 204. For example, a bonding machine can be used to perform bonding operations to bond the circuit die 202 and the sensor die 204 using metal-to-metal bonding, dielectric-to-dielectric bonding, and / or other bonding techniques. In the bonding operation, a circuit die 206 on the circuit die 202 is bonded to a corresponding sensor die 208 on the sensor die 204 to form an image sensor device 210. The image sensor device 210 is then diced and packaged. Other processing steps may be performed to form the image sensor device 210.

[0031] Each image sensor device 210 includes a circuit die 206 and a sensor die 208. The circuit die 206 and the sensor die 208 may be stacked or arranged vertically in the image sensor device 210. The sensor die 208 includes a pixel sensor array, which includes a plurality of pixel sensors 100 or a plurality of portions of a plurality of pixel sensors 100. Specifically, the pixel sensor array includes at least the sensing area 106 of the pixel sensor 100 (and therefore includes a photodiode 112). Thus, the sensor die 208 is primarily configured to sense photons of incident light and convert the photons into a photocurrent 110.

[0032] Circuit die 206 includes circuitry configured to measure, manipulate, and / or otherwise utilize the photocurrent 110. Furthermore, circuit die 206 includes at least a subset of transistors from the control circuitry region 108 of the pixel sensor 100. For example, circuit die 206 may include the column select gate 126 of the pixel sensor 100, the source follower gate 124 of the pixel sensor, and / or combinations thereof. This provides a larger area for the photodiode 112 on the sensor die 208, allowing the size of the photodiode 112 to be increased to improve the sensitivity and / or overall performance of the pixel sensor's light sensing capabilities and / or to allow the size of the pixel sensor 100 to be reduced while maintaining the same size for the photodiode 112.

[0033] like Figure 2A As further shown, circuit die 206 may include a device layer 212 and an interconnect layer 214. Device layer 212 may include devices of circuit die 206 (e.g., transistors), and interconnect layer 214 may include interconnects that enable the supply of signals and / or power to and / or from devices in device layer 212. Sensor die 208 may also include a device layer 216 and an interconnect layer 218. Device layer 216 may include multiple portions of pixel sensor 100, including photodiode 112, transmission gate 114, and floating diffusion node 122, among other examples. Interconnect layer 218 may include interconnects that enable the supply of signals and / or power to and / or from devices in device layer 216.

[0034] The circuit die 206 and the sensor die 208 may be joined at a bonding interface 220, which may be contained between and / or within a portion of the interconnect layers 214 and / or 218. The bonding interface 220 may include bonding pads, bonding vias, bonding dielectric layers, and / or other bonding structures.

[0035] Figure 2B This is a top view of an exemplary pixel sensor array 222 contained on sensor die 208. The pixel sensor array 222 may be contained on sensor die 208 of image sensor device 210. Figure 2B As shown, the pixel sensor array 222 may include a plurality of pixel sensors 100 (or a plurality of portions of the plurality of pixel sensors 100). For example, the pixel sensor array 222 may include photodiodes 112 of the pixel sensors 100. Figure 2B As further shown, the pixel sensors 100 can be arranged in a grid. In some embodiments, the pixel sensors 100 are square (e.g., Figure 2B(As shown in the example). In some embodiments, the pixel sensor 100 includes other shapes, such as rectangular, circular, octagonal, rhomboid and / or other shapes.

[0036] In some embodiments, the size (e.g., width or diameter) of pixel sensor 100 is approximately 1 micrometer. In some embodiments, the size (e.g., width or diameter) of pixel sensor 100 is less than approximately 1 micrometer. For example, one or more widths of pixel sensor 100 may include a range from approximately 0.6 micrometers to approximately 0.7 micrometers. In these examples, pixel sensor 100 may be referred to as a submicron pixel sensor. Submicron pixel sensors can reduce the spacing (e.g., the distance between adjacent pixel sensors) of pixel sensors in pixel sensor array 222, which can increase the pixel sensor density in pixel sensor array 222 (which can improve the efficiency of pixel sensor array 222). However, other values ​​in the size range of pixel sensor 100 are also within the scope of this disclosure.

[0037] Each pixel sensor 100 may be configured to sense a specific wavelength range of incident light associated with a specific color component of the incident light. For example, pixel sensor 100 may be configured to sense a wavelength range associated with the red component of the incident light, and thus may be referred to as a red pixel sensor. As another example, pixel sensor 100 may be configured to sense a wavelength range associated with the blue component of the incident light, and thus may be referred to as a blue pixel sensor. As another example, pixel sensor 100 may be configured to sense a wavelength range associated with the green component of the incident light, and thus may be referred to as a green pixel sensor. In some embodiments, multiple pixel sensors 100 are configured to sense a wavelength range associated with the near-infrared (NIR) component of the incident light, and thus may be referred to as NIR pixel sensors. NIR pixel sensors may be included in pixel sensor array 222 to improve the low-light performance of image sensor device 210 and / or enable image sensor device 210 to achieve night vision functionality.

[0038] like Figure 2B As further shown, the pixel sensor 100 can be electrically and optically isolated via a DTI structure 224 included in the pixel sensor array 222. The DTI structure 224 may include a plurality of interconnected and intersecting trenches in a substrate, the trenches being filled with one or more types of materials, such as dielectric materials, metallic materials, and / or other types of materials. The trenches of the DTI structure 224 may be included around the periphery of the pixel sensor 100, such that the DTI structure 224 forms an isolation grid surrounding the photodiodes 112 of the pixel sensor 100, as... Figure 2B As shown.

[0039] Figure 2CA cross-sectional view of the image sensor device 210 is shown. (As shown) Figure 2C As shown, the circuit die 206 and the sensor die 208 can be joined at the interface 220, such that the circuit die 206 and the sensor die 208 are stacked or arranged vertically in the z-direction of the image sensor device 210. Figure 2C As further shown, the image sensor device 210 includes a pixel sensor array 222 (e.g., including pixel sensor 100), a black level correction (BLC) region 226 adjacent to (e.g., horizontally adjacent) the pixel sensor array 222, a bonding pad region 228 adjacent to (e.g., horizontally adjacent) the BLC region 226, and a sealing ring region 230 adjacent to (e.g., horizontally adjacent) the bonding pad region 228, among other examples.

[0040] like Figure 2C As further shown, the image sensor device 210 includes multiple layers, such as device layer 212 and interconnect layer 214 of circuit die 206, and device layer 216 and interconnect layer 218 of sensor die 208. Device layer 212 of circuit die 206 includes a substrate 232 and a dielectric layer 234 above the substrate 232. The substrate 232 may include silicon (Si) (e.g., a silicon substrate), a material including silicon, III-V compound semiconductor materials (e.g., gallium arsenide (GaAs)), silicon on insulator (SOI), or other types of semiconductor materials. The substrate 232 may include a semiconductor layer, such as a silicon layer. The dielectric layer 234 may include one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y Other examples include silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silica glass (FSG), and / or carbon-doped silicon oxide.

[0041] Device 236 may be contained within and / or on the substrate 232 of device layer 212. Device 236 may include one or more application-specific integrated circuit (ASIC) devices, one or more system-on-chip (SOC) devices, one or more transistors, and / or one or more other components configured to measure the magnitude of photocurrent 110 generated by pixel sensor 100 to determine the intensity of incident light and / or generate images and / or video (e.g., digital images, digital video).

[0042] The interconnect layer 214 of the circuit die 206 may include a dielectric layer 238, a bonding layer 240, a plurality of interconnect structures 242 in the dielectric layer 238, and a plurality of bonding structures 244 in the bonding layer 240. The dielectric layer 238 may include one or more interlayer dielectric (ILD) layers, one or more intermetallic dielectric (IMD) layers, and / or one or more etch stop layers (ESL), among other examples. The dielectric layer 238 and the bonding layer 240 may each include one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y Other examples include silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorinated silicate glass (FSG), and / or carbon-doped silicon oxide.

[0043] Interconnect structures 242 may each include wires, channels, vias, interconnects, metallization layers, and / or other types of electrically conductive structures that electrically connect device 236 to one or more other areas of circuit die 206 and / or to one or more areas of sensor die 208, etc. Bonding structures 244 may each include bonding pads, bonding vias, and / or other types of bonding structures. Interconnect structures 242 and bonding structures 244 may each include one or more electrically conductive materials, such as electrically conductive metals, electrically conductive metal alloys, electrically conductive ceramics, tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), and / or gold (Au), etc., etc.

[0044] The device layer 216 of the sensor die 208 includes a substrate 246 and a dielectric layer 248 beneath the substrate 246. The substrate 246 may include silicon (Si) (e.g., a silicon substrate), a silicon layer or other types of semiconductor layers, including silicon, III-V compound semiconductor materials (e.g., gallium arsenide (GaAs)), SOI, or other types of semiconductor materials. The dielectric layer 248 may include one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y Other examples include silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorinated silicate glass (FSG), and / or carbon-doped silicon oxide.

[0045] The photodiode 112 of the pixel sensor 100 is contained within a substrate 246 of the sensor die 208. Each photodiode 112 may include one or more doped regions of the substrate 246. The substrate 246 may be doped with multiple types of ions to form PN or PIN junctions corresponding to the photodiode 112 (e.g., junctions between p-type, intrinsic (or undoped) type, and n-type portions). For example, the substrate 246 may be doped with an n-type dopant to form a first portion (e.g., an n-type portion) of the photodiode 112 and a p-type dopant to form a second portion (e.g., a p-type portion) of the photodiode 112. The photodiode 112 may be configured to absorb photons of incident light. The absorption of photons causes the photodiode 112 to accumulate charge (photocurrent 110) due to the photoelectric effect. Here, photons bombard the photodiode 112, causing the emission of electrons from the photodiode 112. The emission of electrons leads to the formation of electron-hole pairs, in which electrons migrate toward the cathode of photodiode 112 and holes migrate toward the anode, thereby generating photocurrent 110.

[0046] Photodiode 112 may be electrically and / or optically isolated from each other via one or more isolation structures in substrate 246. Shallow trench isolation (STI) structure 250 extends from the bottom side of substrate 246 (referred to as the front side of substrate 246) into substrate 246, and DTI structure 224 extends from the top side of substrate 246 (referred to as the back side of substrate 246) above STI structure 250 into substrate 246. The combination of STI structure 250 and DTI structure 224 in substrate 246 laterally surrounds pixel sensor 100 in substrate 246 and provides electrical and / or optical isolation for pixel sensor 100 in substrate 246.

[0047] The DTI structure 224 may include an elongated structure comprising a dielectric layer 252 and a dielectric liner 254 between a substrate 246 and the dielectric layer 252. The dielectric liner 254 may be a conformal liner contained on the sidewalls and bottom surface of the DTI structure 224 and conforming to the contours of the sidewalls and bottom surface of the DTI structure 224. The dielectric liner may be included as an antireflective coating (ARC) to passivate the substrate 246 near the DTI structure 224 and / or further promote electrical and / or optical isolation of the pixel sensor 100. The DTI structure 224 also includes an elongated metal insert 256 extending into the dielectric layer 252 and providing enhanced reflectivity to the DTI structure 224. Instead of photons being absorbed in the DTI structure 224, the metal insert 256 increases the reflection of incident light photons leaving the DTI structure 224 and toward the photodiode 112 of the pixel sensor 100, which may increase the QE of the pixel sensor 100. Additionally and / or alternatively, the metal insert 256 may be electrically biased to increase the density of positive charge (e.g., hole density) around the photodiode 112.

[0048] STI structure 250 may include one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y Other examples include silicon oxide (SiON) and / or silicon oxynitride (SiON). The dielectric layer 252 of the DTI structure 224 may include silicon oxide (SiO2) and / or silicon oxynitride (SiON). x Examples of dielectric materials include, for example, SiO2), phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorinated silicate glass (FSG), other low-k dielectric materials having a dielectric constant of 3.9 or less, and / or other dielectric materials. In some embodiments, the dielectric liner 254 may include a high-k dielectric material, such as silicon nitride (SiO2), phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorinated silicate glass (FSG), other low-k dielectric materials having a dielectric constant of 3.9 or less, and / or other dielectric materials. x N y For example, Si3N4), hafnium oxide (HfO) x For example, HfO2), aluminum oxide (Al) x O y (e.g., Al3O4) and / or other materials.

[0049] The metal insert 256 comprises one or more metallic materials and / or one or more metallic materials with high optical reflectivity. Examples of such materials include copper (Cu), tungsten (W), titanium (Ti), aluminum (Al), gold (Au), silver (Ag), platinum (Pt), and / or zinc (Sn), among others. In some embodiments, the metal used for the metal insert 256 may be based on the operating wavelength or operating wavelength range of the incident light of the pixel sensor array 222. For example, if the pixel sensor array 222 is to be used in a low-light application in the pixel sensor 100 to detect incident light in the infrared or NIR wavelength range, copper, gold, or other metals with high reflectivity to NIR light may be used. As another example, if the pixel sensor 100 is to detect incident light in the visible light wavelength range, silver, aluminum, or other metals with high reflectivity to visible light may be used.

[0050] like Figure 2C As further shown, a diffusion structure 258 may be included on the photodiode 112 of the pixel sensor 100. The diffusion structure 258 is included to diffuse or scatter photons of incident light into the substrate 246, allowing the photons to travel a longer path to reach the photodiode 112. A longer path provides more opportunities for the photons to be absorbed in the photodiode 112, thereby increasing the probability of photon absorption. This improves the quantization QE of the pixel sensor 100.

[0051] The diffusion structure 258 may be located within the periphery of the DTI structure 224 in a top view of the pixel sensor array 222, and between opposing portions of the DTI structure 224 on opposite sides of the photodiode 112 in a cross-sectional view of the pixel sensor array 222. The diffusion structure 258 comprises a dielectric material contained within a recess in the substrate 246 above the photodiode 112. Therefore, the diffusion structure 258 extends into the substrate 246. Since the recess in the substrate 246 has angled sidewalls, the bottom surface of the diffusion structure 258 may have a V-shaped cross-sectional profile. Alternatively, the bottom surface of the diffusion structure 258 may have circular sidewalls. The sidewalls forming the recess of the diffusion structure 258 cause the path of photons entering the substrate 246 to be altered by diffraction at the interface between the diffusion structure 258 and the substrate 246. The top surface of the diffusion structure 258 may be substantially flat. The dielectric material of the diffusion structure 258 may be merged across adjacent diffusion structures 258.

[0052] The DTI structure 224 and the diffusion structure 258 are contained in the back side of the substrate 246. The transmission gate 114 of the pixel sensor 100 is contained on the front side of the substrate 246, and the dielectric layer 248 is contained on the transmission gate 114. The transmission gate 114 is electrically connected to the interconnect layer 218, which allows an input (e.g., a gate voltage) to be provided to the transmission gate 114 to control the flow of photocurrent 110 from the photodiode 112 to the floating diffusion node 122 (not shown) of the pixel sensor 100.

[0053] The interconnect layer 218 may include a dielectric layer 260, a bonding layer 262, a plurality of interconnect structures 264 in the dielectric layer 260, and a plurality of bonding structures 266 in the bonding layer 262. The dielectric layer 260 may include one or more ILD layers, one or more IMD layers, and / or one or more ESL layers, or other examples. The dielectric layer 260 and the bonding layer 262 may each include one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y Other examples include silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorinated silicate glass (FSG), and / or carbon-doped silicon oxide.

[0054] Interconnect structures 264 may each include wires, trenches, vias, interconnects, metallization layers, and / or other types of electrically conductive structures that electrically connect the transmission gate 114 to one or more other regions of the sensor die 208 and / or to one or more regions of the circuit die 206, etc. Bonding structures 266 may each include bonding pads, bonding vias, and / or other types of bonding structures. Interconnect structures 264 and bonding structures 266 may each include one or more electrically conductive materials, such as electrically conductive metals, electrically conductive metal alloys, electrically conductive ceramics, tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), and / or gold (Au), etc., etc., etc.

[0055] At the bonding interface 220, bonding layers 240 and 262 may be bonded together (e.g., in the form of dielectric to dielectric bonding), and bonding structures 244 and 266 may be bonded together (e.g., in the form of metal to metal bonding). Signals and / or power may be provided between circuit die 206 and sensor die 208 via bonding structures 244 and 266.

[0056] On the top side of substrate 246, passivation layer 268 may be contained on DTI structure 224 and diffusion structure 258, and metal mesh structure 270 may be contained on passivation layer 268. Passivation layer 268 may include oxide material, such as silicon oxide (SiO2). x Additionally and / or alternatively, silicon nitride (SiN) x ), silicon carbide (SiC) x (or mixtures thereof, such as silicon carbonitride (SiCN), silicon oxynitride (SiON) or other dielectric materials, are used for passivation layer 268.

[0057] A portion of the metal mesh structure 270 may be located above the DTI structure 224 and may be formed around the photodiode 112 of the pixel sensor 100. Openings in the metal mesh structure 270 are included above the photodiode 112, allowing incident light to pass through the metal mesh structure 270 and reach the photodiode 112. The metal mesh structure 270 may be formed from metallic materials (e.g., gold (Au), copper (Cu), silver (Ag), cobalt (Co), tungsten (W), titanium (Ti), ruthenium (Ru), metal alloys (e.g., aluminum-copper (AlCu)) and / or combinations thereof, and other examples).

[0058] A color filter region 272 of the pixel sensor 100 is contained within an opening in the metal mesh structure 270. The color filter region 272 may be contained above a photodiode 112 of the pixel sensor 100. Each color filter region 272 may be configured to filter incident light to allow a specific wavelength of the incident light to reach the photodiode 112. For example, the color filter region 272 may filter incident light to allow red light to pass through the color filter region 272 to reach the associated photodiode 112. As another example, the color filter region 272 may filter incident light to allow green light to pass through the color filter region 272 to reach the associated photodiode 112. As another example, the color filter region 272 may filter incident light to allow blue light to pass through the color filter region 272 to reach the associated photodiode 112. In some embodiments, the color filter region 272 may be non-discriminatory or non-filtering, which may define a white pixel sensor. Non-discriminative or non-filtering color filter region 272 may include a material that allows light of all wavelengths to enter the associated photodiode 112 (e.g., for the purpose of determining overall brightness to increase the light sensitivity of the image sensor). In some embodiments, color filter region 272 may be an NIR bandpass color filter region 272, which may define an NIR pixel sensor. NIR bandpass color filter region 272 may include a material that allows a portion of incident light in the NIR wavelength range to pass to the associated photodiode 112 while blocking visible light from passing through.

[0059] Microlens 274 may be included on and / or on color filter area 272. Microlens 274 may include a corresponding microlens for each pixel sensor 100. Microlenses may be configured to focus incident light onto the photodiode 112 of the associated pixel sensor 100.

[0060] like Figure 2C As further shown, a metal layer 276 may be included on the substrate 246 within the BLC region 226 of the substrate 246. The metal layer 276 may serve as a light-blocking layer to prevent incident light from entering a portion of the substrate 246 within the BLC region 226. Therefore, the portion of the substrate 246 within the BLC region 226 is a sensing area that remains “dark” so that dark current measurements can be performed within the BLC region 226. Dark current measurements can be performed to measure the amount of charge (dark current) generated in the substrate 246 by sources other than incident light (e.g., thermal energy from the substrate 246), and thus, dark current measurements can be used for black level correction (or black level calibration) of the pixel sensor array 222.

[0061] like Figure 2C As further shown, the bonding pad region 228 may include multiple dielectric layers 278, 280, 282, and 284 of the electrically isolating bonding pad structure 286. The bonding pad structure 286 is electrically coupled and / or physically coupled to one or more interconnect structures 264 in the interconnect layer 218 of the sensor die 208. A bonding pad opening 288 is included on the bonding pad structure 286, enabling the formation of external electrical connections to the bonding pad structure 286.

[0062] The plurality of dielectric layers 278, 280, 282 and 284 may each include one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y Other examples include silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorinated silicate glass (FSG), and / or carbon-doped silicon oxide. The bonding pad structure 286 may include metallic materials such as gold (Au), copper (Cu), silver (Ag), cobalt (Co), tungsten (W), titanium (Ti), ruthenium (Ru), metal alloys (e.g., aluminum-copper (AlCu)), and / or combinations thereof.

[0063] The sealing ring region 230 includes a plurality of stacked interconnect structures 242 in the interconnect layer 214 and a plurality of stacked interconnect structures 264 in the interconnect layer 218 to seal the structure and layers of the image sensor device 210 to prevent moisture and other contaminants from entering and to provide structural rigidity to the image sensor device 210.

[0064] As mentioned above, providing Figure 2A-2C For example. Other examples can be found with reference to... Figure 2A-2C The differences mentioned above.

[0065] Figures 3A-3E This is a diagram illustrating an example of a pixel sensor 100 that may be included in the pixel sensor array 222 of the image sensor device 210 described herein. Figure 3A As shown, example 300 of pixel sensor 100 includes a photodiode 112 in a substrate 246 of sensor die 208. Color filter region 272 and microlens 274 of pixel sensor 100 are contained above photodiode 112.

[0066] like Figure 3A As further shown, the DTI structure 224 is contained within a substrate 246 and laterally surrounds a photodiode 112 within the substrate 246. Above the photodiode 112 are one or more diffusion structures 258 between the substrate 246 and the passivation layer 268. The diffusion structures 258 are contained between multiple portions of the DTI structure 224. In a top view of the pixel sensor 100, the diffusion structures 258 are contained within the inner periphery of the portion of the DTI structure 224 surrounding the photodiode 112.

[0067] DTI structure 224 includes a dielectric layer 252, a dielectric liner 254 (e.g., a conformal liner) between the dielectric layer 252 and the substrate 246, and a metal insert (e.g., a metal insert in the dielectric layer 252) Figure 3A (The elongated metal insert in the cross-sectional view). The DTI structure 224, including dielectric layer 252, dielectric liner 254 and metal insert 256, can each extend onto the back surface of substrate 246.

[0068] Each diffusion structure 258 is contained within a recess 302 extending into the substrate 246. The recess 302 is filled with a dielectric material to form the diffusion structure 258. Thus, the diffusion structure 258 extends into the back surface of the substrate 246. The diffusion structure 258 may have a V-shaped profile (in this case, each diffusion structure 258 may have an inverted pyramidal three-dimensional shape), a circular or U-shaped profile, and / or other profiles. The dielectric material may be incorporated between the diffusion structures 258 such that the diffusion structure 258 has a substantially flat top surface containing a passivation layer 268. The dielectric material of the diffusion structure 258 is contained directly on the substrate 246 within the recess 302 (e.g., in direct physical contact with the substrate 246 within the recess 302), in contrast to a liner in the recess 302 between the substrate 246 and the dielectric material of the diffusion structure 258. This occurs at least in part due to the techniques used to form the DTI structure 224 and the diffusion structure 258, which combine... Figures 8A-8HAnd other examples are described.

[0069] like Figure 3A As further shown, a doped implantation region 304 is contained within the substrate 246. The doped implantation region 304 is contained between the photodiode 112 and the diffusion structure 258. The doped implantation region 304 may comprise a blanket implantation region of the substrate 246 extending between opposite sides of the inner periphery of the DTI structure 224 in a cross-sectional view of the pixel sensor 100. The doped implantation region 304 is nonconformally doped with one or more types of dopants, such that the doped implantation region 304 extends between the top and bottom of the recess 302 in the substrate 246.

[0070] A doped implantation region 304 may be included to protect the photodiode 112 from defects that may arise in the substrate 246 due to etching of the substrate 246 to form a recess 302. These defects may include dangling bonds passivated by dopants included in the doped implantation region 304. In some embodiments, the photodiode 112 includes one or more n-type dopants, and the doped implantation region 304 includes one or more p-type dopants that increase the hole concentration (e.g., positive charge carriers) to passivate dangling bonds. In this case, a positive charge is induced on the back surface of the substrate 246, which reduces the likelihood of photocurrent leakage through the back surface of the substrate 246. Examples of p-type dopants that may be included in the doped implantation region 304 include boron (B), gallium (Ga), and / or indium (In), among others. Examples of n-type dopants include phosphorus (P), arsenic (As), and / or antimony (Sb), among others.

[0071] like Figure 3A As further shown, the metal mesh structure 270 may be contained on or above the DTI structure 224 and the passivation layer 268. Color filter regions 272 may be contained within the metal mesh structure 270.

[0072] Figure 3B Example 306 of pixel sensor 100 is shown, which is similar. Figure 3A Example 300 of pixel sensor 100, except that example 306 of pixel sensor 100 includes a composite mesh structure 308 instead of a metal mesh structure 270. The composite mesh structure 308 includes a metal layer 310 and a dielectric layer 312 on the metal layer 310.

[0073] Figure 3C Example 314 of pixel sensor 100 is shown, which is similar to Figure 3AExample 300 of pixel sensor 100, except that the metal mesh structure 270 in example 314 of pixel sensor 100 is encapsulated in passivation layer 268. In other words, the metal mesh structure 270 is embedded in passivation layer 268.

[0074] Figure 3D Example 316 of pixel sensor 100 is shown, which is similar to Figure 3A Example 300 of pixel sensor 100, except that example 316 of pixel sensor 100 includes multiple metal mesh structures. For example, example 316 of pixel sensor 100 includes a metal mesh structure 270 embedded in passivation layer 268 and another metal mesh structure 318 on metal mesh structure 270 and on passivation layer 268.

[0075] Figure 3E An example 320 of the pixel sensor 100 is shown, which is similar to Figure 3A Example 300 of pixel sensor 100, except that the dielectric liner 254 of DTI structure 224 extends continuously between multiple portions of DTI structure 224 and over photodiode 112 in example 320 of pixel sensor 100. The dielectric layer 252 of DTI structure 224 also extends continuously between multiple portions of DTI structure 224 and over photodiode 112, as with buffer layer 322 on dielectric liner 254. This can occur due to performing a planarization operation to form metal insert 256 of DTI structure 224, which stops before removing buffer layer 322 and dielectric liner 254 from over photodiode 112.

[0076] As mentioned above, providing Figures 3A-3E For example. Other examples can be found with reference to... Figures 3A-3E The differences mentioned above.

[0077] Figures 4A-4E This is a diagram illustrating an example of a pixel sensor 100 that may be included in the pixel sensor array 222 of the image sensor device 210 described herein. Figure 4A As shown, Example 400 of pixel sensor 100 is similar to Figure 3A Example 300 of pixel sensor 100. However, Figure 4A Example 400 of the pixel sensor 100 includes a doped implantation liner 402 instead of a doped implantation region 304. The doped implantation liner 402 includes a conformal implantation region that conforms to the contour of a recess 302 in which a diffusion structure 258 is formed. The doped implantation liner 402 performs a passivation function similar to that of the doped implantation region 304. However, the doped implantation liner 402 is formed using a different semiconductor processing technique than that used to form the doped implantation region 304, such as combining... Figures 9A-9H The processing techniques mentioned above.

[0078] Figure 4B Example 404 of pixel sensor 100 is shown, which is similar to Figure 4A Example 400 of pixel sensor 100, except that example 404 of pixel sensor 100 includes a composite mesh structure 308 instead of a metal mesh structure 270. The composite mesh structure 308 includes a metal layer 310 and a dielectric layer 312 on the metal layer 310.

[0079] Figure 4C Example 406 of pixel sensor 100 is shown, which is similar to Figure 4A Example 400 of pixel sensor 100, except that the metal mesh structure 270 in example 406 of pixel sensor 100 is encapsulated in passivation layer 268. In other words, the metal mesh structure 270 is embedded in passivation layer 268.

[0080] Figure 4D Example 408 of pixel sensor 100 is shown, which is similar to Figure 4A Example 400 of pixel sensor 100, except that example 316 of pixel sensor 100 includes multiple metal mesh structures. For example, example 316 of pixel sensor 100 includes a metal mesh structure 270 embedded in passivation layer 268 and another metal mesh structure 318 on top of metal mesh structure 270 and on passivation layer 268.

[0081] Figure 4E An example 410 of the pixel sensor 100 is shown, which is similar to Figure 4A Example 400 of pixel sensor 100, except that the dielectric liner 254 of DTI structure 224 extends continuously between multiple portions of DTI structure 224 and over photodiode 112 in example 320 of pixel sensor 100. The dielectric layer 252 of DTI structure 224 also extends continuously between multiple portions of DTI structure 224 and over photodiode 112, as with buffer layer 322 on dielectric liner 254. This can occur due to performing a planarization operation to form metal insert 256 of DTI structure 224, which stops before removing buffer layer 322 and dielectric liner 254 from over photodiode 112.

[0082] As mentioned above, providing Figures 4A-4E For example. Other examples can be found with reference to... Figures 4A-4E The differences mentioned.

[0083] Figures 5A-5EThis is a diagram of an exemplary embodiment 500 forming the circuit die 206 (or a portion thereof) described herein. In some embodiments, combined with Figures 5A-5E One or more of the semiconductor processing operations described herein may be performed using one or more semiconductor processing equipment (e.g., deposition equipment, exposure equipment, developing equipment, etching equipment, planarization equipment, plating equipment, ion implantation equipment and / or wafer / die transport equipment, etc.).

[0084] Instead of referring to Figure 5A The substrate 232 provides the device layer 212 of the circuit die 206. The substrate 232 may be provided in the form of a semiconductor wafer, such as a silicon (Si) wafer, an SOI wafer, and / or other types of semiconductor workpieces.

[0085] like Figure 5B As shown, one or more devices 236 may be formed in and / or on the substrate 232. One or more semiconductor processing equipment may be used to form one or more portions of the device 236. For example, a deposition equipment may be used to perform various deposition operations to deposit layers of the device 236 and / or deposit photoresist layers for etching portions of the substrate 232 and / or the deposited layers. As another example, an exposure equipment may be used to expose the photoresist layer to form a pattern in the photoresist layer. As another example, a developing equipment may be used to develop the pattern in the photoresist layer. As another example, an etching equipment may be used to etch the substrate 232 and / or portions of the deposited layers to form the device 236. As another example, a planarization equipment may be used to planarize portions of the device 236. As another example, a plating equipment may be used to deposit metal structures and / or layers of the device 236.

[0086] like Figure 5B As further shown, the dielectric layer 234 may be deposited on and / or on the substrate 232 and on and / or on the device 236. A deposition apparatus may be used to deposit the dielectric layer 234 using physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation techniques, or other types of deposition techniques. In some embodiments, after depositing the dielectric layer 234, a planarization apparatus may be used to planarize the dielectric layer 234.

[0087] like Figure 5CAs shown, a first portion of the interconnect layer 214 of the circuit die 206 is formed on the device layer 212. To form the first portion of the interconnect layer 214, a dielectric layer 238 (which may include one or more ILD layers, one or more IMD layers, one or more ESL layers, and / or one or more other types of dielectric layers) can be deposited using a deposition equipment employing PVD, ALD, CVD, oxidation, or other deposition techniques. In some embodiments, after depositing the dielectric layer 238, a planarization equipment can be used to planarize the dielectric layer 238.

[0088] Deposition equipment, exposure equipment, developing equipment, etching equipment, planarization equipment, plating equipment, and / or another semiconductor processing equipment may be used to perform various operations to form an interconnect structure 242 in a first portion of the interconnect layer 214. The deposition equipment and / or plating equipment may be used to deposit the interconnect structure 242 using PVD, ALD, CVD, electroplating, and / or another deposition technique. In some embodiments, after depositing the interconnect structure 242, a planarization equipment may be used to planarize the interconnect structure 242.

[0089] In some embodiments, a first portion of the interconnect layer 214 has multiple via layers (V layers) and metallization layers (M layers) constructed in the z-direction. For example, a first portion of the dielectric layer 238 may be formed, and a recess may be formed in the first portion of the dielectric layer 238, where a first interconnect structure 242 (e.g., a V0 via layer and an M0 metallization layer) may be formed. A second portion of the dielectric layer 238 may be formed, and a recess may be formed in the second portion of the dielectric layer 238, where a second interconnect structure 242 (e.g., a V1 via layer and an M1 metallization layer) may be formed. The remaining via layers and / or metallization layers of the first portion of the interconnect layer 214 may be formed in a similar manner.

[0090] like Figure 5D and Figure 5E As shown, a second portion of the interconnect layer 214 can be formed, and the second portion of the interconnect layer 214 may include a bonding layer 240 and a bonding structure 244. Figure 5D As shown, the bonding layer 240 may be formed on and / or on the dielectric layer 238 and on and / or on the topmost interconnect structure 242. A deposition apparatus may be used to deposit the bonding layer 240 using PVD, ALD, CVD, oxidation, or other deposition techniques. In some embodiments, after depositing the bonding layer 240, a planarization apparatus may be used to planarize the bonding layer 240.

[0091] like Figure 5EAs shown, a bonding structure 244 may be formed in the bonding layer 240. For example, a deposition equipment, an exposure equipment, and a developing equipment may be used to form a patterned mask layer on the bonding layer 240. An etching equipment may be used to etch the bonding layer 240 (e.g., using wet etching techniques, dry etching techniques) to form a recess in the bonding layer 240. A deposition equipment and / or a plating equipment may be used to deposit the bonding structure 244 in the recess using CVD, PVD, ALD, electroplating, and / or other deposition techniques. In some embodiments, after depositing the bonding structure 244, a planarization equipment may perform a planarization operation to planarize the bonding structure 244.

[0092] As mentioned above, providing Figures 5A-5E As an example. Other examples can be related to... Figures 5A-5E The differences mentioned above.

[0093] Figures 6A-6F This is a diagram of an exemplary embodiment 600 forming the sensor die 208 (or a portion thereof) described herein. In some embodiments, combined with Figures 6A-6F One or more of the semiconductor processing operations described herein may be performed using one or more semiconductor processing equipment (e.g., deposition equipment, exposure equipment, developing equipment, etching equipment, planarization equipment, plating equipment, ion implantation equipment and / or wafer / die transport equipment, etc.).

[0094] Instead refer to Figure 6A The substrate 246 provides the device layer 216 of the sensor die 208. The substrate 246 may be provided in the form of a semiconductor wafer, such as a silicon (Si) wafer, an SOI wafer, and / or other types of semiconductor workpieces.

[0095] like Figure 6B As shown, the photodiode 112 of the pixel sensor 100 of the pixel sensor array 222 of the sensor die 208 can be formed in the substrate 246 from the front side of the substrate 246. In some embodiments, an ion implantation stage can be used to implant ions into the substrate 246 to form a PN junction between the P-type doped region and the n-type doped region of the substrate 246, or to form a PIN junction between the P-type doped region of the substrate 246, the n-type doped region of the substrate 246, and the intrinsic (e.g., undoped) semiconductor region of the photodiode 112.

[0096] In some embodiments, prior to forming the photodiode 112, an ion implantation apparatus may be used to implant dopant (e.g., p-type dopant, n-type dopant) into the substrate 246 from the front side to form the doped implantation region 304. In some embodiments, after forming the photodiode 112, an ion implantation apparatus may be used to implant dopant (e.g., p-type dopant, n-type dopant) into the substrate 246 from the front side to form the doped implantation region 304.

[0097] like Figure 6B As further shown, an STI structure 250 can be formed in the substrate 246 (e.g., from the front side of the substrate 246) such that the STI structure 250 is located between the photodiodes 112. In some embodiments, the STI structure 250 is formed after the photodiodes 112 are formed. In some embodiments, the STI structure 250 is formed before the photodiodes 112 are formed. Deposition equipment, exposure equipment, and developing equipment can be used to form a patterned mask layer on the substrate 246. Etching equipment can be used to etch from the front side of the substrate 246 into the substrate 246 (e.g., using wet etching techniques, dry etching techniques) to form a recess in the front side of the substrate 246. Deposition equipment can be used to deposit the STI structure 250 in the recess using CVD, PVD, ALD, oxidation, and / or other deposition techniques. In some embodiments, after depositing the STI structure 250, a planarization equipment can perform a planarization operation to planarize the STI structure 250.

[0098] like Figure 6C As shown, the transmission gate 114 of the pixel sensor 100 may be formed on and / or on the front surface of the substrate 246. Forming the transmission gate 114 may include other examples such as depositing a gate dielectric layer on the front surface of the substrate 246, depositing a gate electrode on the gate dielectric layer, and / or forming a sidewall separator on the sidewall of the gate electrode.

[0099] like Figure 6C As further shown, the dielectric layer 248 may be formed on and / or on the front side of the substrate 246 and on and / or on the transmission gate 114. A deposition equipment may be used to deposit the dielectric layer 248 using CVD, PVD, ALD, electroplating, and / or other deposition techniques. In some embodiments, after depositing the dielectric layer 248, a planarization equipment may perform a planarization operation to planarize the dielectric layer 248.

[0100] like Figure 6DAs shown, a first portion of the interconnect layer 218 of the sensor die 208 is formed on the device layer 216. To form the first portion of the interconnect layer 218, a deposition apparatus may use PVD, ALD, CVD, oxidation, or other deposition techniques to deposit a dielectric layer 260 (which may include one or more ILD layers, one or more IMD layers, one or more ESL layers, and / or one or more other types of dielectric layers). In some embodiments, after depositing the dielectric layer 260, a planarization apparatus may be used to planarize the dielectric layer 260.

[0101] Deposition equipment, exposure equipment, developing equipment, etching equipment, planarization equipment, plating equipment, and / or another semiconductor processing equipment may be used to perform various operations to form an interconnect structure 264 in a first portion of the interconnect layer 218. The deposition equipment and / or plating equipment may be used to deposit the interconnect structure 264 using PVD, ALD, CVD, electroplating, and / or other deposition techniques. In some embodiments, after depositing the interconnect structure 264, a planarization equipment may be used to planarize the interconnect structure 264.

[0102] In some embodiments, a first portion of the interconnect layer 218 has multiple via layers (V layers) and metallization layers (M layers) constructed in the z-direction. For example, a first portion of the dielectric layer 260 may be formed, and a recess may be formed in the first portion of the dielectric layer 260, and a first interconnect structure 264 (e.g., V0 via layer, M0 metallization layer) may be formed in the recess. A second portion of the dielectric layer 260 may be formed, and a recess may be formed in the second portion of the dielectric layer 260, and a second interconnect structure 264 (e.g., V1 via layer, M1 metallization layer) may be formed in the recess. The remaining via layers and / or metallization layers of the first portion of the interconnect layer 218 may be formed in a similar manner.

[0103] like Figure 6E and Figure 6F As shown, a second portion of the interconnect layer 218 can be formed, and the second portion of the interconnect layer 218 may include a bonding layer 262 and a bonding structure 266. Figure 6E As shown, the bonding layer 262 may be formed on and / or on the dielectric layer 260 and on and / or on the topmost interconnect structure 264. A deposition apparatus may be used to deposit the bonding layer 262 using PVD, ALD, CVD, oxidation, or other deposition techniques. In some embodiments, after depositing the bonding layer 262, a planarization apparatus may be used to planarize the bonding layer 262.

[0104] like Figure 6FAs shown, a bonding structure 266 may be formed in the bonding layer 262. For example, a deposition station, an exposure station, and a developing station may be used to form a patterned mask layer on the bonding layer 262. An etching station may be used to etch the bonding layer 262 (e.g., using wet etching techniques, dry etching techniques) to form a recess in the bonding layer 262. A deposition station and / or a plating station may be used to deposit the bonding structure 266 in the recess using CVD, PVD, ALD, electroplating, and / or other deposition techniques. In some embodiments, after depositing the bonding structure 266, a planarization station may perform a planarization operation to planarize the bonding structure 266.

[0105] As mentioned above, providing Figures 6A-6F As an example. Other examples may be found related to... Figures 6A-6F The differences mentioned.

[0106] Figure 7A and Figure 7B This is a figure illustrating an exemplary embodiment 700 of the image sensor device 210 (or a portion thereof) described herein. In some embodiments, combined with Figure 7A and Figure 7B One or more of the semiconductor processing operations described herein may be performed using one or more semiconductor processing equipment (e.g., deposition equipment, exposure equipment, developing equipment, etching equipment, planarization equipment, plating equipment, ion implantation equipment and / or wafer / die transport equipment, etc.).

[0107] like Figure 7A and Figure 7B As shown, a bonding operation is performed to bond a circuit die 206 and a sensor die 208 to form an image sensor device 210. The circuit die 206 and the sensor die 208 may be bonded at a bonding interface 220, which may include bonding layers 240 and 262 (of the circuit die 206 and the sensor die 208, respectively) and bonding structures 244 and 266 (of the circuit die 206 and the sensor die 208, respectively). A bonding machine may be used to form a dielectric-to-dielectric bond between the bonding layers 240 and 262 at the bonding interface 220, and a metal-to-metal bond between the bonding structures 244 and 266 at the bonding interface 220.

[0108] like Figure 7B As shown, after bonding, the circuit die 206 and the sensor die 208 are stacked or arranged vertically in the z-direction of the image sensor device 210. The interconnect layer 214 of the circuit die 206 and the interconnect layer 218 of the sensor die 208 face each other in the image sensor device 210, and the device layer 212 of the circuit die 206 and the device layer 216 of the sensor die 208 face each other back to back.

[0109] As mentioned above, providing Figure 7A and Figure 7B As an example. Other examples may be found related to... Figure 7A and Figure 7B The differences mentioned.

[0110] Figure 8A-8I This is a diagram of an exemplary embodiment 800 of a pixel sensor array 222 forming the sensor die 208 (or a portion thereof) described herein. In some embodiments, combined with Figure 8A-8I One or more of the semiconductor processing operations described herein may be performed using one or more semiconductor processing equipment (e.g., deposition equipment, exposure equipment, developing equipment, etching equipment, planarization equipment, plating equipment, ion implantation equipment and / or wafer / die transport equipment, etc.).

[0111] like Figure 8A As shown, an ion implantation apparatus can be used to implant dopant from a first side 802 (e.g., the front side of substrate 246) into substrate 246 to form photodiodes 112 of pixel sensor 100 in pixel sensor array 222. Figure 8A As further shown, the ion implantation stage can be used to implant dopants (e.g., p-type dopants, n-type dopants) from a first side 802 (e.g., the front side) of the substrate 246 into the substrate 246 to form a doped implantation region 304 (e.g., a blanket-covered implantation region) in the substrate 246. The doped implantation region 304 can be formed such that the doped implantation region 304 is located at a second side 804 (e.g., the back side) of the substrate 246 opposite to the first side.

[0112] In some implementations, prior to the formation of photodiode 112 (e.g., during bonding) Figure 6B Prior to the aforementioned operation, a doped implantation region 304 is formed in the substrate 246. In some embodiments, this is done after the photodiode 112 is formed (e.g., during bonding). Figure 6B Following the aforementioned operation, an ion implantation apparatus can be used to implant dopants (e.g., p-type dopants, n-type dopants) from a first side 802 (e.g., the front side) of substrate 246 into substrate 246 to form a doped implantation region 304. Subsequently, [further actions can be performed]. Figure 6C-6F , Figure 7A and / or Figure 7B The additional operations described herein.

[0113] like Figure 8B-8I As shown, it can be executed Figure 6C-6F , Figure 7A and / or Figure 7B The back-side processing is performed after the additional operations described herein. For example... Figure 8BAs shown, a recess 302 for the diffusion structure 258 of the pixel sensor 100 may be formed in a second side 804 (e.g., the back side) of the substrate 246. The recess 302 may extend into the second side 804 and into the doped implantation region 304 above the photodiode 112. The doped implantation region 304 passivates damage to the substrate 246 that occurs during the formation of the recess 302.

[0114] In some embodiments, a pattern in the photoresist layer is used to etch a second side 804 of the substrate 246 to form a recess 302. In these embodiments, a deposition equipment can be used to form a photoresist layer on the second side 804 of the substrate 246. An exposure equipment can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development equipment can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching equipment can be used to etch from the second side 804 of the substrate into the doped implantation region 304 of the substrate 246 based on the pattern to form the recess 302. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or other types of etching operations. In some embodiments, a photoresist removal equipment can be used to remove the remaining portion of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some embodiments, a hard shielding layer is used as an alternative technique to pattern-based etching of the substrate 246.

[0115] like Figure 8C As shown, the recess 302 is filled with a dielectric material to form a diffusion structure 258 in the recess 302 above the photodiode 112. In this manner, the diffusion structure 258 is formed on a second side 804 (e.g., the back side) of the substrate 246, such that the diffusion structure 258 extends into the doped implantation region 304. A deposition apparatus can be used to deposit the dielectric material of the diffusion structure 258 using PVD, ALD, CVD, oxidation, or other deposition techniques.

[0116] Before forming the recesses of the DTI structure 224 of the pixel sensor array 222 and before forming the metal inserts 256 of the DTI structure 224, the recesses 302 are filled with dielectric material to form a diffusion structure 258. This prevents the metal material of the metal inserts 256 from being deposited in the recesses 302, which would otherwise need to be removed from the recesses 302 by etching. Instead, the deposition of the dielectric material causes the dielectric material of the diffusion structure 258 to merge over the recesses 302 to form a continuous layer. A planarization stage can be used to planarize the top surface of the dielectric material, making the top surface of the dielectric material substantially flat. This provides a flat substrate on which the metal fill layer can be formed, allowing the metal fill layer to be planarized to form the metal inserts 256 of the DTI structure 224, rather than etching the metal fill layer.

[0117] like Figure 8DAs shown, after the diffusion structure 258 is formed, a recess 806 for the DTI structure 224 can be formed around the photodiode 112 in the substrate 246. The recess 806 can be formed from a second side 804 (e.g., the back side) of the substrate 246. Since the diffusion structure 258 is formed before the recess 806 for the DTI structure 224 is formed, the recess 806 can also form a dielectric material through the diffusion structure 258.

[0118] In some embodiments, a pattern in the photoresist layer is used to etch a second side 804 of the substrate 246 to form a recess 806. In these embodiments, a deposition equipment can be used to form a photoresist layer on the second side 804 of the substrate 246. An exposure equipment can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development equipment can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching equipment can be used to etch the second side 804 of the substrate based on the pattern to form the recess 806. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or other types of etching operations. In some embodiments, a photoresist removal equipment can be used to remove the remaining portions of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some embodiments, a hard shielding layer is used as an alternative technique for pattern-based etching of the substrate 246.

[0119] like Figure 8E As shown, the dielectric liner 254 of the DTI structure 224 is conformally deposited on the sidewalls and bottom surface of the recess 806. A deposition apparatus can be used to deposit the dielectric liner 254 using a conformal deposition technique (e.g., ALD). Alternatively and / or alternatively, other deposition techniques, such as CVD, can be used. The dielectric liner 254 may extend continuously on a second side 804 (e.g., the back side) of the substrate 246 such that the dielectric liner 254 is contained above the photodiode 112 and above the diffusion structure 258.

[0120] like Figure 8F As shown, the dielectric layer 252 of the DTI structure 224 can be formed on the dielectric liner 254 on the sidewalls and bottom surface of the recess 806. The dielectric layer 252 can be formed such that open spaces are still maintained in the recess 806 for forming the metal insert 256. A deposition apparatus can be used to deposit the dielectric layer 252 using PVD, ALD, CVD, oxidation, and other deposition techniques. The dielectric layer 252 can extend continuously on a second side 804 (e.g., the back side) of the substrate 246, such that the dielectric layer 252 is contained above the photodiode 112 and above the diffusion structure 258.

[0121] like Figure 8GAs shown, the remaining open space in the recess 806 is filled with a metal filler layer 808. The metal filler layer 808 is deposited on the dielectric layer 252 in the recess 806. The metal filler layer 808 can be deposited such that it also extends across the photodiode 112 and merges over the photodiode 112 to form a merged portion 810 of the metal filler layer 808. This ensures that the recess 806 is completely filled with the metal filler layer 808. A deposition apparatus can be used to deposit the metal filler layer 808 using CVD, PVD, ALD, electroplating, and / or other suitable deposition techniques.

[0122] like Figure 8H As shown, a planarization operation (e.g., chemical mechanical planarization (CMP)) is performed using a planarization machine to planarize the metal filler layer 808, thereby removing the merged portion 810 of the metal filler layer 808 above the photodiode 112. The planarization of the metal filler layer 808 results in the formation of the metal insert 256 of the DTI structure 224. Multiple portions of the dielectric liner 254 and dielectric layer 252 above the photodiode 112 can also be removed during the planarization operation, such as... Figure 8H As shown in the example, to form Figures 3A-3D One or more of the pixel sensors 100 shown in the examples. Alternatively, the planarization operation may be stopped after removing the merged portion 810 of the metal filler layer 808 and before removing the portions of the dielectric liner 254 and dielectric layer 252 above the photodiode 112, to form... Figure 3E An example of a pixel sensor 100 is shown.

[0123] like Figure 8I As shown, a passivation layer 268 is formed on and / or on the dielectric material of the diffusion structure 258 and on and / or on the DTI structure 224. A deposition apparatus can be used to deposit the dielectric layer 252 using PVD, ALD, CVD, oxidation, or other deposition techniques. In some embodiments, after depositing the passivation layer 268, a planarization apparatus is used to planarize the passivation layer 268.

[0124] like Figure 8I As further shown, a metal mesh structure 270 may be formed on and / or on the passivation layer 268. A deposition apparatus may be used to deposit a metal layer on the passivation layer 268 using CVD, PVD, ALD, electroplating, and / or other suitable deposition techniques. The metal layer may be patterned and etched using lithography to form the metal mesh structure 270. A color filter region 272 may be formed in the metal mesh structure 270, and a microlens 274 may be formed on the color filter region 272.

[0125] As mentioned above, providing Figure 8A-8I As an example. Other examples may be found related to... Figure 8A-8I The differences mentioned.

[0126] Figure 9A-9I This is a diagram of an exemplary embodiment 900 of a pixel sensor array 222 forming the sensor die 208 (or a portion thereof) described herein. In some embodiments, combined with Figure 9A-9I One or more of the semiconductor processing operations described herein may be performed using one or more semiconductor processing equipment (e.g., deposition equipment, exposure equipment, developing equipment, etching equipment, planarization equipment, plating equipment, ion implantation equipment and / or wafer / die transport equipment, etc.).

[0127] like Figure 9A As shown, an ion implantation apparatus can be used to implant dopants into substrate 246 from a first side 802 (e.g., the front side of substrate 246) to form photodiodes 112 of pixel sensor 100 of pixel sensor array 222.

[0128] like Figure 9B-9I As shown, it can be executed Figure 6C-6F , Figure 7A and / or Figure 7B The back-side processing is performed after the additional operations described herein. For example... Figure 9B As shown, the recess 302 of the diffusion structure 258 for the pixel sensor 100 may be formed in the second side 804 (e.g., the back side) of the substrate 246.

[0129] like Figure 9C As shown, a doped layer 902 is formed on the sidewall of the recess 302. The doped layer 902 comprises polycrystalline silicon material and / or other types of materials doped with one or more types of dopants (e.g., n-type dopants, p-type dopants). The deposition equipment can use conformal deposition techniques (e.g., CVD or ALD) to conformally deposit the doped layer 902. Alternatively and / or other deposition techniques can be used to deposit the doped layer 902.

[0130] like Figure 9D As shown, an annealing operation is performed to anneal the doped layer 902. The annealing operation (sometimes referred to as dynamic surface annealing (DSA)) causes the dopant to diffuse from the doped layer 902 to the surface of the substrate 246, including the sidewalls of the recess 302. The diffusion of the dopant results in the formation of a doped implant liner 402 in the substrate 246. Therefore, the doped implant liner 402 is formed from a second side 804 of the substrate 246. The doped implant liner 402 passivates any damage to the substrate 246 that may occur during the formation of the recess 302.

[0131] like Figure 9E As shown, after the annealing operation, the doped layer 902 is subsequently removed. The doped layer 902 can be removed by etching, ashing, and / or other suitable techniques.

[0132] like Figure 9F As shown, the recess 302 is filled with a dielectric material to form a diffusion structure 258 in the recess 302 above the photodiode 112. In this manner, the diffusion structure 258 is formed on a second side 804 (e.g., the back side) of the substrate 246, such that the diffusion structure 258 extends into the doped implantation region 304. A deposition apparatus can be used to deposit the dielectric material of the diffusion structure 258 using PVD, ALD, CVD, oxidation, or other deposition techniques.

[0133] Before forming the recess 224 for the DTI structure 222 and before forming the metal insert 256 of the DTI structure 224, the recess 302 is filled with a dielectric material to form a diffusion structure 258. This prevents the metal material of the metal insert 256 from being deposited in the recess 302, which would otherwise need to be removed from the recess 302 by etching. Instead, the dielectric material is deposited so that the dielectric material of the diffusion structure 258 merges over the recess 302 to form a continuous layer. A planarization stage can be used to planarize the top surface of the dielectric material, making the top surface of the dielectric material flat. This provides a flat substrate on which the metal fill layer can be formed, allowing the metal fill layer to be planarized to form the metal insert 256 of the DTI structure 224, instead of etching the metal fill layer.

[0134] like Figure 9G and Figure 9H As shown, executable and combined Figure 8D-8H The similar semiconductor processing operations described above are used to form a DTI structure 224 around the photodiode 112 in the substrate 246 after the diffusion structure 258 has been formed. For example... Figure 9G As shown, a dielectric liner 254, a dielectric layer 252, and a metal filler layer 808 can be formed. Figure 9H As shown, a planarization machine is used to perform a planarization operation (e.g., CMP operation) to planarize the metal filler layer 808, thereby removing the merged portion 810 of the metal filler layer 808 above the photodiode 112. The planarization of the metal filler layer 808 results in the formation of the metal insert 256 of the DTI structure 224. Multiple portions of the dielectric liner 254 and dielectric layer 252 above the photodiode 112 can also be removed during the planarization operation, such as... Figure 9H As shown in the example, to form Figures 4A-4DOne or more of the pixel sensors 100 shown in the examples. Alternatively, the planarization operation may be stopped after removing the merged portion 810 of the metal filler layer 808 and before removing the portions of the dielectric liner 254 and dielectric layer 252 above the photodiode 112, to form... Figure 4E An example of a pixel sensor 100 is shown.

[0135] like Figure 9I As shown, a passivation layer 268 is formed on and / or on the dielectric material of the diffusion structure 258 and on and / or on the DTI structure 224. A deposition apparatus can be used to deposit the dielectric layer 252 using PVD, ALD, CVD, oxidation, or other deposition techniques. In some embodiments, after depositing the passivation layer 268, a planarization apparatus is used to planarize the passivation layer 268.

[0136] like Figure 9I As further shown, a metal mesh structure 270 may be formed on and / or on the passivation layer 268. A deposition apparatus may be used to deposit a metal layer on the passivation layer 268 using CVD, PVD, ALD, electroplating, and / or other suitable deposition techniques. The metal layer may be patterned and etched using lithography to form the metal mesh structure 270. A color filter region 272 may be formed in the metal mesh structure 270, and a microlens 274 may be formed on the color filter region 272.

[0137] As mentioned above, providing Figure 9A-9I As an example. Other examples may be found related to... Figure 9A-9I The differences mentioned.

[0138] Figure 10 This is a flowchart of an example process 1000 related to the formation of the pixel sensor array described herein. In some embodiments, one or more semiconductor processing equipment (e.g., deposition equipment, exposure equipment, developing equipment, etching equipment, planarization equipment, ion implantation equipment, annealing equipment, and / or wafer / die transport equipment, etc., and other examples) are used. Figure 10 One or more process blocks.

[0139] like Figure 10 As shown, process 1000 may include forming a photodiode (block 1010) of a pixel sensor in a substrate of a pixel sensor array. For example, one or more semiconductor processing equipment may be used to form a photodiode 112 of a pixel sensor 100 in a substrate 246 of a pixel sensor array 222, as described herein.

[0140] like Figure 10As further shown, process 1000 may include forming a recess (block 1020) laterally surrounding the photodiode in the substrate. For example, one or more semiconductor processing stations may be used to form a recess 806 laterally surrounding the photodiode 112 in the substrate 246, as described herein.

[0141] like Figure 10 As further shown, process 1000 may include a dielectric liner (block 1030) forming an isolation structure in the recess. For example, one or more semiconductor processing stations may be used to form a dielectric liner 254 of an isolation structure (e.g., DTI structure 224) in the recess 806, as described herein. In some embodiments, one or more semiconductor processing stations may be used to form the dielectric liner 254 of the isolation structure (e.g., DTI structure 224) on the sidewalls and bottom surface of the recess 806.

[0142] like Figure 10 As further shown, process 1000 may include forming a dielectric layer (block 1040) with an isolation structure on a dielectric liner in the recess. For example, one or more semiconductor processing equipment may be used to form a dielectric layer 252 with an isolation structure on a dielectric liner in the recess, as described herein.

[0143] like Figure 10 As further shown, process 1000 may include filling a recess 806 on the dielectric layer with a metal filler layer (block 1050). For example, one or more semiconductor processing instruments may be used to fill a recess 806 on the dielectric layer 252 with a metal filler layer 808, as described herein.

[0144] like Figure 10 As further shown, process 1000 may include an elongated metal insert (block 1060) for planarizing a metal filler layer to form an isolation structure. For example, one or more semiconductor processing units may be used to planarize the metal filler layer 808 to form an elongated metal insert 256 for an isolation structure, as described herein.

[0145] Process 1000 may include additional implementations, such as any single implementation or the implementations described below and / or any combination of one or more other processes described elsewhere herein.

[0146] In a first embodiment, forming the dielectric liner 254 includes forming the dielectric liner 254 over the photodiode 112.

[0147] In the second embodiment, alone or in combination with the first embodiment, process 1000 includes planarizing the dielectric liner 254 to remove the dielectric liner 254 from the photodiode 112.

[0148] In the third embodiment, filling the recess 806 with the metal filler layer 808 alone or in combination with one or more of the first and second embodiments includes filling the recess 806 with the metal filler layer 808 such that the metal filler layer 808 merges to form a merged portion 810 on the photodiode 112, and planarizing the metal filler layer 808 to form an elongated metal insert 256 includes planarizing the metal filler layer 808 to remove the merged portion 810 on the photodiode 112 to form an elongated metal insert 256.

[0149] In the fourth embodiment, the elongated metal insert 256 comprises copper (Cu), either alone or in combination with one or more of the first to third embodiments.

[0150] In the fifth embodiment, either alone or in combination with one or more of the first to fourth embodiments, the dielectric liner 254 comprises a high dielectric constant dielectric material, and the dielectric layer 252 comprises a low dielectric constant dielectric material.

[0151] Although Figure 10 An example block of process 1000 is shown, but in some embodiments, process 1000 includes... Figure 10 The examples shown are those with additional blocks, fewer blocks, different blocks, or different arrangements of blocks. Alternatively, two or more of the blocks in process 1000 can be executed in parallel.

[0152] Figure 11 This is a flowchart of an example process 1100 related to the formation of the pixel sensor array described herein. In some embodiments, one or more semiconductor processing equipment (e.g., deposition equipment, exposure equipment, developing equipment, etching equipment, planarization equipment, ion implantation equipment, annealing equipment, and / or wafer / die transport equipment, etc., and other examples) are used for the process. Figure 11 One or more process blocks.

[0153] like Figure 11 As shown, process 1100 may include forming a photodiode (block 1110) of the pixel sensor in the substrate of the pixel sensor array. For example, one or more semiconductor processing stations may form a photodiode 112 of the pixel sensor 100 in the substrate 246 of the pixel sensor array 222, as described herein.

[0154] like Figure 11 As further shown, process 1100 may include forming a first recess (block 1120) on a photodiode in a substrate. For example, one or more semiconductor processing instruments may be used to form a first recess 302 on a photodiode 112 in a substrate 246, as described herein.

[0155] like Figure 11 As further shown, process 1100 may include filling the first recess with a dielectric material to form a diffusion structure in the first recess above the photodiode (block 1130). For example, one or more semiconductor processing equipment may be used to fill the first recess 302 with a dielectric material to form a diffusion structure 258 in the first recess 302 above the photodiode 112, as described herein.

[0156] Further as Figure 11 As shown, process 1100 may include forming a second recess (block 1140) laterally surrounding a photodiode in the substrate after forming the diffusion structure. For example, after forming the diffusion structure 258, one or more semiconductor processing stations may be used to form a second recess 806 laterally surrounding a photodiode 112 in the substrate 246, as described herein.

[0157] like Figure 11 As further shown, process 1100 may include a dielectric liner (block 1150) forming an isolation structure in the second recess. For example, one or more semiconductor processing stations may be used to form a dielectric liner 254 of an isolation structure (e.g., DTI structure 224) in the second recess 806, as described herein. In some embodiments, one or more semiconductor processing stations may be used to form the dielectric liner 254 of the isolation structure (e.g., DTI structure 224) on the sidewalls and bottom surface of the second recess 806.

[0158] like Figure 11 As further shown, process 1100 may include forming a dielectric layer (block 1160) with an isolation structure on the dielectric liner in the second recess. For example, one or more semiconductor processing equipment may be used to form a dielectric layer 252 with an isolation structure on the dielectric liner 254 in the second recess 806, as described herein.

[0159] like Figure 11 As further shown, process 1100 may include forming an elongated metal insert (block 1170) on the dielectric layer in the second recess. For example, one or more semiconductor processing stations may be used to form the elongated metal insert 256 on the dielectric layer 252 in the second recess 806, as described herein.

[0160] Process 1100 may include additional implementations, such as any single implementation or the implementations described below and / or any combination of one or more other processes described elsewhere herein.

[0161] In the first embodiment, forming the second recess 806 includes forming the second recess 806 around the diffusion structure 258.

[0162] In the second embodiment, alone or in combination with the first embodiment, process 1100 includes forming a doped implantation region (e.g., bulk doped implantation region 304, doped implantation liner 402) in substrate 246, wherein the doped implantation region is perpendicularly adjacent to photodiode 112.

[0163] In the third embodiment, forming the doped implantation region, alone or in combination with one or more of the first and second embodiments, includes forming the doped implantation region prior to forming the first recess.

[0164] In the fourth embodiment, forming the doped implantation region, alone or in combination with one or more of the first to third embodiments, includes forming the doped implantation region prior to forming the photodiode 112.

[0165] In the fifth embodiment, forming the doped implantation region alone or in combination with one or more of the first to fourth embodiments includes forming the doped implantation region from a first side of the substrate 246, and forming a second recess 806 in the substrate 246 surrounding the photodiode 112 includes forming a second recess 806 in the substrate 246 surrounding the photodiode 112 from a second side of the substrate 246 perpendicular to the first side.

[0166] In the sixth embodiment, forming the doped implantation region, alone or in combination with one or more of the first to fifth embodiments, includes forming the doped implantation region after forming the photodiode 112 and after forming the first recess 302.

[0167] In the seventh embodiment, forming the photodiode 112, alone or in combination with one or more of the first to sixth embodiments, includes forming the photodiode 112 from a first side of the substrate 246, and wherein forming the doped implantation region includes forming the doped implantation region from a second side of the substrate 246 perpendicular to the first side.

[0168] In the eighth embodiment, forming the dielectric liner 254, alone or in combination with one or more of the first to seventh embodiments, includes forming the dielectric liner 254 over the diffusion structure 258.

[0169] In the ninth embodiment, either alone or in combination with one or more of the first to eighth embodiments, the dielectric liner 254 comprises a high dielectric constant dielectric material, wherein the dielectric materials of the dielectric layer 252 and the diffusion structure 258 each comprise a low dielectric constant dielectric material.

[0170] Although Figure 11 Example blocks of process 1100 are shown, but in some embodiments, process 1100 includes... Figure 11The examples shown are those with additional blocks, fewer blocks, different blocks, or different arrangements of blocks. Alternatively, two or more of the blocks in process 1100 can be executed in parallel.

[0171] In this manner, a metal insert is formed within a DTI structure that laterally surrounds the photodiode of the pixel sensor. Instead of etching a metal layer to form the metal insert, the metal insert is formed by forming a metal layer and then planarizing it. A recess for the diffusion structure is formed and then completely filled with a dielectric material, which is the opposite of partially filling the recess with a dielectric layer and then forming a metal layer on top of the dielectric layer. In this way, the diffusion structure has a substantially flat top surface upon which the metal layer is then formed, allowing the metal layer to be planarized rather than etched to form the metal insert. Forming the metal insert after the diffusion structure prevents the material of the metal insert from limiting the size and / or shape of the diffusion structure, providing greater manufacturing flexibility when forming the diffusion structure. This greater flexibility in selecting the size and / or shape of the diffusion structure allows it to be formed to distribute incident light for a specific optical wavelength and / or a wider range of optical bandwidths. This improves the QE of the pixel sensor. Alternatively and concurrently, forming the metal insert by planarization rather than etching allows for the use of metals with high reflectivity (e.g., copper) in the metal insert. This increases the reflectivity of the DTI structure, thereby enhancing the optical isolation provided by the DTI structure. Furthermore, completely filling the recess with a dielectric material results in fewer semiconductor processing operations compared to partially filling the recess with a dielectric layer and then completely filling it after the metal insert is formed, which can reduce the cost, complexity, and / or time required to manufacture pixel sensors.

[0172] As described in more detail above, some embodiments described herein provide a method. The method includes forming a photodiode of a pixel sensor in a substrate of a pixel sensor array. The method includes forming a recess laterally surrounding the photodiode in the substrate. The method includes forming a dielectric liner of an isolation structure in the recess. The method includes forming a dielectric layer of the isolation structure on the dielectric liner in the recess. The method includes filling the recess with a metal filler layer on the dielectric layer. The method includes planarizing the metal filler layer to form an elongated metal insert of the isolation structure.

[0173] In some embodiments, forming the dielectric liner includes forming the dielectric liner over the photodiode. In some embodiments, the method further includes planarizing the dielectric liner to remove the dielectric layer over the photodiode. In some embodiments, filling the recess with the metal filler layer includes filling the recess with the metal filler layer such that the metal filler layers merge to form a merged portion over the photodiode, wherein planarizing the metal filler layer to form the elongated metal insert includes planarizing the metal filler layer to remove the merged portion over the photodiode to form the elongated metal insert. In some embodiments, the elongated metal insert comprises copper. In some embodiments, the dielectric liner comprises a high-dielectric-constant dielectric material, wherein the dielectric layer comprises a low-dielectric-constant dielectric material.

[0174] As described in more detail above, some embodiments described herein provide a method. The method includes forming a photodiode of a pixel sensor in a substrate of a pixel sensor array. The method includes forming a first recess over the photodiode in the substrate. The method includes filling the first recess with a dielectric material to form a diffusion structure in the first recess over the photodiode. The method includes forming a second recess laterally surrounding the photodiode in the substrate after forming the diffusion structure. The method includes forming a dielectric liner of an isolation structure in the second recess. The method includes forming a dielectric layer of the isolation structure on the dielectric liner in the second recess. The method includes forming an elongated metal insert on the dielectric layer in the second recess.

[0175] In some embodiments, forming the second recess includes forming the second recess surrounding the diffusion structure. In some embodiments, the method further includes forming a doped implantation region in the substrate, wherein the doped implantation region is perpendicularly adjacent to the photodiode. In some embodiments, forming the doped implantation region includes forming the doped implantation region before forming the first recess. In some embodiments, forming the doped implantation region includes forming the doped implantation region before forming the photodiode. In some embodiments, forming the doped implantation region includes forming the doped implantation region from a first side of the substrate, wherein forming the second recess surrounding the photodiode in the substrate includes forming the second recess around the photodiode in the substrate from a second side of the substrate perpendicularly opposite to the first side. In some embodiments, forming the doped implantation region includes forming the doped implantation region after forming the photodiode and after forming the first recess. In some embodiments, forming the photodiode includes forming the photodiode from a first side of the substrate, wherein forming the doped implantation region includes forming the doped implantation region from a second side of the substrate perpendicularly opposite to the first side. In some embodiments, forming the dielectric liner includes forming the dielectric liner over the diffusion structure. In some embodiments, the dielectric liner comprises a high dielectric constant dielectric material, wherein the dielectric layer and the dielectric material of the diffusion structure each comprise a low dielectric constant dielectric material.

[0176] As described in more detail above, some embodiments described herein provide a pixel sensor array. The pixel sensor array includes a pixel sensor comprising a photodiode in a substrate. The pixel sensor array includes a DTI structure laterally surrounding the photodiode in the substrate, the DTI structure including a conformal liner, a dielectric layer on the conformal liner, and an elongated metal insert in the dielectric layer. The pixel sensor array includes a diffusion structure in a recess in the substrate, wherein the diffusion structure is above the photodiode and within the inner periphery of the DTI structure. The pixel sensor array includes a doped implantation region in the substrate, wherein the doped implantation region is between the photodiode and the diffusion structure.

[0177] In some embodiments, the doped implantation region includes a blanket implantation region extending between opposite sides of the inner periphery of the deep trench isolation structure in a cross-sectional view of the pixel sensor array, wherein the blanket implantation region extends between the top and bottom of the recess in the substrate where the diffusion structure is located. In some embodiments, the doped implantation region includes a conformal implantation region extending between opposite sides of the inner periphery of the deep trench isolation structure in a cross-sectional view of the pixel sensor array, wherein the conformal implantation region conforms to the cross-sectional profile of the recess in the substrate where the diffusion structure is located. In some embodiments, the diffusion structure is in direct physical contact with the substrate in the recess, wherein the conformal liner extends above and over the diffusion structure.

[0178] The terms “approximately” and “substantially” can indicate that the value of a given quantity varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are merely examples and are not intended to be limiting. It should be understood that, according to embodiments of the present invention, the terms “approximately” and “substantially” can refer to a percentage of the value of a given quantity.

[0179] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of this utility model, and are not intended to limit it. Although the embodiments of this utility model have been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A pixel sensor array, characterized in that, include: Photodiode, in the substrate; A deep trench isolation structure, laterally surrounding the photodiode in the substrate, includes: Conformal lining; A dielectric layer, on top of the conformal liner; and A slender metal insert is located within the dielectric layer; A diffusion structure is located in a recess in the substrate, wherein the diffusion structure is above the photodiode and within the inner periphery of the deep trench isolation structure; and A doped implantation region in the substrate, wherein the doped implantation region is located between the photodiode and the diffusion structure.

2. The pixel sensor array according to claim 1, characterized in that, The doped implantation region includes a blanket implantation region extending between opposite sides of the inner periphery of the deep trench isolation structure in a cross-sectional view of the pixel sensor array. as well as The blanket-covered implantation area extends between the top and bottom of the recess in the substrate where the diffusion structure is located.

3. The pixel sensor array according to claim 1, characterized in that, The doped implantation region includes a conformal implantation region extending between opposite sides of the inner periphery of the deep trench isolation structure in a cross-sectional view of the pixel sensor array; and The conformal implantation region corresponds to the cross-sectional profile of the recess in the substrate where the diffusion structure is located.

4. The pixel sensor array according to claim 1, characterized in that, The diffusion structure is in direct physical contact with the substrate within the recess; and The conformal liner extends above and over the diffusion structure.

5. The pixel sensor array according to claim 1, characterized in that, The material of the elongated metal insert is selected based on the operating wavelength range of the incident light from the pixel sensor array.

6. The pixel sensor array according to claim 1, characterized in that, The elongated metal insert extends over the back surface of the substrate.

7. The pixel sensor array according to claim 1, characterized in that, The diffusion structure described therein has a V-shaped profile, a circular profile, or a U-shaped profile.

8. The pixel sensor array according to claim 1, characterized in that, The doped implantation region extends between the top and bottom of the recess in the substrate.

9. The pixel sensor array according to claim 1, characterized in that, Also includes: A passivation layer is applied over the deep trench isolation structure and over the diffusion structure.

10. The pixel sensor array according to claim 1, characterized in that, Also includes: A metal mesh structure is situated above the deep trench isolation structure and around the photodiode, the metal mesh structure including an opening above the photodiode.

Images