Semiconductor device and power device

Abstract

The utility model relates to a semiconductor device and a power device, and the semiconductor device comprises a semiconductor layer, a gate trench, a body region, a source region, and a drain region. A gate insulating film including insulating film side portions disposed on sidewalls of the gate trench and an insulating film bottom portion sandwiched between two opposing first insulating film side portions and disposed on a bottom wall of the gate trench; the material of the bottom of the insulating film is different from that of the side part of the insulating film, and the dielectric constant of the material of the bottom of the insulating film is 2-10 times that of the material of the side wall of the insulating film; and the gate electrode is embedded in the gate trench through the gate insulating film, so that the withstand voltage characteristic of the trench gate is improved, the gate electric leakage is remarkably improved, and the gate reliability of the semiconductor device is improved.

Description

Technical Field

[0001] This disclosure generally relates to the field of semiconductor technology. More specifically, this disclosure relates to a semiconductor device and a power device. Background Technology

[0002] Silicon carbide (SiC), a wide-bandgap semiconductor material, has become an ideal choice for high-voltage, high-temperature, high-frequency, high-power, and low-switching-loss power electronic devices due to its advantages such as high critical breakdown electric field, high thermal conductivity, and high electron saturation velocity. Compared with planar MOSFETs, trench MOSFETs can effectively reduce cell size and increase channel density. For 4H-SiC materials, the vertical crystal plane defect density is low, resulting in higher channel mobility. However, since the electron mobility of the sidewalls is twice that of the crystal plane, the SiC / SiO2 interface of the MOSFET has a high interface state density, resulting in a relatively low channel mobility. Therefore, how to increase the gate voltage to improve the channel mobility of the MOSFET has become an urgent technical problem to be solved. Summary of the Invention

[0003] To address some or all of the aforementioned problems, this disclosure provides a semiconductor device and a power device that can improve channel mobility, enhance trench gate breakdown voltage characteristics, improve gate leakage current, and improve gate reliability of the semiconductor device.

[0004] According to a first aspect of this disclosure, a semiconductor device is provided, comprising: a semiconductor layer having a first conductivity type, the semiconductor layer including opposing first and second surfaces; a gate trench extending from the first surface of the semiconductor layer to the second surface; a bottom wall of the gate trench parallel to the first surface and a sidewall intersecting the first surface; a body region of a second conductivity type disposed in the semiconductor layer and defining a portion of the sidewall of the gate trench; a source region of the first conductivity type disposed on a surface portion of the body region and defining another portion of the sidewall of the gate trench; a drain region of the first conductivity type formed on one side opposite to the source and body regions and defining the bottom wall of the gate trench; a gate insulating film including: an insulating film side portion disposed on the sidewall of the gate trench and an insulating film bottom portion sandwiched between two opposing insulating film side portions and disposed on the bottom wall of the gate trench; a gate electrode disposed in the gate trench via the gate insulating film; the material of the insulating film bottom portion is different from the material of the insulating film side portion, and the dielectric constant of the material of the insulating film bottom portion is 2 to 10 times that of the dielectric constant of the material of the insulating film sidewall.

[0005] According to a second aspect of this disclosure, a power device is provided, comprising: a semiconductor layer having a first conductivity type, the semiconductor layer including opposing first and second surfaces; a gate trench extending from the first surface to the second surface of the semiconductor layer, the bottom wall of the gate trench being parallel to the first surface and the sidewalls intersecting the first surface; a body region of a second conductivity type disposed in the semiconductor layer and defining a portion of the sidewalls of the gate trench; a source region of the first conductivity type disposed on a surface portion of the body region and defining another portion of the sidewalls of the gate trench; and a drain of the first conductivity type. A region is formed on the side opposite to the source region and defines the bottom wall of the gate trench; a gate insulating film is disposed on the inner surface of the gate trench, and the gate insulating film is configured to include an insulating film side portion of a first material and an insulating film bottom portion of a second material, and the insulating film side portion and the insulating film bottom portion intersect each other, the insulating film side portion extends from the bottom wall of the gate trench to the opening of the gate trench, and the insulating film bottom portion is located between the bottom wall of the gate trench and the two insulating film side portions; the dielectric constant of the second material is 2 to 10 times that of the first material; the gate electrode is embedded in the gate trench via the gate insulating film.

[0006] In the semiconductor devices and power devices provided in this disclosure, the insulating film within the gate trench is configured as an insulating film sidewall on the sidewall of the gate trench and a bottom insulating film sandwiched between two opposing insulating film sidewalls and disposed on the bottom wall of the gate trench. The dielectric constant of the bottom insulating film material is 2 to 10 times that of the insulating film sidewall material. Because the bottom wall material of the gate trench has a higher dielectric constant than the sidewall material, the sidewalls and bottom are adapted to gate oxide layers with different dielectric constants based on different crystal oxidation rates. This reduces the significant difference in gate oxide thickness between the trench gate sidewalls and the bottom, allowing the trench bottom wall to withstand a greater electric field strength and a higher breakdown risk, thereby strengthening the gate withstand voltage and significantly increasing gate reliability. Therefore, this embodiment not only improves the withstand voltage characteristics of the trench gate and reduces gate leakage current, but also enhances the gate reliability of the semiconductor device or power device. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0008] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in some embodiments of this disclosure;

[0009] Figure 2This is a flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of the present disclosure;

[0010] Figures 3a-3f This is a schematic diagram illustrating structural changes in the process flow of a semiconductor device provided for some embodiments of this disclosure;

[0011] Figure 4 This is another flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of the present disclosure;

[0012] Figures 5a-5f This is a schematic diagram illustrating structural changes in the process flow of a semiconductor device provided in some embodiments of this disclosure;

[0013] Figure 6 This is a schematic diagram of the structure of a power device provided in some embodiments of this disclosure. Detailed Implementation

[0014] The present disclosure will now be further explained in conjunction with the accompanying drawings.

[0015] In the description of this application, "growth" refers to "epitaxygrowth," that is, growing a layer structure with certain requirements on a material to be treated. Techniques involving "growth" may include metal-organic chemical vapor deposition (MOCVD), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), atomic layer deposition (ALD), etc. Those skilled in the art can select an appropriate epitaxial growth technique based on the specific circumstances.

[0016] In the description of this application, "etching" should be understood in a broad sense, that is, growing a layer of photoresist on the surface of the material to be processed, selectively exposing and developing the photoresist through a mask to leave a photoresist layer on the surface of the material to be processed that is the same as the mask pattern, then selectively etching the material to be processed by chemical or physical methods, and finally peeling off the photoresist layer to form a structure on the material to be processed that corresponds to the mask pattern.

[0017] In the description of this application, the orientation or positional relationship indicated by terms such as "upper" or "lower" is based on the orientation or positional relationship shown in the accompanying drawings and is only for the convenience of describing this disclosure and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0018] In the description of this application, except for Embodiment 1, the other embodiments are written in a manner that avoids repetition as much as possible, that is, focusing on the differences between each embodiment and other embodiments. In these embodiments, any technical features that are not explicitly described can be referred to the corresponding description in Embodiment 1.

[0019] The specific embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0020] This disclosure provides a semiconductor device. Please refer to [link / reference]. Figure 1 , Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in some embodiments of this disclosure, such as... Figure 1 As shown, the semiconductor device 10 includes:

[0021] A semiconductor layer 101 having a first conductivity type, the semiconductor layer 101 including a first surface 1011 and a second surface 1012 opposite to each other;

[0022] A gate trench 102 extends from the first surface 1011 of the semiconductor layer 101 toward the second surface 1012. The bottom wall 1021 of the gate trench 102 is parallel to the first surface 1011, and the side wall 1022 intersects with the first surface 1011.

[0023] A body region 103 of the second conductivity type is disposed in the semiconductor layer 101 and defines a portion of the sidewall 1022 of the gate trench 102;

[0024] A source region 104 of the first conductivity type is disposed on the surface portion of the body region 103 and defines another portion of the gate trench 102.

[0025] A drain region 105 of the first conductivity type is formed on the side of the source region 104 opposite to the body region 103, and defines the bottom wall of the gate trench 102.

[0026] The gate insulating film 106 includes: an insulating film side portion 1061 disposed on the sidewall 1022 of the gate trench and an insulating film bottom portion 1062 sandwiched between two opposing insulating film side portions 1061 and disposed on the bottom wall 1021 of the gate trench.

[0027] The gate electrode 107 is embedded in the gate trench 102 via the gate insulating film 106;

[0028] The material of the bottom 1062 of the insulating film is different from the material of the side 1061 of the insulating film, and the dielectric constant of the material of the bottom 1062 of the insulating film is 2 to 10 times that of the material of the side wall 1061 of the insulating film.

[0029] Here, the first conductivity type can be P-type or N-type, and the second conductivity type can be N-type or P-type. It can be understood that when the first conductivity type is P-type, the second conductivity type is N-type, and vice versa. The following examples will all use N-type as the first conductivity type and P-type as the second conductivity type.

[0030] It should be noted that the shape and size of the gate trench 102 are determined according to the specific device design. In some embodiments, the gate trench 102 extends from the first surface 1011 toward the second surface 1012. The depth and width of the extension are designed according to the device design requirements. Typically, the depth of the gate trench 102 cannot exceed the thickness of the drift layer, and the bottom depth of the gate trench 102 must exceed the longitudinal thickness of the source region 104 and the body region 103.

[0031] The body region 103 is disposed in the body layer 101 and defines a portion of the sidewall 1022 of the gate trench 102. Since the second conductivity type is opposite to the first conductivity type of the semiconductor layer 101, a PN junction is also formed between it and the semiconductor layer, thereby providing specific electrical properties, such as adjusting the threshold voltage of the device.

[0032] The source region 104, having a first conductivity type, is disposed on the surface portion of the body 103 and defines the bottom wall 1021 of the gate trench 102. The presence of the source region 104 enables the device to achieve a specific current conduction function. It works together with the body region 103 and the semiconductor layer 101 to ensure the normal operation of the semiconductor device.

[0033] Of course, in some embodiments, a body contact region 1031 is also provided on the side of the source region 104 away from the gate trench 102. The body contact region 1031 has the same conductivity type as the body region 103, and the doping concentration of the body contact region 1031 is greater than that of the body region 103. This is used to reduce the ohmic contact resistance on the one hand and the body diode on-resistance on the other hand.

[0034] Drain region 105 may be an N-type drift layer in some embodiments.

[0035] The gate insulating film 106 includes an insulating film side portion 1061 disposed on the sidewall 1022 of the gate trench 102 and an insulating film bottom portion 1062 disposed on the bottom wall 1021 of the gate trench and sandwiched between the two opposing insulating film side portions 1061. The insulating film side portions 1061 and the insulating film bottom portion 1062 together constitute an insulating protection for the gate electrode 107, preventing it from short-circuiting with the surrounding conductive area.

[0036] The gate electrode 107 is embedded in the gate trench 102 via the gate insulating film 106. The gate electrode 107 is used to control the conduction and cutoff of the semiconductor device. By applying different voltage signals, the current can be regulated.

[0037] In some embodiments, the semiconductor material may be SiC or Si, etc. In particular, SiC has become an ideal choice for high-voltage, high-temperature, high-frequency, high-power, and low-switching-loss power electronic devices due to its advantages such as high critical breakdown electric field, high thermal conductivity, and high electron saturation velocity. In this embodiment, the semiconductor material may be SiC. Exemplarily, the semiconductor material may also be 4H-SiC, and of course, other crystal forms of SiC may also be used. It should be noted that the semiconductor layer 101, the body region 103, the source region 104, and the drain region 105 may be made of the same crystal form of SiC or different crystal forms of SiC.

[0038] It should be noted that in some embodiments, please refer to Figure 1 The semiconductor layer 101 may include a substrate 101a and an epitaxial layer 101b. The epitaxial layer 101b may include a buffer layer and a drift layer. It should be understood that the buffer layer is typically disposed between the substrate (not shown) and the drift layer, and its function is to alleviate lattice mismatch and stress between the substrate and the drift layer, reduce defect propagation, and improve the quality of the epitaxial layer and the reliability of the device. The drift layer is a key part of the SiC device epitaxial layer, mainly used to withstand reverse voltage and determining the device's breakdown voltage and other performance characteristics. During operation, charge carriers drift and move within this layer. In some embodiments, the doping concentration of the substrate 101a is greater than the doping concentration of the epitaxial layer 101b.

[0039] Doping concentration: Generally low doping is used. For n-type SiC devices, the n-type doping concentration is typically in the range of [range missing]. For example, in some 600V withstand voltage SiC MOSFETs, the n-type doping concentration of the drift layer may be around [range missing]. Such a low doping concentration is beneficial for improving the breakdown voltage of the device, enabling it to withstand higher reverse voltages without breakdown.

[0040] It is important to understand that, compared to planar devices, SiC trench devices can effectively reduce cell size and increase channel density. For 4H-SiC materials, the crystal planes of the trench sidewalls are typically (112.0) and the crystal plane of the trench bottom wall is (0001). Generally speaking, the oxidation rates of different crystal planes vary greatly, with (000.1) oxidation being the fastest and (0001) oxidation being the slowest, while (112.0) is in between. This results in a significant difference in the gate oxide thickness between the sidewalls and bottom wall of the trench type. Moreover, the bottom wall of the trench bears the largest electric field, which has a high risk of FN (Fowler-Nordheim) tunneling, leading to a decrease in gate breakdown voltage and a significant reduction in reliability.

[0041] Based on this, since the gate insulating film in this embodiment includes a bottom portion and a side portion, and the materials of the bottom and side portions are different, with the dielectric constant of the bottom material being 2 to 10 times that of the sidewall material, and the gate oxide thickness differing between the sidewalls and bottom due to different oxidation rates on different crystal planes, the use of materials with significantly different dielectric constants can compensate for the impact of this thickness difference to some extent. The bottom material with a higher dielectric constant can better withstand the electric field even with a thinner gate oxide layer at the bottom, because a high dielectric constant means a stronger ability to store electrical energy. Under the same electric field strength, according to the capacitance calculation formula (where C is capacitance, S is dielectric constant, S is plate area, and d is plate spacing), a high dielectric constant material can store more charge with a smaller thickness d, thus better resisting the electric field and reducing the risk of FN tunneling.

[0042] In this embodiment, since the materials at the bottom of the insulating film are different from those on the sides of the insulating film, resulting in an inherent difference in the oxide thickness of the trench structure, the electric field distribution between the trench sidewalls and the trench bottomwalls is balanced by a reasonable matching of dielectric constants, thereby improving the gate withstand voltage performance and thus enhancing the reliability of the semiconductor device.

[0043] Furthermore, it should be added that in this embodiment, since the material at the bottom of the insulating film is different from the material on the sides of the insulating film, and the dielectric constant of the material at the bottom of the insulating film is 2 to 8 times greater than that of the material on the sides of the insulating film, the thickness of the gate oxide insulating film on the bottom wall of the trench is adjustable, or in other words, the difference in thickness between the gate oxide insulating film on the bottom wall of the trench and the gate oxide insulating film on the sides of the trench is reduced. For example, in this embodiment, the thickness of the bottom of the insulating film can be 2 to 8 times smaller than the thickness of the gate oxide insulating film on the bottom wall of the trench in conventional devices. It should be noted that the trench mentioned here is the gate trench described in this embodiment.

[0044] In some embodiments, the thickness of the bottom 1062 of the insulating film is the same as the thickness of the insulating film 1061, or the thickness of the bottom 1062 of the insulating film is thinner than the thickness of the side portion 1061 of the insulating film. It should be noted that the thickness direction here is the oxidation direction of the semiconductor material. For the bottom 1062 of the insulating film, the thickness direction is the direction from the first surface 1011 to the second surface 1012 of the semiconductor layer 101. For the side portion 1061 of the insulating film, the thickness direction is the direction from inside the gate trench 102 to outside the gate trench 102.

[0045] In some embodiments, the thickness of the bottom of the insulating film is 40~200 nm. It should be understood that, on the one hand, the total thickness of the bottom of the insulating film cannot exceed the distance from the bottom wall of the gate trench to the bottom of the body region; on the other hand, if the bottom of the insulating film is too thick, it will result in a very thin poly layer, which will lead to an uneven distribution of the electric field applied to the gate oxide. Therefore, setting the thickness of the bottom of the insulating film to 40~200 nm can effectively improve the gate withstand voltage while ensuring the basic electrical performance of the device.

[0046] In some embodiments, the material on the side of the insulating film is SiO2. The material at the bottom of the insulating film includes a high-k dielectric material, wherein the dielectric constant of the high-k dielectric material is greater than the dielectric constant of silicon oxide (3.9). According to Gauss's law, E ox ·ε ox =E s ·ε s ( E ox and E s It refers to the magnitude of the electric field that SiO2 and SiC can withstand. ε ox and ε s These are the dielectric constants of SiO2 and SiC, respectively. If SiO2 continues to be used as the bottom insulating material for trenching, the peak electric field intensity in the oxide layer is 2.5 times that inside the semiconductor. If a material with a higher dielectric constant than SiO2 is used instead... ε ox =3.9 Even higher than SiC ( ε s =9.6 If the material is a certain type of material, the peak electric field will be dispersed instead of concentrated at the bottom of the trench, which can greatly improve the device's withstand voltage. Compared with SiO2, it can improve the withstand voltage by more than 2 times, and the gate leakage current can also be greatly improved.

[0047] In some embodiments, the high-k dielectric material includes at least one of the following: Si3N4, HfO2, HfSi X The dielectric materials include La2O3, Ta2O5, TiO2, Y2O5, ZrO2, and ZrSiO. Please refer to Table 1. In some embodiments, the dielectric materials can be combined according to different device requirements.

[0048] Table 1:

[0049] In some embodiments, the semiconductor device (not shown) further includes: an interlayer dielectric covering the gate electrode; a source electrode covering the semiconductor layer and the interlayer dielectric; and a drain electrode disposed on a second surface of the semiconductor layer.

[0050] Another aspect of this application provides a method for manufacturing a semiconductor device. Please refer to... Figure 2 As shown in Figure 3, the method for fabricating this semiconductor device includes:

[0051] Step 21: Provide a first device 31, the first device comprising: a semiconductor layer 101 having a first conductivity type, the semiconductor layer 101 including opposing first surfaces 1011 and second surfaces 1012; a body region 103 of a second conductivity type disposed in the semiconductor layer 101; a source region 104 of a first conductivity type disposed on the surface portion of the body region 103; and a drain region 105 of a first conductivity type formed on the side of the source region 104 opposite to the body region 103.

[0052] Step 22: Fabricate gate trench 102 on the first device 31;

[0053] For example, please refer to Figure 3a The etching process can begin on the first surface 1011 of the semiconductor layer 101 of the first device 31 using wet etching or dry etching, and proceed through the source region 104 and the body region 103 to the drain region 105. This results in the body region 103 and the source region 104 being located on the sidewall 1021 of the gate trench 102, and the drain region 105 defining the bottom 1022 of the gate trench 102.

[0054] Step 23: Deposit a first dielectric 301 of a certain thickness on the bottom wall and sidewalls of the gate trench;

[0055] Please see Figure 3b It should be noted that the first dielectric material can be SiO2 or poly, etc., with a thickness of 40~100nm, used for subsequent self-aligned formation of the gate insulating film. Of course, the specific material of the first dielectric material is not limited here, as long as it can be used as a mask material.

[0056] Step 24: Remove the first dielectric from the bottom wall of the gate trench using a self-aligned process.

[0057] Please see Figure 3c At this time, the sidewall 1021 of the gate trench 102 forms a self-aligned spatial spacing protection layer.

[0058] Step 25: Deposit a second dielectric of a certain thickness at the bottom and sidewalls of the gate trench, namely the bottom of the insulating film 1062.

[0059] Please see Figure 3dThe second dielectric material here is a high-k dielectric, such as (Si3N4, Al2O3, TiO2, HfO2, etc.), with a thickness of 40~200nm. According to Gauss's law, Eox·εox=Es·εs (Eox and Es are the electric field strengths that SiO2 and SiC can withstand, and εox and εs are the dielectric constants of SiO2 and SiC, respectively). If SiO2 is used as the bottom material of the trench, the peak electric field strength in the oxide layer is 2.5 times that inside the semiconductor. If a material with a dielectric constant higher than SiO2 (εox=3.9) or even higher than SiC (εs=9.6) is used, the peak electric field will be dispersed and will not be concentrated at the bottom of the trench, which can greatly improve the breakdown voltage of the device. Compared with SiO2, it can improve the breakdown voltage by more than 2 times, and the gate leakage current can also be greatly improved.

[0060] Step 26: Remove the spacer protective layer 3011 using a wet process;

[0061] Please see Figure 3e It can be seen that the remaining second dielectric is formed as the bottom 1062 of the insulating film of the gate trench bottom wall 106.

[0062] Step 27: High-temperature in-situ growth of gate oxide (SiO2) on the sidewall of the gate trench to form a gate insulating film.

[0063] Please see Figure 3f It can be seen that an insulating film side portion 1061 is grown on the sidewall 1021 of the gate trench 102.

[0064] Another aspect of this application provides a method for manufacturing a semiconductor device. Please refer to... Figure 4 As shown in Figure 5, the method for fabricating this semiconductor device includes:

[0065] Step 41: Provide a first device 31, the first device comprising: a semiconductor layer 101 having a first conductivity type, the semiconductor layer 101 including opposing first surfaces 1011 and second surfaces 1012; a body region 103 of a second conductivity type disposed in the semiconductor layer 101; a source region 104 of a first conductivity type disposed on the surface portion of the body region 103; and a drain region 105 of a first conductivity type formed on the side of the source region 104 opposite to the body region 103.

[0066] Step 22: Fabricate gate trench 102 on the first device 31;

[0067] For example, please refer to Figure 5aThe etching process can begin on the first surface 1011 of the semiconductor layer 101 of the first device 31 using wet etching or dry etching, and proceed through the source region 104 and the body region 103 to the drain region 105. This results in the body region 103 and the source region 104 being located on the sidewall 1021 of the gate trench 102, and the drain region 105 defining the bottom 1022 of the gate trench 102.

[0068] Step 42: Deposit a second dielectric of a certain thickness at the bottom and sidewalls of the gate trench, i.e., the bottom of the insulating film 1062;

[0069] Please see Figure 5b The second dielectric material here is a high-k dielectric material, such as (Si3N4, Al2O3, TiO2, HfO2, etc.), with a thickness of 40~200nm, used to improve the withstand voltage characteristics of the gate trench.

[0070] Step 43: Deposit a first dielectric 301 of a certain thickness on the bottom wall of the gate trench. For example, it can be SiO2 (40~200nm) as a hard mask material to protect the high-k material at the bottom.

[0071] Please see Figure 5c The bottom wall of the gate trench has an additional layer of hard mask material covering the high-k dielectric.

[0072] Step 44: Remove the first dielectric 301, i.e., hard mask material, from the sidewalls using a wet etching process with a high selectivity ratio.

[0073] Please see Figure 5d There is no dielectric covering at the sidewall 1021 of the gate trench 102.

[0074] Step 45: Please refer to Figure 5e The first dielectric layer 301, such as the SiO2 mask layer, on the surface of the high-k material is removed by a wet process.

[0075] Step 46: High-temperature in-situ growth of gate oxide (SiO2) on the sidewall of the gate trench to form a gate insulating film.

[0076] Please see Figure 5f It can be seen that an insulating film side portion 1061 is grown on the sidewall 1021 of the gate trench 102.

[0077] It should be noted that the semiconductor device prepared by the method described in this embodiment has the same technical effect as the semiconductor device described above, and will not be repeated here.

[0078] This disclosure also provides a power device; please refer to the following embodiments. Figure 6 , Figure 6 This is another structural schematic diagram of a power device provided in some embodiments of the present disclosure, such as... Figure 6 As shown, the power device 100 includes:

[0079] A semiconductor layer 101 having a first conductivity type, the semiconductor layer 101 including opposing first surfaces 1011 and second surfaces 1012;

[0080] The gate trench 102 extends from the first surface 1011 of the semiconductor layer 101 to the second surface 1012. The bottom wall of the gate trench 102 is parallel to the first surface 101, and the sidewalls intersect with the first surface.

[0081] A gate trench 102 extends from the first surface 1011 of the semiconductor layer 101 toward the second surface 1012. The bottom wall 1021 of the gate trench 102 is parallel to the first surface 1011, and the side wall 1022 intersects with the first surface 1011.

[0082] A body region 103 of the second conductivity type is disposed in the semiconductor layer 101 and defines a portion of the sidewall 1022 of the gate trench 102;

[0083] A source region 104 of the first conductivity type is disposed on the surface portion of the body region 103 and defines another portion of the sidewall 1022 of the gate trench 102.

[0084] A source region 104 of the first conductivity type is disposed on the surface portion of the body region 103 and defines the bottom wall 1021 of the gate trench 102.

[0085] A drain region 105 of the first conductivity type is formed on the side of the source region 104 opposite to the body region 103, and defines the bottom wall of the gate trench 102.

[0086] A gate insulating film 106 is disposed on the inner surface of the gate trench 102. The gate insulating film 106 is configured to include an insulating film side portion 1061 of a first material and an insulating film bottom portion 1062 of a second material, with the insulating film side portion 1061 and the insulating film bottom portion 1062 intersecting each other. The insulating film side portion 1061 extends from the bottom wall 1041 of the gate trench 102 to the opening of the gate trench 102. The insulating film bottom portion 1062 is located between the bottom wall 1022 of the gate trench 102 and the two insulating film side portions 1061. The dielectric constant of the second material is 2 to 10 times that of the first material.

[0087] The gate electrode 107 is embedded in the gate trench 102 via the gate insulating film 106.

[0088] It should be noted that the power device in this embodiment has the same technical effects as the semiconductor device embodiments described above, and will not be repeated here.

[0089] In some embodiments, please refer to Figure 2 The power device also includes:

[0090] Source wiring 108 is formed on semiconductor layer 101 in such a way that source regions 104 are connected together;

[0091] An interlayer insulating film 109 is disposed between the source wiring 108 and the gate electrode 107;

[0092] Drain wiring 1010 is formed on semiconductor layer 101 in a manner connected to drain region 105.

[0093] In some embodiments, the thickness of the bottom 1062 of the insulating film is 40~200nm.

[0094] In some embodiments, the insulating film side portion 1061 and the insulating film bottom portion 1062 each have a uniform thickness, thereby ensuring the uniformity of the electric field.

[0095] The above description is merely a preferred embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any person skilled in the art can easily make changes or variations within the technical scope of this disclosure, and such changes or variations should be covered within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims. As long as there is no structural conflict, the various technical features mentioned in the various embodiments can be combined in any way. This disclosure is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A semiconductor device, comprising: A semiconductor layer having a first conductivity type, the semiconductor layer comprising opposing first and second surfaces; A gate trench extends from the first surface of the semiconductor layer to the second surface, with the bottom wall of the gate trench parallel to the first surface and the sidewalls intersecting the first surface. A body region of a second conductivity type is disposed in the semiconductor layer and defines a portion of the sidewall of the gate trench; A source region of a first conductivity type is disposed on the surface portion of the body region and defines another portion of the sidewall of the gate trench; A drain region of the first conductivity type is formed on the side of the source region opposite to the body region, and defines the bottom wall of the gate trench; A gate insulating film includes: an insulating film side portion disposed on the sidewall of the gate trench and an insulating film bottom portion sandwiched between two opposing insulating film sides and disposed on the bottom wall of the gate trench; The gate electrode is embedded in the gate trench via the gate insulating film; The material at the bottom of the insulating film is different from the material on the side of the insulating film, and the dielectric constant of the material at the bottom of the insulating film is 2 to 10 times that of the material on the sidewall of the insulating film.

2. The device according to claim 1, characterized in that, The bottom of the insulating film has the same thickness as the side portion of the insulating film.

3. The device according to claim 1, characterized in that, The bottom of the insulating film is thinner than the side portion of the insulating film.

4. The device according to claim 1, characterized in that, The thickness of the bottom of the insulating film is 40~200nm.

5. The device according to claim 1, characterized in that, The material on the side of the insulating film includes silicon oxide; the material at the bottom of the insulating film includes a high-k dielectric material, wherein the dielectric constant of the high-k dielectric material is greater than that of silicon oxide.

6. A power device, comprising: A semiconductor layer having a first conductivity type, the semiconductor layer comprising opposing first and second surfaces; A gate trench extends from the first surface of the semiconductor layer to the second surface, with the bottom wall of the gate trench parallel to the first surface and the sidewalls intersecting the first surface. A body region of a second conductivity type is disposed in the semiconductor layer and defines a portion of the sidewall of the gate trench; A source region of a first conductivity type is disposed on the surface portion of the body region and defines another portion of the sidewall of the gate trench; A drain region of the first conductivity type is formed on the side of the source region opposite to the body region, and defines the bottom wall of the gate trench; A gate insulating film is disposed on the inner surface of the gate trench. The gate insulating film is configured to include an insulating film side portion of a first material and an insulating film bottom portion of a second material, wherein the insulating film side portion and the insulating film bottom portion intersect each other. The insulating film side portion extends from the bottom wall of the gate trench to the opening of the gate trench, and the insulating film bottom portion is located between the bottom wall of the gate trench and the two insulating film side portions. The dielectric constant of the second material is 2 to 10 times that of the first material. The gate electrode is embedded in the gate trench via the gate insulating film.

7. The device according to claim 6, wherein the power device further comprises: Source wiring is formed on the semiconductor layer in such a way that the source regions are connected together; An interlayer insulating film is disposed between the source wiring and the gate electrode; Drain wiring is formed on the semiconductor layer in a manner that connects to the drain region.

8. The device according to claim 6, wherein the thickness of the bottom of the insulating film is 40~200nm.

9. The device according to claim 6, wherein the side portion of the insulating film and the bottom portion of the insulating film each have a uniform thickness.

Images