Packaging module
By setting an anti-warping layer on the packaging unit, the warping problem is improved, the operability of the packaging module is realized, the process difficulties caused by warping are solved, and the cost is controllable.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SILICONWARE PRECISION IND CO LTD
- Filing Date
- 2025-05-16
- Publication Date
- 2026-05-15
AI Technical Summary
Existing technologies suffer from warping issues caused by the removal of the carrier plate during the packaging process, which makes subsequent process stations difficult or impossible to operate, especially when the robotic arm suction head cannot vacuum pick up solder balls.
An anti-warping layer is set on the packaging unit, and the warping is improved by the stretching and contraction of the adhesive film under reverse stress. The packaging module design with a monolithic architecture includes multiple packaging units and an anti-warping layer, covering the packaging layer.
It enables workability in subsequent process stations, reduces problems caused by warpage, and does not require additional processes or materials, keeping costs under control.
Smart Images
Figure CN224250167U_ABST
Abstract
Description
Technical Field
[0001] This application relates to a semiconductor packaging technology, and more particularly to a packaging module comprising multiple packaging units. Background Technology
[0002] High-performance computing (HPC) technology is becoming increasingly important and widespread in modern life (such as the development of medical technology, the development of cancer drugs, or the automatic sensing and detection computing of autonomous vehicles). Among them, the packaging structures used in devices applied in these fields are such as fan-out multi-chip module (FOMCM) structure and fan-out embedded bridge die (FOEB) structure, which have the characteristics of multi-chip / high circuit layer count / large fan-out size / high heat dissipation design.
[0003] Please see Figures 1A to 1C This is a cross-sectional schematic diagram of a conventional fan-out package structure. First, multiple conductive pillars 11 and multiple semiconductor chips 12 are formed on a carrier plate 10. Next, an overlay layer 13 is formed on the carrier plate 10 to cover the semiconductor chips 12 and the multiple conductive pillars 11. Then, a circuit structure 14 is formed on the overlay layer 13. Next, multiple electronic components 15 are placed on the circuit structure 14, and then an encapsulation layer 16 covers the multiple electronic components 15. Afterward, the carrier plate 10 is removed to bond multiple solder balls 17.
[0004] However, after the aforementioned method forms the encapsulation layer 16, the carrier plate 10 needs to be removed to perform the solder ball 17 placement operation. However, after the carrier plate 10 is removed, the overall structure warps due to stress issues, resulting in a smiling or crying face shape. This causes difficulties or even prevents subsequent process stations from placing the overall structure into the machine (such as the robotic arm's suction head being unable to vacuum-adhere due to the overall structure warping during solder ball placement).
[0005] Therefore, how to overcome the various shortcomings of existing technologies is a technical problem that all sectors urgently need to solve. Utility Model Content
[0006] In view of the deficiencies of the prior art, this application provides a packaging module with a monolithic architecture, comprising: multiple packaging units, wherein each packaging unit includes a circuit structure, multiple electronic components disposed on the circuit structure and a packaging layer covering the multiple electronic components; and an anti-warping layer formed on the multiple packaging units to cover the packaging layer.
[0007] This application also provides a method for manufacturing a packaging module, wherein a plurality of packaging units are formed on a carrier board, wherein each packaging unit includes a circuit structure, a plurality of electronic components disposed on the circuit structure and a packaging layer covering the plurality of electronic components; and an anti-warping layer is formed on the plurality of packaging units to cover the packaging layer.
[0008] In the aforementioned packaging module and its manufacturing method, each packaging unit further includes a bridge chip disposed on the circuit structure and electrically connected to the circuit structure.
[0009] In the aforementioned packaging module and its manufacturing method, each packaging unit further includes a plurality of conductive posts disposed on the circuit structure and electrically connected to the circuit structure.
[0010] In the aforementioned packaging module and its manufacturing method, each packaging unit further includes a covering layer disposed on the circuit structure to cover the bridging chip and the plurality of conductive pillars.
[0011] The aforementioned packaging module and its manufacturing method further include removing the carrier plate, forming a circuit portion electrically connected to the plurality of conductive pillars on the covering layer, and setting a plurality of conductive elements electrically connected to the circuit portion on the circuit portion.
[0012] The aforementioned packaging module and its manufacturing method further include removing the carrier plate to provide multiple conductive elements electrically connected to the circuit structure on the circuit structure.
[0013] The aforementioned packaging module and its manufacturing method also include removing the anti-warping layer and exposing the plurality of electronic components outside the packaging layer.
[0014] In the aforementioned packaging module and its manufacturing method, each packaging unit is a fan-out embedded bridge structure or a fan-out multi-chip structure.
[0015] In the aforementioned packaging module and its manufacturing method, the thickness of each packaging unit is 900–1400 micrometers. The aspect ratio of the electronic component is 1.5–3. The thickness of the anti-warping layer is 50–100 micrometers.
[0016] As can be seen from the above, the packaging module of this application sets an anti-warping layer on the packaging layer of multiple packaging units in the monolithic architecture, and uses the film stretching and shrinking of reverse stress to improve the large warping caused by the original process, thereby achieving workability in subsequent process stations and reducing problems caused by warping. Attached Figure Description
[0017] Figures 1A to 1C This is a cross-sectional schematic diagram of an existing fan-out packaging structure.
[0018] Figures 2A to 2E This is a cross-sectional schematic diagram of the first embodiment of the packaging module and its manufacturing method of this application.
[0019] Figures 3A to 3C This is a cross-sectional schematic diagram of the second embodiment of the packaging module and its manufacturing method of this application.
[0020] Explanation of reference numerals in the attached figures
[0021] 10. Bearing plate
[0022] 11 Conductive pillars
[0023] 12 Semiconductor chips
[0024] 13. Covering layer
[0025] 14. Circuit Structure
[0026] 15 Electronic components
[0027] 16 Encapsulation Layer
[0028] 17 Tin Balls
[0029] 2,3 packaged modules
[0030] 20, 30 package units
[0031] 20a First side
[0032] 20b Second side
[0033] 21 Bridge chip
[0034] 210 Conductor
[0035] 22,32 Line Structure
[0036] 220 dielectric layer
[0037] 221 Line Relocation Layer
[0038] 23 Conductive pillars
[0039] 24 Line Department
[0040] 25 coating layers
[0041] 26, 36 Electronic components
[0042] 28, 38 encapsulation layers
[0043] 29,39 Conductive elements
[0044] 8 Anti-warping layer
[0045] 9. Support plate
[0046] H represents thickness. Detailed Implementation
[0047] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification.
[0048] It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the scope of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this application, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.
[0049] Please see Figures 2A to 2E This is a cross-sectional schematic diagram of the first embodiment of the packaging module and its manufacturing method of this application. The packaging module of this application is implemented in a monolithic architecture such as wafer form or panel form, and includes multiple packaging areas.
[0050] like Figure 2A As shown, a carrier plate 9 is provided, on which a plurality of conductive pillars 23 are formed and a plurality of bridging chips 21 are disposed. The plurality of conductive pillars 23 surround the bridging chips 21, wherein a plurality of conductors 210 are bonded to and electrically connected on the bridging chips 21, and the plurality of conductors 210 are spherical, such as solder balls, or columnar, such as copper pillars, solder bumps, or stud conductive parts made by wire bonding machines, but are not limited thereto. In addition, the bridging chip 21 has opposing active and non-active surfaces. The bridging chip 21 is bonded to the carrier plate 9 with its non-active surface, while the active surface has a plurality of electrode pads and a protective film, such as a passivation material, and the conductors 210 are disposed on the electrode pads and embedded in the protective film.
[0051] A covering layer 25 is then formed on the carrier plate 9 to cover the bridging chip 21, the plurality of conductors 210, and the plurality of conductive posts 23. In this embodiment, the covering layer 25 is an insulating material, such as polyimide (PI), dry film, or an encapsulating colloid or molding compound such as epoxy resin. Furthermore, a leveling process is used to expose the end faces of the plurality of conductive posts 23 and the end faces of the plurality of conductors 210 outside the covering layer 25.
[0052] Next, a circuit structure 22 is formed on the covering layer 25, and the circuit structure 22 electrically connects the plurality of conductive pillars 23 and the plurality of conductors 210. The circuit structure 22 includes a plurality of dielectric layers 220 and a plurality of redistribution layers (RDLs) 221 disposed on the dielectric layers 220. Alternatively, the circuit structure 22 may include only a single dielectric layer 220 and a single redistribution layer 221. Furthermore, the material forming the redistribution layer 221 is copper, and the material forming the dielectric layer 220 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), or prepreg (PP).
[0053] Multiple electronic components 26 are then mounted on the circuit structure 22, and an encapsulation layer 28 is formed, for example, by molding, to cover the multiple electronic components 26. The electronic components 26 can be active components, passive components, or a combination of both. In one embodiment, the electronic components 26 are, for example, semiconductor chips such as graphics processing units (GPUs) and high-bandwidth memory (HBM). The electronic components 26 are electrically connected to the circuit structure 22 via multiple conductive bumps such as solder bumps, copper bumps, or others, and at least two of the electronic components 26 can be electrically connected to each other via the bridging chip 21. Furthermore, the encapsulation layer 28 is an insulating material, such as polyimide (PI), dry film, an encapsulating colloid such as epoxy resin, or a molding compound, which can be formed on the circuit structure 22 by lamination or molding. It should be understood that the material of the encapsulation layer 28 may be the same as or different from the material of the covering layer 25. Alternatively, an adhesive primer may be formed first between the electronic component 26 and the circuit structure 22 to cover the plurality of conductive bumps, and then the encapsulation layer 28 may be formed to cover the adhesive primer and the plurality of electronic components 26. The aforementioned adhesive primer may be selectively formed or not formed between the electronic component 26 and the circuit structure 22.
[0054] Accordingly, after the encapsulation layer 28 is formed in the molding process, a plurality of encapsulation units 20 are formed on the carrier plate 9. Each encapsulation unit 20 has a first side 20a and a second side 20b, and includes a circuit structure 22, a plurality of electronic components 26 disposed on the circuit structure 22, and an encapsulation layer 28 covering the electronic components 26. The thickness H of the encapsulation unit 20 is about 900 to 1400 μm (micrometers), and the aspect ratio of the electronic components 26 is between 1.5 and 3.
[0055] like Figure 2B and Figure 2C As shown, an anti-warping layer 8 is provided on the plurality of encapsulation units 20 to obtain the encapsulation module 2 of this application. In this embodiment, an adhesive film is formed on the encapsulation layer 28 of the plurality of encapsulation units 20 by lamination. Then, the plurality of encapsulation units 20 with the adhesive film are moved into an oven for curing to form an anti-warping layer 8 on the plurality of encapsulation units 20. The thickness of the anti-warping layer 8 is 50-100 μm.
[0056] like Figure 2D As shown, the carrier plate 9 can be removed subsequently to provide multiple conductive elements 29 on the second side of the multiple encapsulation units 20. Due to the provision of the anti-warping layer 8, the film stretching and shrinking under reverse stress is used to improve the large warping caused in the original process in response to the structural deformation that may occur when forming the encapsulation layer during the molding process. This enables workability in subsequent process stations (such as the installation of multiple conductive elements) and reduces problems caused by warping.
[0057] In this embodiment, a circuit portion 24 can be formed on the cladding layer 25 to electrically connect the plurality of conductive pillars 23. The circuit portion 24 may also include an insulating layer and a bump under metal layer (UBM) to connect conductive elements 29 such as a plurality of solder bumps or solder balls (of type C4); or, the circuit portion 24 can be formed on the cladding layer 25 through an RDL process to connect the conductive elements 29.
[0058] like Figure 2E As shown, a thinning process can also be performed, such as a polishing operation, to remove the anti-warping layer 8 and part of the encapsulation layer 28 to expose the plurality of electronic components 26, so as to provide good heat dissipation for the plurality of electronic components 26.
[0059] Please see Figures 3A to 3C This is a cross-sectional schematic diagram of the packaging module and its manufacturing method according to the second embodiment of this application. The packaging module of this application is implemented in a monolithic architecture such as wafer form or panel form, and includes multiple packaging areas.
[0060] like Figure 3A As shown, a carrier board 9 is provided, and a circuit structure 32 is formed on the carrier board 9. Then, a plurality of electronic components 36 are disposed on the circuit structure 32, and an encapsulation layer 38 is formed on the circuit structure 32 to cover the plurality of electronic components 36, thereby forming a plurality of encapsulation units 30. The circuit structure 32 includes a plurality of dielectric layers and a plurality of circuit redistribution layers, and the electronic components 36 are active components, passive components, or a combination of both.
[0061] like Figure 3BAs shown, an anti-warping layer 8 is provided on the plurality of encapsulation units 30 to obtain the encapsulation module 3 of this application. In this embodiment, an adhesive film is formed on the encapsulation layer 38 of the plurality of encapsulation units 30 by pressing. Then, the plurality of encapsulation units 30 with the adhesive film are moved into an oven for curing to form an anti-warping layer 8 on the plurality of encapsulation units 30, thereby obtaining the encapsulation module 3 of this application.
[0062] like Figure 3C As shown, the carrier plate 9 can be removed subsequently, and multiple conductive elements 39 are attached to the circuit structure 32 (on the other side where the electronic components 36 are located). Then, a thinning process is performed to remove the anti-warping layer 8 and part of the encapsulation layer 38 through a grinding operation to expose the multiple electronic components 36, so as to provide good heat dissipation for the multiple electronic components 36.
[0063] Through the aforementioned manufacturing method, this application provides a packaging module 2,3, which has a monolithic architecture and includes: a plurality of packaging units 20,30, wherein each packaging unit 20,30 includes a circuit structure 22,32, a plurality of electronic components 26,36 disposed on the circuit structure 22,32 and a packaging layer 28,38 covering the plurality of electronic components 26,36; and an anti-warping layer 8 formed on the plurality of packaging units 20,30 to cover the packaging layer 28,38.
[0064] In one embodiment, each of the packaging units 20 is, for example, a fan-out embedded bridge (FOEB) structure, which further includes a plurality of conductive posts 23 and a bridge chip 21 disposed on the circuit structure 22, a cover layer 25 formed on the circuit structure 22 and covering the plurality of conductive posts 23 and the bridge chip 21, a circuit portion 24 disposed on the cover layer 25, and a plurality of conductive elements 29 disposed on the circuit portion 24. The bridge chip 21 and the plurality of conductive posts 23 are electrically connected to the circuit structure 22. The plurality of conductive posts 23 are embedded in the cover layer 25 and surround the bridge chip 21. The circuit portion 24 is electrically connected to the plurality of conductive posts 23 and the plurality of conductive elements 29.
[0065] In one embodiment, each of the packaging units 30 is, for example, a fan-out multi-chip (FOMCM) structure, which further includes a plurality of conductive elements 39 disposed on the circuit structure 32, and the plurality of conductive elements 39 are electrically connected to the circuit structure 32.
[0066] In summary, the packaging module of this application incorporates an anti-warpage layer on the packaging layer of multiple packaging units in a monolithic architecture. It utilizes the stretching and contraction of the adhesive film under reverse stress to mitigate significant warpage caused by the original manufacturing process. This ensures workability in subsequent process stages and reduces problems caused by warpage. Furthermore, the aforementioned structure eliminates the need for newly developed processes, materials, or purchased equipment. Existing materials, processes, and equipment can address existing industry technical issues, thus avoiding substantial additional cost expenditures.
[0067] The above embodiments are used to illustrate the principles and effects of this application, and are not intended to limit this application. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be as set forth in the claims.
Claims
1. A packaging module, which is a monolithic architecture, characterized in that, include: Multiple packaging units, each including a circuit structure, multiple electronic components disposed on the circuit structure, and a packaging layer covering the multiple electronic components; as well as An anti-warping layer is formed on the plurality of packaging units to cover the packaging layer.
2. The packaging module as described in claim 1, characterized in that, Each of the package units also includes a bridge chip disposed on the circuit structure and electrically connected to the circuit structure.
3. The packaging module as described in claim 2, characterized in that, Each of the packaging units also includes a plurality of conductive posts disposed on the circuit structure and electrically connected to the circuit structure.
4. The packaging module as described in claim 3, characterized in that, Each of the packaging units also includes a covering layer disposed on the circuit structure to cover the bridge chip and the plurality of conductive pillars.
5. The packaging module as described in claim 4, characterized in that, Each of the packaging units also includes a circuit section disposed on the cover layer and electrically connected to the plurality of conductive pillars.
6. The packaging module as described in claim 5, characterized in that, Each of the packaging units also includes a plurality of conductive elements disposed on the circuit section and electrically connected to the circuit section.
7. The packaging module as described in claim 1, characterized in that, Each of the packaging units also includes a plurality of conductive elements disposed on the circuit structure and electrically connected to the circuit structure.
8. The packaging module as described in claim 1, characterized in that, Each of these package units is a fan-out embedded bridge structure or a fan-out multi-chip structure.
9. The packaging module as described in claim 1, characterized in that, The thickness of each of these packaging units is 900–1400 micrometers.
10. The packaging module as described in claim 1, characterized in that, The aspect ratio of this electronic component is 1.5 to 3.
11. The packaging module as described in claim 1, characterized in that, The thickness of the anti-warping layer is 50–100 micrometers.