Photoelectric relay

Abstract

The utility model discloses a photoelectric relay, and belongs to the technical field of photoelectric relays. The photoelectric relay provided by the utility model comprises an IR side structure, a PVG side structure, an MOS side structure, a packaging structure and a buffer end lead frame, the buffer end lead frame comprises a PVG functional area and an MOS functional area, the PVG chip and the PVG functional area are connected through a first bonding wire (gold wire), and the MOS chip and the MOS functional area are connected through a second bonding wire (aluminum wire or copper wire), so that direct bonding wire connection of the PVG chip and the MOS chip is replaced, conduction of heat of the MOS side to the PVG side is effectively prevented, and the heat dissipation capability is improved; all the lead frames are made of thickened copper alloy materials, and the thickness range is 0.127-0.5 mm, so that the current load capacity of the photoelectric relay is effectively improved. According to the photoelectric relay provided by the utility model, the buffer end lead frame is additionally arranged, the lead frame is thickened, differential bonding wires are adopted and the like, so that the problem that the reliability of the existing photoelectric relay is insufficient under the condition of large current due to heat conduction is solved; therefore, the photoelectric relay is suitable for high-power large-current scenes such as electric automobiles and industrial inverters.

Description

Technical Field

[0001] This utility model relates to the field of relay technology, and more specifically, to a photoelectric relay. Background Technology

[0002] Relays are commonly used in circuit control for fault protection and circuit isolation. Their performance directly impacts the safety and stability of the applied equipment. In fields such as electric vehicles and lithium battery protection control boards, bidirectional inverters, programmable logic controllers (PLCs), industrial testing equipment, and power equipment (industrial UPS), high-current mechanical relays are typically chosen for their application circuits. However, mechanical relays achieve circuit switching through mechanical contacts. Over time, these contacts are prone to wear, leading to increased contact resistance and decreased contact reliability. In severe cases, this can cause problems such as arcing and contact adhesion. Furthermore, mechanical relays are susceptible to electromagnetic interference during use, and their large size, noise, and short lifespan limit their application scenarios.

[0003] Optoelectronic relays achieve complete isolation between input and output circuits through optocoupler. This electrical isolation characteristic allows the optoelectronic relay to operate stably even in complex electromagnetic environments. Furthermore, the absence of mechanical contacts in optoelectronic relays avoids problems such as contact wear and arcing. Taiwanese patent TW1551045B discloses a typical optoelectronic relay packaging structure, such as... Figure 1 As shown, it includes a light-emitting element 12 ， 14 photoelectric conversion chips ， and two metal-oxide-semiconductor wafers 16 ， and 18 ， Light-emitting element 12 ， Receives input signals and generates optical signals; photoelectric conversion chip 14 ， Based on the received optical signal, an output voltage control signal is generated to control two metal-oxide-semiconductor wafers 16. ， and 18 ， The on / off state of the photoelectric relay. This is due to the photoelectric conversion chip 14 of the photoelectric relay. ， Metal-Oxygen Semiconductor Wafer 16 ， 18 ， By stitching 19 ， When making electrical connections, and applying this photoelectric relay to high-power, high-current applications, the metal-oxide-semiconductor wafer 16... ， and 18 ， It will generate a lot of heat, which will be transmitted through the wire 19. ， Photoelectric conversion chip 14 ， End conduction leads to photoelectric conversion chip 14 ， The reduced boost pressure consequently affects the reliability of the control. Therefore, as... Figure 1The package structure shown is well-suited for low-power or low-current applications, but not for high-power, high-current applications. To enable the application of this advantageous photoelectric relay in high-power, high-current fields, a specifically designed photoelectric relay is needed. Summary of the Invention

[0004] To overcome the limitations of existing photoelectric relays in terms of current load capacity, which prevents them from being applied to high-power, high-current scenarios such as electric vehicles and lithium battery protection control boards, bidirectional inverters, programmable controllers, industrial testing equipment, and power equipment (industrial UPS), this utility model provides a photoelectric relay and its manufacturing method.

[0005] This invention provides a photoelectric relay, comprising: an IR (Infrared) side structure, a PVG (Photovoltaic Generator) side structure, a MOS (Metal-Oxide-Semiconductor) side structure, and a packaging structure; the packaging structure is used for packaging the IR side structure, the PVG side structure, and the MOS side structure; the IR side structure includes an IR leadframe and an IR chip fixed thereon; the PVG side structure includes a PVG leadframe and a PVG chip fixed thereon; the MOS side structure includes a MOS leadframe and a MOS chip fixed thereon; the IR chip is used to emit light signals, the PVG chip is used to receive the light signals and generate control signals, the control signals are used to drive the MOS chip to switch on and off; the photoelectric relay also includes a buffer leadframe, and the PVG chip and the MOS chip are respectively wire-bonded to the buffer leadframe via bonding wires.

[0006] The photoelectric relay provided by this invention adds a buffer lead frame between the PVG chip and the MOS chip. This buffer lead frame is bonded to both the PVG chip and the MOS chip via bonding wires, replacing the direct electrical connection between the two chips. This reduces the heat generated by the MOS chip during operation from being conducted to the PVG chip via the bonding wires, preventing the PVG chip from losing its functionality due to overheating and enhancing its stability and reliability. Simultaneously, the buffer lead frame increases the heat dissipation area, improving heat dissipation and increasing the current load capacity of the photoelectric relay, making it suitable for high-power, high-current applications.

[0007] Furthermore, the PVG lead frame includes a PVG base island and PVG base island support ribs, and the MOS lead frame includes a MOS base island and MOS pins; the PVG chip is fixed on the PVG base island, and the MOS chip is fixed on the MOS base island.

[0008] Furthermore, the IR lead frame has a first positioning hole, and the PVG lead frame has a second positioning hole; the IR lead frame and the PVG lead frame are positioned face-to-face through the first positioning hole and the second positioning hole to ensure that the IR chip and the PVG chip are positioned opposite each other and aligned at the center.

[0009] Furthermore, the buffer end lead frame includes a PVG functional region and a MOS functional region, which are located at opposite ends of the buffer end lead frame; the bonding wires include a first bonding wire and a second bonding wire; the PVG chip and the PVG functional region are bonded together via the first bonding wire, and the MOS chip and the MOS functional region are bonded together via the second bonding wire.

[0010] Furthermore, the first bonding wire is a gold wire, and the second bonding wire is an aluminum wire or a copper wire.

[0011] Furthermore, the IR chip and the IR lead frame are bonded together by gold wire bonding.

[0012] The photoelectric relay provided by this utility model has relatively small voltage and current when the IR chip and the PVG chip are working, and gold wire is used for internal bonding connection; the voltage and current when the MOS chip is working is relatively large, and aluminum wire or copper wire is used for bonding connection between the MOS chip and the MOS functional area. On the one hand, this improves the load capacity of the bonding wire, and on the other hand, it reduces the cost.

[0013] Furthermore, the packaging structure includes a first molding die and a second molding die; the first molding die encapsulates the IR chip, the PVG chip, and the PVG functional area to form a first molding die structure; the second molding die encapsulates the MOS chip, the MOS functional area, and the first molding die structure.

[0014] Furthermore, the MOS base island includes a first MOS base island and a second MOS base island, and the MOS chip includes a first MOS chip and a second MOS chip; the first MOS chip is fixed on the first MOS base island, and the second MOS chip is fixed on the second MOS base island.

[0015] Furthermore, the lower surface of the first MOS chip is the drain of the first MOS chip, the lower surface of the second MOS chip is the drain of the second MOS chip, the upper surface of the first MOS base island is the drain pin of the first MOS chip, and the upper surface of the second MOS base island is the drain pin of the second MOS chip; the IR chip is fixed on the IR lead frame using non-conductive adhesive, and the PVG chip is fixed on the PVG base island using non-conductive adhesive; the first MOS chip is fixed on the first MOS base island using conductive adhesive, and the lower surface of the first MOS chip and the upper surface of the first MOS base island are electrically connected; the second MOS chip is fixed on the second MOS base island using conductive adhesive, and the lower surface of the second MOS chip and the upper surface of the second MOS base island are electrically connected.

[0016] Furthermore, the thickness of the IR lead frame, the PVG lead frame, the MOS lead frame, and the buffer end lead frame are all greater than 0.127 mm and less than 0.5 mm.

[0017] The photoelectric relay provided by this utility model has its IR lead frame, PVG lead frame, MOS lead frame and buffer end lead frame all made of thickened materials, which improves the voltage and current load capacity of the photoelectric relay and enables it to be applied to high power and high current scenarios.

[0018] Furthermore, the first molding compound is a white or transparent adhesive, made of a white or transparent epoxy resin composite material; the second molding compound is a black adhesive, made of a black epoxy resin composite material; wherein, the light transmittance of the first molding compound is greater than 90%, and the light absorption rate of the second molding compound is greater than 90%.

[0019] Furthermore, the rated current range of the photoelectric relay is 6A~400A, and the rated voltage range of the photoelectric relay is 20V~6500V.

[0020] It should be noted that the photoelectric relay provided by this invention is a single-channel structure, that is, it achieves control of two MOS chips through the cooperation of one IR chip and one PVG chip. Based on this, it is theoretically possible to form a multi-channel structure by increasing the number of corresponding components. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments of this utility model will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the circuit structure of a photoelectric relay provided in the prior art;

[0023] Figure 2 This is a three-dimensional schematic diagram of the relationship between the IR side structure, PVG side structure, MOS side structure and buffer end lead frame in one embodiment of this utility model;

[0024] Figure 3 This is another perspective schematic diagram of the cooperation relationship between the IR side structure, PVG side structure, MOS side structure and buffer end lead frame in one embodiment of this utility model;

[0025] Figure 4 This is a schematic diagram of the IR side structure in one embodiment of the present invention;

[0026] Figure 5 This is a schematic diagram showing the relationship between the PVG side structure, the MOS side structure, and the buffer end lead frame in one embodiment of this utility model;

[0027] Figure 6 In one embodiment of this utility model, based on Figure 3 A schematic diagram of the first molding structure formed by molding and curing using a first molding mold;

[0028] Figure 7 In one embodiment of this utility model, based on Figure 6 A schematic diagram of the structure after molding using the second molding die;

[0029] Figure 8 This is a schematic diagram of the IR side structure after the IR chip is installed in one embodiment of the present invention;

[0030] Figure 9 This is a schematic diagram of the structure after wire bonding using the first bonding wire in one embodiment of the present invention;

[0031] Figure 10 This is a schematic diagram of the structure after wire bonding using the second bonding wire in one embodiment of the present invention;

[0032] Figure 11 This is a schematic diagram of the structure after curing using a second molding die in one embodiment of the present invention.

[0033] Reference numerals in the background art:

[0034] 10 ， 12. Photoelectric relays; ， 14 Light-emitting elements; ， Photoelectric conversion chip; 16 ， and 18 ，Two metal-oxide-semiconductor (MOS) wafers; 19 ， , wiring;

[0035] Reference numerals in the detailed embodiments:

[0036] 1. IR leadframe; 2. PVG leadframe; 3. MOS leadframe; 4. Buffer leadframe; 5. PVG chip; 6. IR chip; 7. MOS chip; 8. First molding compound; 9. Second molding compound; 10. First bonding wire; 11. Second bonding wire; 12. Gold wire;

[0037] 3a. First MOS lead frame; 3b. Second MOS lead frame;

[0038] 7a. First MOS chip; 7b. Second MOS chip;

[0039] 10a. Lower first bond line; 10b. Upper first bond line; 10c. Middle first bond line;

[0040] 11a. Lower second bond line; 11b. Upper second bond line; 11c. Middle second bond line;

[0041] 21. PVG base island; 22. PVG base island support reinforcement;

[0042] 31. MOS base island; 32. MOS pin;

[0043] 41. S-pole of buffer leadframe; 42. G-pole of buffer leadframe; 43. Residual support rib of buffer leadframe; 44. PVG functional area; 45. MOS functional area;

[0044] 22a, First PVG base island support reinforcement; 22b, Second PVG base island support reinforcement;

[0045] 31a, First MOS base island; 31b, Second MOS base island;

[0046] 32a, D pin of the first MOS chip; 32b, D pin of the second MOS chip;

[0047] 42a. Lower buffer end lead frame G pole; 42b. Upper buffer end lead frame G pole;

[0048] 43a. Lower buffer end conductor frame support rib; 43b. Upper buffer end conductor frame support rib. Detailed Implementation

[0049] The technical solution of this utility model will be clearly and completely described below with reference to the accompanying drawings and embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the scope of protection of this utility model.

[0050] In the description of this utility model, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0051] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0052] like Figure 2 , Figure 3 , Figure 9 and Figure 10 As shown in one embodiment of the present invention, a photoelectric relay includes: an IR-side structure, a PVG-side structure, a MOS-side structure, and a packaging structure; the packaging structure is used for packaging the IR-side structure, the PVG-side structure, and the MOS-side structure; the IR-side structure includes an IR lead frame 1 and an IR chip 6 fixed thereon; the PVG-side structure includes a PVG lead frame 2 and a PVG chip 5 fixed thereon; the MOS-side structure includes a MOS lead frame 3 and a MOS chip 7 fixed thereon; the IR chip 6 is used to emit an optical signal, the PVG chip 5 is used to receive the optical signal and generate a control signal, the control signal being used to drive the MOS chip 7 to switch on and off; it also includes a buffer lead frame 4, the PVG chip 5 and the MOS chip 7 being wire-bonded to the buffer lead frame 4 via a first bonding wire 10 and a second bonding wire 11, respectively.

[0053] In this example, the first bonding wire 10 is preferably a gold wire; the second bonding wire 11 can be an aluminum wire or a copper wire, preferably a copper wire, for bonding the MOS chip 7. Using copper wire to electrically connect the MOS chip improves the current load capacity of the bonding wire and reduces the cost.

[0054] In this example, the IR lead frame 1 has a first positioning hole (not shown), and the PVG lead frame 2 has a second positioning hole (not shown). The first positioning hole includes four positioning holes located at the four corners of the IR lead frame 1, and the second positioning hole includes four positioning holes located at the four corners of the PVG lead frame 2. The IR lead frame 1 and the PVG lead frame 2 are positioned face-to-face through the first and second positioning holes, that is, through the cooperation of two sets of eight positioning holes, the center point of the IR lead frame 1 and the center point of the PVG lead frame 2 are aligned. The IR lead frame 1 and the PVG lead frame 2 are adjusted according to the height of the IR chip 6 and the PVG chip 5. The distance between the IR lead frame 1 and the PVG lead frame 2 is controlled by the size of the conical positioning pins (not shown) and the positioning holes at the four corners, ensuring that the distance between the IR lead frame 1 and the PVG lead frame 2 is greater than the sum of the heights of the IR chip 6 and the PVG chip 5. Based on the dimensions and center points of the IR chip 6 and the PVG chip 5, their coordinate positions on the IR lead frame 1 and the PVG lead frame 2 are determined, ensuring that the IR chip 6 and the PVG chip 5 are relatively aligned and centered, allowing the PVG chip to receive the optical signal emitted by the IR chip over a larger area, reducing the probability of erroneous communication. Typically, if the center error between the IR chip 6 and the PVG chip 5 is 25µm, the communication success rate between the IR chip 6 and the PVG chip 5 is approximately 95%; if the center error between the IR chip 6 and the PVG chip 5 is 50µm, the communication success rate is only approximately 85%.

[0055] like Figure 5As shown, in one embodiment of this utility model, the PVG lead frame 2 includes a PVG base island 21 and PVG base island support ribs 22. The PVG base island 21 is used to support the PVG chip 5. The PVG chip 5 is fixed on the PVG base island 21 using non-conductive adhesive (not shown). The PVG base island support ribs 22 are used to support the PVG lead frame 2. The MOS lead frame 3 includes a MOS base island 31 and MOS pins 32. The MOS base island 31 includes a first MOS base island 31a and a second MOS base island 31b. The MOS pins 32 include a first MOS chip drain pin 32a and a second MOS chip drain pin 32b. OS chip D pin 32b; the MOS chip 7 includes a first MOS chip 7a and a second MOS chip 7b; the lower surface of the first MOS chip 7a is the drain of the first MOS chip 7a, and the lower surface of the second MOS chip 7b is the drain of the second MOS chip 7b; the first MOS chip 7a and the second MOS chip 7b are fixed and electrically connected to the first MOS base island 31a and the second MOS base island 31b respectively with conductive adhesive (not shown), and are electrically connected to the outside through the first MOS chip D pin 32a and the second MOS chip D pin 32b respectively.

[0056] In this example, Figure 5 The first MOS chip drain pin 32a and the second MOS chip drain pin 32b shown both have two pins. There is no specific limit to the number of pins 32a and 32b. The number of pins can be adjusted according to actual needs. For example, each pin 32a and pin 32b can be set to one.

[0057] In this example, there are no particular limitations on the types of non-conductive and conductive adhesives. For instance, non-conductive adhesives can be epoxy resin, silicone, polyimide, or other insulating fixatives; conductive adhesives can be copper-filled epoxy resin, silver-filled epoxy resin, or other non-insulating fixatives.

[0058] like Figure 5 , Figure 9 and Figure 10As shown, in one embodiment of this utility model, the buffer end lead frame 4 includes a buffer end lead frame S pole 41, a buffer end lead frame G pole 42, and a buffer end lead frame residual support rib 43. The buffer end lead frame G pole 42 includes a lower buffer end lead frame G pole 42a and an upper buffer end lead frame G pole 42b. The structure of the buffer end lead frame 4 can be divided into a PVG functional area 44 and a MOS functional area 45. The PVG functional area 44 and the MOS functional area 45 are located at the left and right ends of the buffer end lead frame 4, respectively. The PVG functional area 44 includes... The left end of the buffer lead frame S pole 41, the left end of the lower buffer lead frame G pole 42a, and the left end of the upper buffer lead frame G pole 42b are included. The MOS functional region 45 specifically includes the right end of the buffer lead frame S pole 41, the right end of the lower buffer lead frame G pole 42a, and the right end of the upper buffer lead frame G pole 42b. The PVG chip 5 and the PVG functional region 44 can be wire bonded by the first bonding line 10 or the second bonding line 11. The MOS chip 7 and the MOS functional region 45 are wire bonded by the second bonding line 11.

[0059] In a preferred embodiment, the PVG chip 5 and the PVG functional area 44 are wire-bonded via the first bonding line 10. The first bonding line 10 includes a lower first bonding line 10a, an upper first bonding line 10b, and a middle first bonding line 10c. The second bonding line 11 includes a lower second bonding line 11a, an upper second bonding line 11b, and a middle second bonding line 11c. The lower first bonding line 10a is used to wire-bond the gate output of the PVG chip to the left end of the lower buffer leadframe G pole 42a, and the upper first bonding line 10b is used to wire-bond the other gate output of the PVG chip to the upper buffer leadframe G pole 42a. The left end of 2b is wire bonded, and the source output of the PVG chip is wire bonded to the left end of the S pole 41 of the buffer lead frame using the middle first bonding line 10c; the gate of the first MOS chip 7a is wire bonded to the right end of the gate of the lower buffer lead frame 42a using the lower second bonding line 11a; the gate of the second MOS chip 7b is wire bonded to the right end of the gate of the upper buffer lead frame 42b using the upper second bonding line 11b; and the source poles of the first MOS chip 7a and the second MOS chip 7b are wire bonded to the right end of the S pole 41 of the buffer lead frame using the middle second bonding line 10c.

[0060] Using the buffer leadframe 4 provided in this example, the PVG chip 5 and the MOS chip 7 are wire-bonded to the buffer leadframe 4 via the first bonding wire 10 and the second bonding wire 11, respectively. This effectively reduces the heat generated by the MOS chip 7 during operation from being conducted to the PVG chip 5 through the bonding wires, preventing the PVG chip 5 from losing its functionality due to overheating, thus enhancing its stability and reliability. Simultaneously, the buffer leadframe 4 increases the heat dissipation area, improving the heat dissipation effect and enhancing the current load capacity of the photoelectric relay, making it applicable to high-power, high-current scenarios.

[0061] like Figure 8 As shown in one embodiment of this utility model, the IR chip 6 and the IR lead frame 1 are wire bonded together by gold wire 12. The welding position of the gold wire 12 in the figure is only for illustrative purposes, and the welding position of the gold wire 12 is not specifically limited, as long as the power supply of the IR chip 6 is guaranteed. According to actual needs, the gold wire 12 can be wire bonded to other pins of the IR lead frame 1. In this example, the IR lead frame 1 has 5 pins. The number of pins of the IR lead frame 1 is not specifically limited, and the number of pins can be adjusted according to actual needs.

[0062] like Figure 6 , Figure 7 and Figure 11 As shown, in one embodiment of the present invention, the packaging structure includes a first molding die 8 and a second molding die 9; the first molding die 8 molds the IR chip 6, the PVG chip 5 and the PVG functional area 44, and forms a first molding structure after baking and curing; the second molding die 9 molds the MOS chip 7, the MOS functional area 45 and the first molding structure, and forms the entire packaging structure after baking and curing.

[0063] In this example, the first molding die 8 can be white glue or transparent glue, preferably white glue, and is made of white epoxy resin composite material; the second molding die 9 is black glue, and is made of black epoxy resin composite material; wherein, the light transmittance of the first molding die 8 is greater than 90%, ensuring that the light signal emitted by the IR chip can be received by the PVG chip without obstruction; the light absorption rate or light blocking rate of the second molding die 9 is greater than 90%, so as to protect the chip and circuit of the entire product and facilitate subsequent laser printing.

[0064] In this example, the IR leadframe 1, the PVG leadframe 2, the MOS leadframe 3, and the buffer leadframe 4 are all thickened, preferably within a thickness range of greater than 0.127 mm and less than 0.5 mm. Thickening the leadframes improves their current load capacity, making them suitable for high-current applications. It is important to emphasize that there is no specific upper limit to the thickness of the leadframes; the chosen upper limit of 0.5 mm is a preferred range to ensure the miniaturization and low-cost requirements of the photoelectric relay. Depending on the specific application, the leadframe thickness can also be greater than 0.5 mm. The material of the leadframes is not limited, as long as its conductivity meets the requirements. Highly conductive metals are generally preferred; in this example, a C192 copper alloy is preferred.

[0065] In this example, the rated current range of the photoelectric relay is 6A to 400A, and the rated voltage range is 20V to 6500V. Compared with the prior art, the current load capacity of the photoelectric relay provided by this invention is significantly improved, that is, it can withstand a current of more than 6A, which is one of the main contributions of the photoelectric relay of this invention.

[0066] The photoelectric relay provided in this example, by adding a buffer lead frame 4 between the PVG chip 5 and the MOS chip 7 instead of directly connecting the PVG chip 5 and the MOS chip 7 via bonding wires, effectively reduces the heat generated by the MOS chip 4 during operation from being conducted to the PVG chip 7 through the bonding wires, thus preventing the PVG chip 7 from losing its functionality due to excessive temperature. At the same time, the IR lead frame 1, the PVG lead frame 2, the MOS lead frame 3, and the buffer lead frame 4 are all thickened, improving the current load capacity of the photoelectric relay. Through the above design, the photoelectric relay can be applied to high-power, high-current scenarios.

[0067] The above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model, and should all be included within the protection scope of this utility model.

Claims

1. A photoelectric relay, comprising: IR-side structure, PVG-side structure, MOS-side structure, and packaging structure; The packaging structure is used for packaging the IR-side structure, the PVG-side structure, and the MOS-side structure; The IR side structure includes an IR lead frame and an IR chip fixed thereon; The PVG side structure includes a PVG lead frame and a PVG chip fixed thereon; The MOS-side structure includes a MOS lead frame and a MOS chip fixed thereon; The IR chip is used to emit optical signals, the PVG chip is used to receive the optical signals and generate control signals, and the control signals are used to drive the MOS chip to switch on and off. The feature is that it further includes a buffer end lead frame, wherein the PVG chip and the MOS chip are respectively bonded to the buffer end lead frame via bonding wires.

2. The photoelectric relay according to claim 1, characterized in that: The PVG lead frame includes a PVG base island and PVG base island support ribs, and the MOS lead frame includes a MOS base island and MOS pins; The PVG chip is fixed on the PVG base island, and the MOS chip is fixed on the MOS base island.

3. The photoelectric relay according to claim 1, characterized in that: The IR lead frame has a first positioning hole, and the PVG lead frame has a second positioning hole; The IR lead frame and the PVG lead frame are positioned face-to-face through the first positioning hole and the second positioning hole to ensure that the IR chip and the PVG chip are positioned opposite each other and aligned at the center.

4. The photoelectric relay according to claim 1, characterized in that: The buffer end leadframe includes a PVG functional area and a MOS functional area, which are located at opposite ends of the buffer end leadframe. The bonding wires include a first bonding wire and a second bonding wire; The PVG chip and the PVG functional area are bonded together by the first bonding line, and the MOS chip and the MOS functional area are bonded together by the second bonding line.

5. The photoelectric relay according to claim 4, characterized in that: The first bonding wire is a gold wire, and the second bonding wire is an aluminum wire or a copper wire.

6. The photoelectric relay according to claim 1, characterized in that: The IR chip and the IR lead frame are bonded together by gold wire bonding.

7. The photoelectric relay according to claim 4, characterized in that: The packaging structure includes a first molding die and a second molding die; The first molding compound encapsulates the IR chip, the PVG chip, and the PVG functional area to form a first molding compound structure; The second molding compound encapsulates the MOS chip, the MOS functional area, and the first molding compound structure.

8. The photoelectric relay according to claim 2, characterized in that: The MOS base island includes a first MOS base island and a second MOS base island, and the MOS chip includes a first MOS chip and a second MOS chip; The first MOS chip is fixed on the first MOS base island, and the second MOS chip is fixed on the second MOS base island.

9. The photoelectric relay according to claim 8, characterized in that: The lower surface of the first MOS chip is the drain of the first MOS chip, and the lower surface of the second MOS chip is the drain of the second MOS chip; The IR chip is fixed on the IR lead frame using non-conductive adhesive, and the PVG chip is fixed on the PVG base island using non-conductive adhesive. The first MOS chip is fixed to the first MOS base island using conductive adhesive, and the lower surface of the first MOS chip is electrically connected to the upper surface of the first MOS base island. The second MOS chip is fixed to the second MOS base island using conductive adhesive, and the lower surface of the second MOS chip and the upper surface of the second MOS base island are electrically connected.

10. The photoelectric relay according to claim 1, characterized in that: The thickness of the IR leadframe, the PVG leadframe, the MOS leadframe, and the buffer end leadframe is greater than 0.127 mm and less than 0.5 mm.

11. The photoelectric relay according to claim 7, characterized in that: The first molding compound is white glue or transparent glue, made of white or transparent epoxy resin composite material; The second molding compound is made of black epoxy resin composite material; The first molding die has a light transmittance of more than 90%, and the second molding die has a light absorption rate of more than 90%.

12. The photoelectric relay according to any one of claims 1-11, characterized in that: The rated current range of the photoelectric relay is 6A~400A, and the rated voltage range of the photoelectric relay is 20V~6500V.

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