Improved siC-IGBT hybrid power module driving circuit

Abstract

The utility model relates to drive circuit technical field, concretely is a kind of improved SiC-IGBT hybrid power module drive circuit, comprising: MCU, drive chip, delay circuit A, delay circuit B, SiC transistor, IGBT transistor;The signal output end of drive chip is used to receive the PWM control signal of MCU;The signal output end of drive chip is two-way output, one way is connected the gate of SiC transistor through delay circuit A, drive resistance R1, another way is connected the base of IGBT transistor through delay circuit B, drive resistance R3.Drive chip output one way PWM signal realizes two-way output through delay circuit, one way drive IGBT transistor, one way drive SiC transistor, delay circuit can adjust switch sequence, switch delay time, and external push-pull circuit of drive chip self-attached can realize the adjustment of driving power supply and the enhancement of driving capacity.

Description

Technical Field

[0001] This utility model relates to the field of drive circuit technology, specifically an improved SiC-IGBT hybrid power module drive circuit. Background Technology

[0002] With the development of new energy vehicle technology, the requirements for the power level and efficiency of motor controllers are becoming increasingly higher. Traditional Si-based IGBT modules have limited output capabilities, high losses, low efficiency, and the switching frequency should not be too high. Therefore, SiC power modules have been extensively researched and used. SiC power modules can greatly improve the power level, reduce losses, and improve system efficiency, thereby increasing the driving range. However, SiC power modules are very expensive and in short supply. In order to solve the above problems, hybrid power modules combining SiC transistors and IGBT transistors have been gradually developed. The overall performance of hybrid modules is between that of IGBTs and SiC.

[0003] Existing adaptive hybrid power module drive circuits, such as Figure 1 As shown, Si-based IGBTs and SiC transistors use the same drive path, the drive power supply is not adjustable, and the switching sequence and switching delay are not adjustable, which cannot fully utilize the advantages of hybrid modules.

[0004] Therefore, in order to better utilize the optimal performance of each hybrid power module, a dedicated drive circuit needs to be developed to match them. The dedicated drive circuit should have the following requirements: (1) adjustable power supply voltage for SiC and IGBT; (2) adjustable switching sequence for SiC and IGBT; and (3) adjustable switching delay time for SiC and IGBT. In response to the above requirements, this utility model provides an improved SiC-IGBT hybrid power module drive circuit. Utility Model Content

[0005] The purpose of this invention is to provide an improved SiC-IGBT hybrid power module drive circuit to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, this utility model provides the following technical solution:

[0007] An improved SiC-IGBT hybrid power module driver circuit includes: an MCU, a driver chip, a delay circuit A, a delay circuit B, a SiC transistor, and an IGBT transistor;

[0008] The signal input terminal of the driver chip is used to receive the PWM control signal from the MCU;

[0009] The signal output terminal of the driver chip is divided into two paths. One path is connected to the gate of the SiC transistor through the delay circuit A and the driving resistor R1, and the other path is connected to the base of the IGBT transistor through the IGBT transistor and the driving resistor R3.

[0010] The drain of the SiC transistor is connected in series with the collector of the IGBT transistor and then connected to the external bus power supply DC+.

[0011] The source of the SiC transistor and the emitter of the IGBT transistor are connected in series and then connected to the external bus power supply DC-.

[0012] A resistor R2 and a gate capacitor C1 are connected in parallel between the gate and source of the SiC transistor.

[0013] A resistor R4 and a gate capacitor C2 are connected in parallel between the base and emitter of the IGBT transistor.

[0014] Preferably, the power supply voltage of the driver chip is supplied through VCC, and the negative voltage is supplied through VEE.

[0015] Preferably, the delay circuit A includes: diode D1, diode D2, diode D5, resistor R6, resistor R5, capacitor C3, and capacitor C4;

[0016] The N-terminal of diode D1 is connected to the P-terminal of diode D2 and then connected to the signal output terminal of the driver chip.

[0017] The P-terminal of the diode D1 is connected in series with the resistor R6 and then connected to one end of the driving resistor R1.

[0018] The N-terminal of diode D2 is connected to one end of driving resistor R1 via resistor R5 and the P-terminal of diode D5.

[0019] One end of the capacitor C3 is connected to the common terminal of the diode D1 and the resistor R6, and the other end is grounded;

[0020] One end of the capacitor C4 is connected to the common terminal of the resistor R5 and the P terminal of the diode D5, and the other end is grounded.

[0021] Preferably, the delay circuit B includes: diode D3, diode D4, diode D6, resistor R9, resistor R8, capacitor C5, and capacitor C6;

[0022] The N-terminal of diode D3 is connected to the P-terminal of diode D4 and then connected to the signal output terminal of the driver chip.

[0023] The P-terminal of the diode D3 is connected in series with the resistor R9 and then connected to one end of the driving resistor R3.

[0024] The N-terminal of diode D4 is connected to one end of driving resistor R3 via resistor R8 and the P-terminal of diode D6.

[0025] One end of the capacitor C5 is connected to the common terminal of the diode D3 and the resistor R9, and the other end is grounded;

[0026] One end of the capacitor C6 is connected to the common terminal of the resistor R8 and the P terminal of the diode D6, and the other end is grounded.

[0027] Compared with the prior art, the beneficial effects of this utility model are as follows: In this improved SiC-IGBT hybrid power module drive circuit, the MCU outputs PWM according to the control algorithm, and the isolated drive chip realizes the basic drive function. One PWM signal output by the drive chip is used to realize two outputs through the delay circuit, one of which drives the IGBT transistor and the other drives the SiC transistor. The delay circuit can adjust the switching sequence and the switching delay time. The push-pull circuit built into the drive chip can realize the adjustment of the drive power supply and the enhancement of the drive capability. Attached Figure Description

[0028] Figure 1 A schematic diagram of the discrete drive circuit for a traditional hybrid power module in the prior art;

[0029] Figure 2 This is a schematic diagram of the discrete drive circuit for the hybrid power module of this utility model;

[0030] Figure 3 This is an example of a PWM waveform diagram showing the switching sequence controlled by an MCU in this invention;

[0031] Figure 4 This is an example of a PWM waveform diagram showing the MCU controlling the switch delay time in this invention. Detailed Implementation

[0032] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0033] In the description of this patent, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected," "linked," and "set up" should be interpreted broadly. For example, they can refer to a fixed connection or setting, a detachable connection or setting, or an integral connection or setting. Those skilled in the art can understand the specific meaning of the above terms in this patent according to the specific circumstances.

[0034] An improved SiC-IGBT hybrid power module drive circuit, such as Figure 2 As shown, the system includes: an MCU, a driver chip, delay circuit A, delay circuit B, a SiC transistor, and an IGBT transistor. The signal input terminal of the driver chip is used to receive the PWM control signal from the MCU. The signal output terminal of the driver chip is split into two paths: one path is connected to the gate of the SiC transistor through the delay circuit A and the driving resistor R1, and the other path is connected to the base of the IGBT transistor through the IGBT transistor and the driving resistor R3. The power supply voltage of the driver chip is supplied through VCC, and the negative voltage is supplied through VEE. The drain of the SiC transistor and the collector of the IGBT transistor are connected in series and then connected to the external bus power supply DC+. The source of the SiC transistor and the emitter of the IGBT transistor are connected in series and then connected to the external bus power supply DC-. A resistor R2 and a gate capacitor C1 are connected in parallel between the gate and the source of the SiC transistor. A resistor R4 and a gate capacitor C2 are connected in parallel between the base and the emitter of the IGBT transistor. Specifically, the delay circuit A includes: diodes D1, D2, and D5; resistors R6 and R5; capacitors C3 and C4; the N-terminal of diode D1 is connected to the P-terminal of diode D2 and then to the signal output terminal of the driver chip; the P-terminal of diode D1 is connected in series with resistor R6 and then to one end of the driver resistor R1; the N-terminal of diode D2 passes through resistor R5 and the P-terminal of diode D5, and then the N-terminal of diode D5 is connected to one end of the driver resistor R1; one end of capacitor C3 is connected to the common terminal of the P-terminal of diode D1 and resistor R6, and the other end is grounded; one end of capacitor C4 is connected to the common terminal of resistor R5 and the P-terminal of diode D5, and the other end is grounded. The delay circuit B includes: diodes D3, D4, and D6; resistors R9 and R8; capacitors C5 and C6; the N-terminal of diode D3 is connected to the P-terminal of diode D4 and then connected to the signal output terminal of the driver chip; the P-terminal of diode D3 is connected in series with resistor R9 and then connected to one end of the driver resistor R3; the N-terminal of diode D4 is connected to one end of the driver resistor R3 via resistor R8 and the P-terminal of diode D6; one end of capacitor C5 is connected to the common terminal of the P-terminal of diode D3 and resistor R9, and the other end is grounded; one end of capacitor C6 is connected to the common terminal of resistor R8 and the P-terminal of diode D6, and the other end is grounded.

[0035] In this embodiment, the driver chip can be a commercially available chip with built-in push-free circuitry, used for controlling the drive power supply of VCC and VEE. Those skilled in the art can easily understand this from the existing technology, so it will not be described in detail here.

[0036] Its working principle is as follows:

[0037] Description of delay circuit A and delay circuit B:

[0038] Wherein: D1, D2, D5, R5, R6, C3, C4 constitute the peripheral delay circuit A of the SiC transistor; D3, D4, D6, R8, R9, C5, C6 constitute the peripheral delay circuit B of the IGBT transistor;

[0039] The specific coordination is as follows:

[0040] The turn-on sequence and delay time of SiC transistors and IGBT transistors are controlled by D2, D5, R5, C4, D4, D6, R8, and C6 (ignoring diode voltage drop).

[0041] The turn-on delay time of the SiC transistor is:

[0042] The turn-on delay time of the IGBT transistor is:

[0043] The time difference between the two: *

[0044] The turn-off sequence and delay time of SiC transistors and IGBT transistors are controlled by D1, R6, C3, D3, R9, and C5.

[0045] The delay time of the SiC transistor is:

[0046] The delay time of the IGBT transistor is:

[0047] Time difference between the two *

[0048] SiC transistor drive circuit:

[0049] Opening circuit: When the PWM signal sent by the MCU is high level, it flows through the driver chip for amplification and isolation, is delayed by D2, R5, C4 and D5, and then enters the gate of the SiC transistor through the drive resistor R1 to charge the gate capacitor C1 of the SiC transistor.

[0050] Shutdown circuit: When the PWM signal sent by the MCU is low, it flows through the driver chip for amplification and isolation, is delayed by D1, R6, and C3, and then enters the gate of the SiC transistor through the drive resistor R1 to discharge the gate capacitor C1 of the SiC transistor.

[0051] The driver chip provides signal isolation and power enhancement, the peripheral delay circuit controls the delay time, and the driver resistor R1 and gate capacitor C1 control the driving switching speed.

[0052] IGBT transistor drive circuit:

[0053] Opening circuit: When the PWM signal sent by the MCU is high level, it flows through the driver chip for amplification and isolation, is delayed by D4, R8, C6 and D6, and then enters the gate of the IGBT transistor through the drive resistor R3 to charge the gate capacitor C2 of the IGBT transistor.

[0054] Shutdown circuit: When the PWM signal sent by the MCU is low, it flows through the driver chip for amplification and isolation, is delayed by D3, R9, and C5, and then enters the gate of the IGBT transistor through the drive resistor R3 to discharge the gate capacitor C2 of the IGBT transistor.

[0055] Delay circuits can control the following switching sequence and switching time, specifically as follows: Figure 3 and Figure 4 As shown:

[0056] Switch logic description:

[0057] The PWM signal emitted by the MCU undergoes switching logic processing via an external delay circuit, as detailed below:

[0058] when Execution Figure 3 Configuration 1 in the middle;

[0059] when Execute at time Figure 3 Configuration 2 in the middle;

[0060] when Execution Figure 3 Configuration 3 in the middle;

[0061] when Execute at time Figure 3 Configuration 4 in the middle.

[0062] Switch delay time description:

[0063] The PWM signal emitted by the MCU is controlled by an external delay circuit for switching delay time, as follows:

[0064] Opening delay time affected Control, among which The size is calculated according to the formula above;

[0065] Shutdown delay time is affected Control, among which The size is calculated according to the formula above.

[0066] The driver chip performs signal isolation and power enhancement, the peripheral delay circuit controls the delay time, and the driver resistor R3 and gate capacitor C2 control the driving switching speed.

[0067] The method includes the following steps:

[0068] (1) In this embodiment, the output current is used as the basis for switching the switch configuration, but junction temperature, bus voltage and other conditions can also be used.

[0069] (2) The MCU receives the sampling signal and the drive command and outputs the PWM signal;

[0070] (3) The MCU outputs the PWM signal normally and drives the chip to receive the PWM control signal from the MCU according to the sampling result. After isolation and amplification, the signal is sent to the delay circuits A and B.

[0071] (4) When the sampled current is less than the set current threshold X, the current switching on and off is executed according to strategy A;

[0072] (5) The MCU continues to run, and when it detects that the output current is greater than X+10A, it executes strategy B;

[0073] (6) The MCU continues to run, and when it detects that the output current is less than X-10A, it executes strategy A;

[0074] (7) And so on.

[0075] The foregoing has shown and described the basic principles, main features, and advantages of this utility model. Those skilled in the art should understand that this utility model is not limited to the above embodiments. The embodiments and descriptions in the specification are merely preferred examples and are not intended to limit the utility model. Various changes and modifications can be made to this utility model without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed utility model. The scope of protection of this utility model is defined by the appended claims and their equivalents.

Claims

1. An improved SiC-IGBT hybrid power module drive circuit, characterized in that, include: MCU, driver chip, delay circuit A, delay circuit B, SiC transistor, IGBT transistor; The signal input terminal of the driver chip is used to receive the PWM control signal from the MCU; The signal output terminal of the driver chip is divided into two paths. One path is connected to the gate of the SiC transistor through the delay circuit A and the driving resistor R1, and the other path is connected to the base of the IGBT transistor through the IGBT transistor and the driving resistor R3. The drain of the SiC transistor and the collector of the IGBT transistor are connected in series and then connected to the external bus power supply DC+. The source of the SiC transistor and the emitter of the IGBT transistor are connected in series and then connected to the external bus power supply DC-. A resistor R2 and a gate capacitor C1 are connected in parallel between the gate and source of the SiC transistor. A resistor R4 and a gate capacitor C2 are connected in parallel between the base and emitter of the IGBT transistor.

2. The improved SiC-IGBT hybrid power module drive circuit according to claim 1, characterized in that: The power supply voltage of the driver chip is supplied through VCC, and the negative voltage is supplied through VEE.

3. The improved SiC-IGBT hybrid power module drive circuit according to claim 1, characterized in that: The delay circuit A includes: diode D1, diode D2, diode D5, resistor R6, resistor R5, capacitor C3, and capacitor C4; The N-terminal of diode D1 is connected to the P-terminal of diode D2 and then connected to the signal output terminal of the driver chip. The P-terminal of the diode D1 is connected in series with the resistor R6 and then connected to one end of the driving resistor R1. The N-terminal of diode D2 is connected to one end of driving resistor R1 via resistor R5 and the P-terminal of diode D5. One end of the capacitor C3 is connected to the common terminal of the diode D1 and the resistor R6, and the other end is grounded; One end of the capacitor C4 is connected to the common terminal of the resistor R5 and the P terminal of the diode D5, and the other end is grounded.

4. The improved SiC-IGBT hybrid power module drive circuit according to claim 1, characterized in that: The delay circuit B includes: diode D3, diode D4, diode D6, resistor R9, resistor R8, capacitor C5, and capacitor C6; The N-terminal of diode D3 is connected to the P-terminal of diode D4 and then connected to the signal output terminal of the driver chip. The P-terminal of the diode D3 is connected in series with the resistor R9 and then connected to one end of the driving resistor R3. The N-terminal of diode D4 is connected to one end of driving resistor R3 via resistor R8 and the P-terminal of diode D6. One end of the capacitor C5 is connected to the common terminal of the diode D3 and the resistor R9, and the other end is grounded; One end of the capacitor C6 is connected to the common terminal of the resistor R8 and the P terminal of the diode D6, and the other end is grounded.

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