Semiconductor device

Abstract

A semiconductor device includes a package structure including a package member bonded to a first side of a package substrate, and the package member including a first die; and a second die bonded to the second side of the package substrate; the fixing device comprises a first cavity and a thermoelectric cooling module located below the first cavity, a part of the packaging structure is located in the first cavity, the part of the packaging structure comprises a second crystal grain, and the second crystal grain is in thermal contact with the thermoelectric cooling module.

Description

Technical Field

[0001] This utility model relates to a semiconductor device, and more particularly to a packaging structure and the fixture and thermoelectric cooling module thereon. Background Technology

[0002] The semiconductor industry has experienced sustained rapid growth due to advancements in integrated circuits and continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, or the like). The primary improvement in integration density comes from repeatedly shrinking the minimum structural size to integrate more components into a given area.

[0003] These integration improvements are inherently two-dimensional because the area occupied by the integrated components is essentially located on the surface of the semiconductor wafer. The increased density of integrated circuits and the corresponding reduction in area typically exceed the ability to directly bond integrated circuit wafers to the substrate. Interposers are used for redistribution from the wafer's ball contact area to a larger area within the interposer. Furthermore, interposers enable three-dimensional packages to contain multiple wafers. Other packaging methods have also been developed to integrate three-dimensional applications. Utility Model Content

[0004] The purpose of this invention is to provide a semiconductor device to solve at least one of the above-mentioned problems.

[0005] In one embodiment, the semiconductor device includes a package structure comprising: a package member bonded to a first side of a package substrate, the package member including a first die; and a second die bonded to a second side of the package substrate; and a retainer including a first cavity and a thermoelectric cooling module located under the first cavity, wherein a portion of the package structure is located in the first cavity, wherein the portion of the package structure includes a second die, and wherein the second die is in thermal contact with the thermoelectric cooling module.

[0006] According to one embodiment of the present invention, a printed circuit board is also coupled to the fixture.

[0007] According to one embodiment of the present invention, the packaging structure uses multiple pins of the retainer to be electrically coupled to the printed circuit board.

[0008] According to one embodiment of the present invention, each of the plurality of pins includes a top plunger and a bottom plunger.

[0009] According to one embodiment of the present invention, each of the plurality of pins includes a housing located between the top plunger and the bottom plunger.

[0010] According to one embodiment of the present invention, the outer shell is located in the retainer.

[0011] According to one embodiment of the present invention, each of the plurality of pins includes a spring mechanism located in the housing.

[0012] According to one embodiment of the present invention, it further includes a first metal layer located on the thermoelectric cooling module and a second metal layer located on the lower surface of the second grain.

[0013] According to one embodiment of the present invention, a thermal interface material is further located between the first metal layer and the second metal layer.

[0014] According to one embodiment of the present invention, the sidewall of the second grain is attached to the sidewall of the thermoelectric cooling module via an adhesive layer. Attached Figure Description

[0015] Figures 1 to 13 This is a cross-sectional view of an intermediate stage in the fabrication of the packaging structure in some embodiments.

[0016] Figure 14A and Figure 14B This is a cross-sectional view of an intermediate stage of an electrical testing package structure or a manufacturing assembly package structure, as shown in some embodiments.

[0017] Figure 15 This is a cross-sectional view of an intermediate stage of an electrical testing package structure or a package structure for manufacturing assembly, as shown in some other embodiments.

[0018] Figure 16A and Figure 16B This is a cross-sectional view of an intermediate stage in the electrical testing of the package structure or the manufacturing of the package structure, as shown in some other embodiments.

[0019] Figure 17A and Figure 17B This is a cross-sectional view of an intermediate stage in the electrical testing of the package structure or the manufacturing of the package structure, as shown in some other embodiments.

[0020] The attached figures are labeled as follows:

[0021] T1, T2: Total thickness

[0022] T3, T4: Thickness

[0023] W1, W2: Width

[0024] 10,30: Package structure

[0025] 20, 25, 35, 45: Combined packaging structures

[0026] 15,40: Components

[0027] 60: Main Body

[0028] 62: Active Surface

[0029] 64, 76: Intrawire structure

[0030] 68, 68A, 68B, 68A / B: Grain size

[0031] 70,300:Substrate

[0032] 72: First Surface

[0033] 74: Through hole

[0034] 77, 79: Metal Columns

[0035] 78: Metal capping layer

[0036] 90: First Packaging Area

[0037] 91: Conductive junction

[0038] 92: Second Packaging Area

[0039] 94: Cutting line area

[0040] 96: Components

[0041] 100,202,314: Subfill material

[0042] 112: Sealant

[0043] 116: Second Surface

[0044] 117: Dielectric layer

[0045] 118: Metallized Pattern

[0046] 120, 312: Electrical connectors

[0047] 140: Surface apparatus

[0048] 200: Encapsulation component

[0049] 212,218,420,428,442: Thermal interface materials

[0050] 214: Radiator

[0051] 216: Adhesive Material

[0052] 220: Cooling device

[0053] 302: Substrate core

[0054] 304, 306: Rewiring Structure

[0055] 307: Conductive via

[0056] 308: Landing Grid Array Pad

[0057] 400: Fixture

[0058] 401: The First Void

[0059] 402: Top

[0060] 403: The Second Void

[0061] 404: Bottom

[0062] 405: Pin

[0063] 406: Outer shell

[0064] 408: Plunger

[0065] 410, 426: Thermoelectric cooling module

[0066] 412, 430: Adhesive layer

[0067] 414, 422, 444: Metal layer

[0068] 416: Hole

[0069] 418: Printed Circuit Board

[0070] 424: Metal Block

[0071] 446: Cold Plate

[0072] 447: Entry Port

[0073] 448: Support plate

[0074] 449: Export Port

[0075] 450: Backplate

[0076] 452: Fasteners Detailed Implementation

[0077] The following detailed description is illustrated with accompanying drawings to aid in understanding various aspects of this utility model. It is worth noting that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of various structures may be arbitrarily increased or decreased for clarity.

[0078] The different embodiments or examples provided below can implement different structures of the present invention. The embodiments of specific components and arrangements are intended to simplify this disclosure and not to limit the present invention. For example, a description of forming a first component on a second component includes direct contact between the two, or a spacing between the two with other additional components rather than direct contact. Various embodiments of the present invention may repeatedly use the same reference numerals for brevity, but elements with the same reference numerals in various embodiments and / or arrangements do not necessarily have the same correspondence.

[0079] In addition, spatial relative terms such as “below,” “below,” “lower,” “above,” “higher,” or similar terms are used to describe the relationship between some elements or structures in the accompanying drawings and other elements or structures. These spatial relative terms include different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is turned in a different orientation (rotated 90 degrees or other orientations), the spatial relative adjectives used will also be interpreted according to the orientation after the turn.

[0080] Various embodiments include methods for forming device packages, such as chip-on-wafer-on-substrate (CIP) packages. The device package includes packaging components (such as wafer-on-wafer package components including one or more first semiconductor wafers bonded to an interposer) and a packaging substrate. A first side (also considered as the front side) of the packaging substrate may be bonded to the interposer on the side opposite to the one or more first semiconductor wafers. A second semiconductor wafer may be bonded to a second side (also considered as the back side) of the packaging substrate, wherein the second side of the packaging substrate and the first side of the packaging substrate are opposite sides of the packaging substrate. Temporary electrical connections can be established between the device package and specific test points on a printed circuit board to evaluate and test the electrical, functional, and performance characteristics of the device package. The temporary electrical connection can be manufactured using a fixture including a top (also considered as a top guide), a bottom (also considered as a bottom guide), and pins extending through the top and bottom of the fixture. Each pin may include a bottom plunger extending below the lower surface of the fixture and inserted into an individual hole in the printed circuit board, with the hole aligned with a desired contact (such as a contact pad) in the printed circuit board. Each pin may also include a top plunger. The contact may correspond to a test point, a program interface, or other area requiring a temporary electrical connection. After the bottom plunger of each pin is inserted into an individual hole in the printed circuit board, the pin physically and electrically contacts the contact point. Each pin further includes a housing located between the top plunger and the bottom plunger. A spring mechanism is located in the housing to compress or retract the pin when pressure is applied and to return it to its extended state when pressure is removed.

[0081] The top of the retainer includes a first cavity that extends partially through the top of the retainer. A second cavity is located in the remaining top of the retainer. For example, the second cavity may be located in the lower surface of the first cavity. The width of the first cavity is greater than the width of the second cavity. A thermoelectric cooling module (also considered a Peltier device or thermoelectric cooler) is located in the second cavity, wherein the thermoelectric cooling module is bonded to the lower surface of the second cavity with an adhesive layer (such as a die-bonded film). The top plungers of the respective pins may protrude above the lower surface of the first cavity and above the upper surface of the thermoelectric cooling module located in the second cavity. The device package is then placed in the first cavity of the retainer, wherein the device package is secured between the sidewalls of the first cavity to ensure that the first plunger is properly aligned with the individual landing grid pads on the back side of the package substrate of the device package. The retainer is designed to firmly hold and support the device package during testing and to prevent lateral movement of the device package. After the device package is placed in the first cavity of the retainer, the top plunger of each pin physically contacts the individual landing grid pads on the package substrate to ensure an electrical connection is formed between the device package and the printed circuit board via the pins.

[0082] Furthermore, after the device package is placed in the first cavity of the retainer for testing, the thermoelectric cooling module physically contacts the lower surface of the second semiconductor wafer via a thermal interface material located between the thermoelectric cooling module and the second semiconductor wafer. Some advantages of the embodiments described herein include enhanced cooling of the device package (e.g., containing the second semiconductor wafer) from the back side of the packaging substrate during testing and operation. This enhanced cooling effect can accommodate device packages with more semiconductor wafers on both the front and back sides of the packaging substrate, as it is suitable for handling the additional heat generated by the added semiconductor wafers. Furthermore, the enhanced cooling effect from the back side of the packaging substrate (e.g., containing the second semiconductor wafer) effectively eliminates heat sinks and mitigates hot spots during testing and operation of the device package, improving overall temperature control and thermal management of the device package. This further allows for power delivery to the device package from the back side of the packaging substrate without forming hot spots or heat sinks within the device package.

[0083] The embodiments will be described with specific examples, such as die-interposer-substrate stacked packaging using wafer-on-substrate (W2D) technology. However, other embodiments may employ other packaging methods, such as fan-out packaging, and other processes.

[0084] Figures 1 to 13 This is a cross-sectional view of an intermediate stage in the fabrication of the packaging structure 10 in some embodiments. Figure 1One or more dies 68 are displayed. The body 60 of the die 68 may include any number of dies, substrates, transistors, active devices, passive devices, or the like. In one embodiment, the body 60 may include a substrate semiconductor substrate, a semiconductor-on-insulator substrate, a multilayer semiconductor substrate, or the like. The semiconductor material of the body 60 may be silicon, germanium, semiconductor compounds (such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), semiconductor alloys (such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide), or combinations thereof. Other substrates such as multilayer substrates or gradient substrates may also be used. The body 60 may be doped or undoped. Devices such as transistors, capacitors, resistors, diodes, or the like may be formed in and / or on the active surface 62 of the body 60.

[0085] The interconnect structure 64 includes one or more dielectric layers and individual metallization patterns, formed on the active surface 62. The metallization patterns in the dielectric layers may employ vias and / or circuitry to route electrical signals between devices, and may also contain various electrical devices such as capacitors, resistors, inductors, or the like. Multiple devices and metallization patterns can be interconnected to perform one or more functions. These functions may include memory structures, process structures, sensors, amplifiers, power distribution, input / output circuits, or the like. Furthermore, die interconnects such as conductive pillars (e.g., containing metals such as copper) are formed within and / or on the interconnect structure 64 to provide external electrical connections to circuits and devices.

[0086] In the example of forming one layer of interconnect structure 64, an intermetallic dielectric layer may be formed. For example, the intermetallic dielectric layer may be composed of a low-dielectric-constant dielectric material such as phosphosilicate glass, borosilicate glass, fluorosilicate glass, silicon carbide, spin-coated glass, spin-coated polymer, silicon carbide material, the aforementioned compounds, the aforementioned composites, combinations of the aforementioned, or similar substances, and its formation method may be any suitable method known in the art, such as spin coating, chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma-assisted chemical vapor deposition, or similar methods. For example, a metallization pattern may be formed in the intermetallic dielectric layer, and the formation method may employ photolithography to deposit and pattern photoresist material on the intermetallic dielectric layer, exposing the portion of the intermetallic dielectric layer where the metallization pattern will be formed. Etching processes such as anisotropic dry etching may be used to create recesses and / or openings in the intermetallic dielectric layer to correspond to the exposed portions of the intermetallic dielectric layer. The recesses and / or openings may be padded with a diffusion barrier layer and filled with a conductive material. The diffusion barrier layer may include one or more layers of tantalum nitride, tantalum, titanium nitride, titanium, cobalt-tungsten, the like, or combinations thereof, and its deposition method may be atomic layer deposition or a similar method. The conductive material of the metallization pattern may include copper, aluminum, tungsten, silver, or combinations thereof, and its deposition method may be chemical vapor deposition, physical vapor deposition, or a similar method. Any excess diffusion barrier layer and / or conductive material on the intermetallic dielectric layer may be removed, and the removal method may be chemical mechanical polishing. These steps may be repeated to form an additional layer of interconnect structure 64.

[0087] exist Figure 2 In this process, the main body 60 containing the interconnect structure 64 is cut into individual granules 68. Generally, each of the granules 68 contains the same circuitry, such as the same devices and metallization patterns, but some or all of the granules 68 may have different circuitry. The cutting process may include sawing, slicing, or similar methods.

[0088] Dies 68 may each include one or more logic dies (such as central processing units, graphics processors, system-on-a-chip, field-programmable gate arrays, microcontrollers, or the like), memory dies (such as dynamic random access memory dies, static random access memory dies, or the like), power management dies (such as power management integrated circuit dies), radio frequency dies, sensor dies, microelectromechanical systems dies, signal processing dies (such as digital signal processing dies), front-end dies (such as analog front-end dies), the like, or combinations thereof. Furthermore, dies 68 in some embodiments may have different dimensions (such as different heights and / or surface areas), while dies 68 in other embodiments may have the same dimensions (such as the same height and / or surface area).

[0089] Figure 3One or more components 96 in the display process. Component 96 may be an interposer or other die. Substrate 70 may form the body of component 96. Substrate 70 may be a wafer. Substrate 70 may include a substrate semiconductor substrate, a semiconductor-on-insulator substrate, a multilayer semiconductor substrate, or the like. The semiconductor material of substrate 70 may be silicon, germanium, semiconductor compounds (such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), semiconductor alloys (such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide), or combinations thereof. Other substrates such as multilayer substrates or gradient substrates may also be used. Substrate 70 may be doped or undoped. Devices such as transistors, capacitors, resistors, diodes, or the like may be formed in and / or on the first surface 72 (which may also be considered an active surface) of substrate 70. In embodiments where component 96 is an interposer, component 96 typically does not contain any active device therein, although the interposer may include passive devices formed in and / or on the first surface 72. In these embodiments, component 96 does not have any active device on the substrate 70.

[0090] A through-hole 74 is formed extending from a first surface of substrate 70 into substrate 70. When substrate 70 is a silicon substrate, through-hole 74 is sometimes considered as a through-substrate via or through-silicon via. The through-hole 74 can be formed by forming a recess in substrate 70, and the formation method can be etching, drilling, laser technology, a combination of the above, and / or similar methods. A thin dielectric material can be formed in the recess, for example, using oxidation technology. A thin barrier layer can be compliantly deposited on the front side of substrate 70 and in the opening, and the deposition method can be chemical vapor deposition, atomic layer deposition, physical vapor deposition, thermal oxidation, a combination of the above, and / or similar methods. The barrier layer may include nitrides or oxides of nitride, such as titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, a combination of the above, and / or similar substances. A conductive material can be deposited on the thin barrier layer and in the opening. The conductive material can be formed by electrochemical plating, chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations thereof, and / or similar methods. Examples of conductive materials include copper, tungsten, aluminum, silver, gold, combinations thereof, and / or similar materials. For example, excess conductive material and barrier layer can be removed from the front side of substrate 70 by chemical mechanical polishing. Therefore, through-hole 74 may include conductive material and barrier layer located between the conductive material and substrate 70.

[0091] Interconnect structures 76 are formed on the first surface 72 of the substrate 70 and are used to electrically connect integrated circuit devices (if present) and / or vias 74 together and / or electrically connect them to external devices. Interconnect structures 76 may include one or more dielectric layers and individual metallization patterns within the dielectric layers. The metallization patterns may include vias and / or lines for connecting any devices and / or vias 74 together and / or connecting them to external devices. The dielectric layers may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or dielectric materials with low dielectric constants (such as phosphosilicate glass, borosilicate glass, fluorosilicate glass, silicon oxycarbide, spin-coated glass, spin-coated polymers, silicon carbide materials, compounds of the above, composites of the above, combinations of the above, or the like). The deposition method of the dielectric layer may be any suitable method known in the art, such as spin coating, chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma-assisted chemical vapor deposition, or similar methods. Metallization patterns can be formed within the dielectric layer, for example, by using photolithography to deposit and pattern photoresist material onto the dielectric layer to expose portions of the dielectric layer that will be transformed into metallization patterns. Etching processes, such as anisotropic dry etching, can be used to create recesses and / or openings in the dielectric layer to correspond to the exposed portions. Recesses and / or openings can be created by a diffusion barrier layer liner, and conductive material can be filled into the recesses and / or openings. The diffusion barrier layer can include one or more layers of tantalum nitride, tantalum, titanium nitride, titanium, cobalt-tungsten, or the like, and its deposition method is atomic layer deposition or a similar method. The conductive material can include copper, aluminum, tungsten, silver, combinations thereof, or the like, and its deposition method is chemical vapor deposition, physical vapor deposition, or a similar method. Any excess diffusion barrier layer and / or conductive material on the dielectric layer can be removed, and the removal method can be chemical mechanical polishing.

[0092] Electrical connections 77 / 78 are formed on the upper surface of the interconnect structure 76, such as on conductive pads in the dielectric layer of the interconnect structure 76. In some embodiments, the electrical connections 77 / 78 include metal pillars 77 and metal capping layers 78, such as solder caps, located on the metal pillars 77. The electrical connections 77 / 78 (containing the metal pillars 77 and the metal capping layers 78) are sometimes considered as microbumps. In some embodiments, the metal pillars 77 include conductive materials such as copper, aluminum, gold, nickel, palladium, the like, or combinations thereof, and are formed by sputtering, printing, electroplating, electroless plating, chemical vapor deposition, or similar methods. The metal pillars 77 may be solderless and have substantially drooping sidewalls. In some embodiments, individual metal capping layers 78 are formed on individual upper surfaces of the metal pillars 77. The metal capping layers 78 may include nickel, tin, tin-lead, gold, copper, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or combinations thereof, and are formed by plating processes.

[0093] In another embodiment, the electrical connections 77 / 78 do not include metal pillars, but may be solder balls and / or bumps such as those formed by controlled-collapse wafer bonding, electroless nickel-plated gold, electroless nickel-plated palladium-plated gold techniques, or similar techniques. In these embodiments, the electrical connections 77 / 78 of the bumps may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof. The electrical connections 77 / 78 may be formed by first forming a solder layer, and the formation method may be vapor deposition, electroplating, printing, solder transfer, ball placement, or similar methods. Once the solder layer is formed on the structure, a reflow process can be performed to shape the material into the desired bump shape.

[0094] exist Figure 4 In this configuration, die 68 (including dies 68A and 68B) is attached to a first side of component 96, for example, via metal pillars 79 on the die to bond with the flip chip of electrical connectors 77 / 78 to form a conductive junction 91. The metal pillars 79 may be similar to metal pillars 77 and will not be described again here. For example, die 68 may be placed on electrical connectors 77 / 78 using a pick-and-place tool. In some embodiments, a metal capping layer 78 is formed on the metal pillars 77, the metal pillars 79 of the die 68, or both.

[0095] Die 68A and die 68B may be different types of dies. In some embodiments, die 68A includes logic dies (such as central processing units, graphics processors, systems-on-a-chip, preprogrammable gates and arrays, microcontrollers, or the like), memory dies (such as dynamic random access memory dies, static random access memory dies, or the like), power management dies (such as power management integrated circuit dies), radio frequency dies, sensor dies, microelectromechanical systems dies, signal processing dies (such as digital signal processing dies), front-end dies (such as analog front-end dies), the like, or combinations thereof. In some embodiments, die 68A is a system-on-a-chip or graphics processor die, and die 68B is a memory die used by die 68A. In some embodiments, die 68B includes a stack of one or more memory dies such as memory dies (e.g., dynamic random access memory dies, static random access memory dies, high-bandwidth memory dies, hybrid memory cube dies, or the like). In embodiments of memory die stacking, die 68B may include a memory die and a memory controller, such as a stack of four or eight memory dies and a memory controller. Furthermore, in some embodiments, die 68B differs in size from die 68A (e.g., different height and / or surface area). In other embodiments, die 68B has the same size as die 68A (e.g., same height and / or surface area). In some embodiments, die 68B has a similar height to die 68A (e.g., similar height and / or surface area). Figure 4 (As shown). In some embodiments, the heights of grain 68A and grain 68B are different.

[0096] The conductive junction 91 can electrically couple the circuitry in the die 68 to the through-hole 74 in the interconnect structure 76 and the component 96 via the interconnect structure 64. In addition, the interconnect structure 76 can electrically interconnect the dies 68A and 68B with each other.

[0097] In some embodiments, before joining electrical connections 77 / 78, flux (not shown) such as no-clean flux may be applied to electrical connections 77 / 78. Flux may be applied to electrical connections 77 / 78, or inkjet flux may be applied to electrical connections 77 / 78. In another embodiment, flux may also be applied to electrical connections 79 / 78. In some embodiments, electrical connections 77 / 78 and / or 79 / 78 may have an epoxy flux (not shown) formed thereon before reflow, and at least some epoxy portions of the epoxy flux are retained after grain 68 is bonded to component 96. The retained epoxy portions may serve as an underfill layer to reduce stress and protect the interface formed by the reflow of electrical connections 77 / 78 / 79.

[0098] The bonding between die 68 and component 96 can be solder bonding or direct metal-to-metal bonding (such as copper-to-copper or tin-to-tin). In one embodiment, die 68 is bonded to component 96 using a reflow process. During this reflow process, electrical connections 77 / 78 / 79 contacts physically and electrically couple die 68 to component 96. After the bonding process, an intermetallic compound (not shown) may be formed at the interface between the metal pillars 77 / 79 and the metal capping layer 78.

[0099] exist Figure 4 As shown in the following figures, the first package area 90 and the second package area 92 are used to form the first package and the second package, respectively. The dicing line area 94 is located between adjacent package areas. Figure 4 As shown, a single die 68A and multiple dies 68B are bonded to the first packaging region 90 and the second packaging region 92.

[0100] exist Figure 5 In the process, underfill material 100 is delivered into the gap between grain 68 and interconnect structure 76. Underfill material 100 may extend upward along the sidewalls of grains 68A and 68B. Underfill material 100 may be any acceptable material such as polymer, epoxide, molded underfill layer, or the like. Underfill material 100 may be formed by capillary process after bonding grain 68, or by suitable deposition method before bonding grain 68.

[0101] exist Figure 6In this process, sealant 112 is formed on various components. Sealant 112 may be a molding compound, epoxide, or the like, and its application method may be compression molding, transfer molding, or similar methods. A curing step, such as thermosetting, UV curing, or similar steps, is performed to cure the sealant 112. In some embodiments, grains 68 are embedded in the sealant 112, and a planarization step, such as grinding, may be performed after curing the sealant 112 to remove excess portion of the sealant 112 above the upper surface of the grains 68. In summary, the upper surface of the grains 68 may be exposed, and may be flush with the upper surface of the sealant 112. In some embodiments, the heights of grains 68B and 68A may be different, and the sealant 112 may still cover grains 68B after the planarization step.

[0102] Figures 7 to 10 The method of forming the second side of component 96 is shown. Figure 7 In the middle, flip Figure 6 The structure is designed to prepare for forming the second side of member 96. Although not shown, the structure can be placed... Figures 7 to 10 The carrier plate or supporting structure used in the process.

[0103] exist Figure 8 In this process, a thinning process is performed on the second side of the substrate 70 to thin the substrate 70 until the through-hole 74 is exposed. The thinning process applied to the second surface 116 of the substrate 70 may include an etching process, a polishing process, a similar process, or a combination thereof.

[0104] exist Figure 9A redistribution structure is formed on the second surface 116 of the substrate 70 to electrically connect the through-holes 74 together and / or to external devices. The redistribution structure includes a dielectric layer 117 and a metallization pattern 118 located within and / or on the dielectric layer 117. The metallization pattern may include vias and / or traces for connecting the through-holes 74 together and / or connecting them to external devices. The metallization pattern 118 may sometimes be considered as redistribution lines. The dielectric layer 117 may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or a low dielectric constant dielectric material (such as phosphosilicate glass, borosilicate glass, fluorosilicate glass, silicon oxycarbide, spin-coated glass, spin-coated polymer, silicon carbide material, the above compounds, the above composites, combinations of the above, or the like). The deposition method for dielectric layer 117 can be any suitable method known in the art, such as spin coating, chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma-assisted chemical vapor deposition, or similar methods. Metallization pattern 118 can be formed in dielectric layer 117, for example, by using photolithography to deposit and pattern photoresist material on dielectric layer 117 to expose portions of dielectric layer 117 that will be transformed into metallization pattern 118. Etching processes such as anisotropic dry etching can be used to create openings in dielectric layer 117 corresponding to the exposed portions of dielectric layer 117. A seed layer (not shown) can be formed on the exposed surface of dielectric layer 117 and within the openings. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer containing multiple sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer on the titanium layer. For example, the seed layer can be formed using physical vapor deposition or similar methods. Photoresist is then formed and patterned on the seed layer. The photoresist can be formed by spin coating or a similar method. The photoresist can be exposed to light for patterning. The pattern of the photoresist can correspond to a metallization pattern 118. The patterning step can form openings through the photoresist to expose a seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating (e.g., electroplating or electroless plating) or a similar method. The conductive material can include metals such as copper, titanium, tungsten, aluminum, or the like. The portion of the photoresist and conductive material on which the seed layer is not formed is then removed. The photoresist can be removed using an acceptable ashing or stripping process, such as using oxygen plasma or a similar method. Once the photoresist is removed, the exposed seed layer can be removed using an acceptable etching process. The remaining portion of the seed layer and conductive material forms a metallization pattern 118.

[0105] exist Figure 10Electrically connected elements 120 are formed on the metallization pattern 118 and electrically coupled to the via 74. The electrically connected elements 120 may be formed on the upper surface of the redistribution structure on the metallization pattern 118. In some embodiments, the metallization pattern 118 includes a bump under-metallization layer. The electrically connected elements 120 may be formed on the bump under-metallization layer.

[0106] In some embodiments, the electrical connector 120 is a solder ball and / or bump, such as a ball grid array ball, a controlled collapse wafer connection microbump, a bump formed by electroless nickel-impregnated gold, a bump formed by electroless nickel- and palladium-impregnated gold, or the like. The electrical connector 120 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof. In some embodiments, the electrical connector 120 may be formed by first forming a solder layer, which may be formed by vapor deposition, electroplating, printing, solder transfer, ball placement, or similar methods. Once the solder layer is formed on the structure, it can be reflowed to shape the material into the desired bump shape. In another embodiment, the electrical connector 120 is a metal pillar (such as a copper pillar), which may be formed by sputtering, printing, electroplating, electroless plating, chemical vapor deposition, or similar methods. The metal pillar may be solderless and may have substantially vertical sidewalls. In some embodiments, a metal capping layer (not shown) is formed on top of the electrical connection 120 of the metal pillar. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or combinations thereof, and may be formed by an electroplating process.

[0107] Electrical connector 120 will be used to join additional electrical components such as semiconductor substrates, packaging substrates, printed circuit boards, or the like (see...) Figure 12 ).

[0108] exist Figure 11 In the process, the component 96 is divided along the cutting line area 94 between the adjacent first encapsulation area 90 and the second encapsulation area 92 to form an encapsulation component 200 containing a die 68A, the component 96, and the die 68B. The division can be by sawing, cutting, or similar methods.

[0109] Figure 12 The encapsulation component 200 is attached to the substrate 300. The electrical connector 120 is aligned and pressed against the bonding pads of the substrate 300. The electrical connector 120 can be reflowed to create a bond between the substrate 300 and the component 96.

[0110] The substrate 300 may be a packaging substrate or the like, and may include an organic substrate, a ceramic substrate, a silicon substrate, or the like. Before the substrate 300 is attached to the packaging component 200, the substrate 300 may be processed according to feasible manufacturing processes to form a redistribution structure in the substrate 300. For example, the substrate 300 includes a substrate core 302. The substrate core 302 may be composed of glass fiber, resin, filler, other materials, and / or combinations thereof. The substrate core 302 may be composed of organic and / or inorganic materials. In some embodiments, the substrate core 302 includes one or more passive components (not shown) embedded therein. The substrate core 302 may be modified to include other materials or components. A conductive via 307 may extend through the substrate core 302. In some embodiments, the conductive via 307 may include a conductive material such as copper, a copper alloy, or other conductors, and may include a barrier layer, a pad, a seed layer, and / or a filler material. The conductive via 307 may provide a vertical electrical connection from one side of the substrate core 302 to the other side of the substrate core 302. For example, conductive vias 307 are coupled between conductive structures on one side of the substrate core 302 and conductive structures on the opposite side of the substrate core 302. For example, the vias 307 can be formed using drilling, photolithography, laser processing, or other methods, and conductive material can be filled behind the vias 307. In some embodiments, the conductive vias 307 are hollow conductive through-holes, the center of which can be filled with insulating material. Redistribution structures 304 and 306 are located on opposite sides of the substrate core 302. Redistribution structures 304 and 306 are electrically coupled vias 307 and can transmit electrical signals in a fan-out manner. Each redistribution structure 304 and 306 includes a dielectric layer and a metallization pattern. Redistribution structure 304 can be attached to the packaging member 200 by electrical connectors 120. One side of the substrate 300 includes the exposed surface of the redistribution structure 304, which can also be considered as the front side of the substrate 300. One side of the substrate 300 includes the exposed surface of the redistribution structure 306, which can also be regarded as the back side of the substrate 300.

[0111] like Figure 12 As shown, the landing grid array pad 308 may be located on the back side of the substrate 300 (such as on the surface of the redistribution structure 306). The landing grid array pad 308 may include flat metal pads (such as those containing copper or the like) to serve as contacts for making electrical connections between the package structure 10 and other external devices or package components.

[0112] Underfill material 202 may be dispensed between the encapsulation component 200 and the substrate 300 to surround the electrical connector 120. Underfill material 202 may be any acceptable material such as polymer, epoxide, molded underfill layer, or the like.

[0113] In addition, one or more surface devices 140 may be connected to the substrate 300. The surface devices 140 may provide additional functionality or programming to the package member 200 or the entire package. In one embodiment, the surface device 140 may include surface-mount devices or integrated passive devices (including passive devices such as resistors, inductors, capacitors, jumpers, combinations thereof, or the like) that need to be connected to the package member 200 or other parts of the package for use in conjunction with the package member 200 or other parts of the package. In various embodiments, the surface device 140 may be disposed on a first principal surface of the substrate 300, an opposing principal surface of the substrate 300, or both.

[0114] exist Figure 13 In this process, adhesive material 216 is delivered onto substrate 300. Adhesive material 216 may include any material suitable for sealing components such as heat sink 214 onto substrate 300, such as epoxide, urethane, polyurethane, silicone elastomer, or the like. Adhesive material 216 may be delivered to the outer portion, periphery, or edge of substrate 300. Heat sink 214 may include a heat cap or heat ring. In addition, thermal interface material 212 may be applied to the upper surface of encapsulation component 200 (such as the upper surface of dies 68A and 68B) and the upper surface of underfill material 100. Thermal interface material 212 may include, but is not limited to, graphite, polymer-based adhesives, hot grease, phase change materials, liquid bonding materials, metal-filled polymer matrices, or solder metals of lead, tin, indium, silver, copper, bismuth, or the like (preferably indium or lead-tin alloys). If thermal interface material 212 is solid, the solid may be heated to a solid-liquid transition and then the liquid may be applied to the upper surface of encapsulation component 200.

[0115] like Figure 13 As shown, a heat sink 214 is placed on a substrate 300, surrounding and also located on the encapsulation member 200. The heat sink 214 may be made of a highly thermally conductive material, such as a metal like copper, steel, iron, or the like. The heat sink 214 protects the encapsulation member 200. The heat sink 214 is coupled to the encapsulation member 200 by a thermal interface material 212. After the heat sink 214 is placed on the substrate 300, a suitable curing process can be performed to cure the adhesive material 216, thus securely attaching the heat sink 214 to the substrate 300.

[0116] After the heat sink 214 is attached to the substrate 300, the cooling device 220 may be coupled to the upper surface of the heat sink 214 with a thermal interface material 218, as appropriate. The material and application method of the thermal interface material 218 may be similar to those of the aforementioned thermal interface material 212. The cooling device 220 is placed on the heat sink 214, wherein the cooling device 220 may be coupled to the heat sink 214 by the thermal interface material 218. The cooling device 220 may then be considered as a heat dissipation structure. In some embodiments, the cooling device 220 may be any suitable device for heat dissipation. For example, the cooling device 220 in one embodiment may be a heat pipe cooling device, a gas (fan) cooling device, or the like. The cooling device may not be shown in the following figures.

[0117] Electrical connections 312 may be formed on the bonding pads of the redistribution structure 306 before or after the heat sink 214 is attached to the substrate 300. In some embodiments, the electrical connections 312 are solder balls and / or bumps, such as ball grid array balls, controlled collapse wafer connection microbumps, or the like. The electrical connections 312 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof. In some embodiments, the electrical connections 312 are formed by first forming a solder layer, and the formation method may be vapor deposition, electroplating, solder transfer, ball placement, or similar methods. Once the solder layer is formed on the structure, reflow can be performed to shape the material into the desired bump shape.

[0118] After the electrical interconnect 312 is formed, it can be used to attach the die 68 (which may include the aforementioned die 68A or 68B) to the back side of the substrate 300. The dies 68A / B coupled to the back side of the substrate 300 are electrically coupled to other dies 68A / B of the package member 200 via the substrate 300, through the via 74, and the electrical interconnect 120.

[0119] The bonding between the die 68 on the back side of the substrate 300 and the substrate 300 can be solder bonding. In one embodiment, the die 68 is bonded to the bonding pad of the redistribution structure 306 on the back side of the substrate 300 using a reflow process. Electrical connectors 312 during the reflow process contact to physically and electrically couple the die 68A / B to the substrate 300.

[0120] An underfill material 314 can be dispensed between the substrate 300 and the dies 68A / B coupled to the back side of the substrate 300. The underfill material 314 may surround the electrical connector 312. The underfill material 314 may be any acceptable material such as polymers, epoxides, molded underfill layers, or the like.

[0121] Figure 14A Display component 15, which can be used to establish a temporary electrical connection to Figure 13The aforementioned package structure 10 is connected to specific test points on the printed circuit board 418. After establishing a temporary electrical connection, the electrical, functional, and performance characteristics of the package structure 10 can be evaluated and tested. Component 15 may include a retainer 400 (which may also be considered a socket module), comprising a top 402 (which may also be considered a top guide plate), a bottom 404 (which may also be considered a bottom guide plate), and pins 405 extending through the top 402 and bottom 404 of the retainer 400. The top 402 and bottom 404 may include machinable ceramics, Vespel polyimide purchased from DuPont, aluminum nitride, polyetheretherketone engineering plastics, polytetrafluoroethylene, or the like. In one embodiment, the total thickness T1 of the top 402 and bottom 404 may be 5.5 mm to 8 mm. Each pin 405 may include a movable bottom plunger 408 extending below the lower surface of the retainer 400 and inserted into a specific hole 416 in the printed circuit board 418, the hole 416 aligning with a predetermined contact (such as a contact pad) in the printed circuit board 418. Pins 405 may also include a movable top plunger 408. These contacts may correspond to test points, program interfaces, or other areas requiring temporary electrical connections. After the respective bottom plunger 408 of each pin 405 is inserted into the specific hole 416 in the printed circuit board, the pin 405 can physically and electrically contact the contact. Each pin 405 further includes a housing 406 (which may also be considered a cylinder) located between the top plunger 408 and the bottom plunger 408, wherein the housing 406 is located within the retainer 400. A spring mechanism is disposed within the housing 406, and the spring mechanism allows the pin 405 to compress or retract when pressure is applied (e.g., via vertical movement of the top plunger 408 and / or the bottom plunger 408), and return to its extended state when pressure is removed. In one embodiment, the pin 405 does not move laterally, and a gap may surround the sidewall of the housing 406 (e.g., there may be a space between the sidewall of the housing 406 and the retainer 400). In one embodiment, the housing 406, the top plunger 408, and the bottom plunger 408 may comprise brass, copper, or the like, on which thin layers such as nickel, rhodium, gold, bronze, or alloys may be formed.

[0122] The top 402 of the retainer 400 may include a first cavity 401 extending partially through the top 402 of the retainer 400. A second cavity 403 is located in the remaining top 402 of the retainer 400. For example, the second cavity 403 may be located in the lower surface of the first cavity 401. The total thickness T2 of the remaining top 402 of the retainer 400 and the bottom 404 of the retainer 400 may be 1.5 mm to 4 mm. Having a total thickness T1 of 5.5 mm to 8 mm for the top 402 and the bottom 404, and a total thickness T2 of 1.5 mm to 4 mm for the remaining top 402 of the retainer 400 and the bottom 404 of the retainer 400, offers several advantages. These advantages include the first cavity 401 having a suitable depth, allowing the encapsulation structure 10 to be properly secured when inserted and placed within the first cavity 401, such as... Figure 14B As shown. For example, if the total thickness T1 of the top 402 and bottom 404 is less than 5.5 mm, or the total thickness T2 of the remaining top 402 and bottom 404 of the retainer 400 is greater than 4 mm, the encapsulation structure 10 cannot be properly secured in the first cavity 401, degrading performance and causing reliability issues during operation. The width W1 of the first cavity 401 may be greater than the width W2 of the second cavity 403. A thermoelectric cooling module 410 (also considered as a Peltier device or thermoelectric cooler) is located in the second cavity 403, wherein the thermoelectric cooling module 410 is attached to the lower surface of the second cavity 403 by an adhesive layer 412 (such as a die bonding film or the like). The thermoelectric cooling module 410 may be a solid-state electronic component designed to regulate temperature using the Peltier effect. The thermoelectric cooling module 410 may include multiple semiconductor units composed of n-type and p-type materials, which are connected in series and sandwiched between ceramic substrates. When a direct current is applied to a semiconductor junction (e.g., where an n-type material contacts a p-type material), one side absorbs heat (e.g., the cooling side) while the other side releases heat (e.g., the heating side). This temperature difference allows the thermoelectric cooling module 410 to cool or heat a specific area, depending on the direction of the current. In one embodiment, the thickness T3 of the thermoelectric cooling module 410 can be from 1 mm to 3 mm. In one embodiment, the upper surface area of ​​the thermoelectric cooling module 410 and the lower surface area of ​​the substrate 300 (e.g., the cooling side absorbs heat) are different. Figure 14B The proportion (as shown) can be 50% to 80%. In one embodiment, the upper surface of the thermoelectric cooling module 410 is higher than the lower surface of the first cavity 401. The metal layer 414 may be located on the upper surface of the thermoelectric cooling module 410. In one embodiment, the metal layer 414 may include titanium, copper, nickel vanadium, gold, combinations thereof, or the like.

[0123] In one embodiment, the top plunger 408 of each pin 405 may protrude above the lower surface of the first cavity 401. In one embodiment, a portion of the top plunger 408 of each pin 405 may protrude above the upper surface of the thermoelectric cooling module 410 in the second cavity. In one embodiment, a portion of the top plunger 408 of each pin 405 may protrude above the upper surface of the metal layer 414.

[0124] A temporary electrical connection can be established by the retainer 400 (e.g.) Figure 14B (As shown) at specific test points on the package structure 10 and the printed circuit board 418 (such as...) Figure 14B The electrical, functional, and performance characteristics of the package structure 10 are evaluated and tested between the pins 405 and the corresponding holes 416 in the printed circuit board 418. Each pin 405 has a bottom plunger 408 that can be inserted into an individual hole 416 in the printed circuit board 418, with the hole aligning with an individual contact (such as a contact pad) in the printed circuit board 418. After the bottom plunger 408 of each pin 405 is inserted into the individual hole 416 in the printed circuit board 418, the pin 405 physically and electrically contacts the contact (such as a contact pad).

[0125] The printed circuit board 418 may include a non-conductive substrate material such as glass fiber reinforced epoxide (FR-4), ceramic, or the like. The printed circuit board 418 may include a thin layer of copper foil laminated onto its surface to define conductive lines and serve as electrical pathways. Components may be embedded in the printed circuit board 418 via surface mount technology.

[0126] In one embodiment, a printed circuit board 418 is used for testing package structure 10 and is coupled to a retainer 400 to form component 15. The printed circuit board 418 provides an interface for testing package structure 10 and includes contacts, connectors, and holes 416 (such as sockets) for aligning with the specific layout and arrangement of the package structure 10 to be tested. The printed circuit board 418 can be dedicated to the testing phase and facilitates the application of electrical signals, measurements, and tests to evaluate the performance of package structure 10.

[0127] In other embodiments, during manufacturing, the printed circuit board 418 is permanently assembled with the retainer 400 into the component 15, wherein the printed circuit board 418 serves as the final electronic product (e.g., Figure 14B The following describes some of the functional requirements of the combined package structure 20. The printed circuit board 418 may include the necessary electronic components, circuitry, and connections required for the intended operation of the combined package structure 20. This includes microprocessors, memory, sensors, and other components. Furthermore, the printed circuit board 418 may integrate various other devices and packages to extend its functionality and accommodate other electronic components beyond the combined package structure 20.

[0128] exist Figure 14BIn the process, the package structure 10 is then inserted into and placed in the first cavity 401 of the retainer 400, wherein a portion of the package structure 10 is fixed between the sidewalls of the first cavity 401 to ensure that the top plunger 408 is properly aligned with the individual landing grid pads 308 on the back side of the substrate 300 of the package structure 10. After the package structure 10 is inserted into and placed in the first cavity 401 of the retainer 400, a portion of the package structure 10 also protrudes above the upper surface of the retainer 400 and above the first cavity 401. The retainer 400 is designed to firmly hold and support the package structure 10 during electrical testing and to prevent lateral movement of the package structure 10. After the package structure is placed in the first cavity 401 of the retainer 400, the top plunger 408 of each pin 405 makes physical and electrical contact with the individual landing grid pads 308 on the substrate 300 to ensure that an electrical connection is formed between the package structure 10 and the printed circuit board 418 via the pin 405. Each spring mechanism of the pin 405 can compress the pin 405 (e.g., via vertical movement of the top plunger 408 and / or the bottom plunger 408) when the package structure 10 is inserted into the first cavity 401 and pressure is applied to the pin 405. Furthermore, after the package structure 10 is placed in the first cavity 401 of the retainer 400, the thermoelectric cooling module 410 physically contacts the lower surface of the dies 68A / B, and the dies 68A / B are coupled to the back side of the substrate 300 via a thermal interface material 420 located between the thermoelectric cooling module 410 and the dies 68A / B. The material and application method of the thermal interface material 420 can be customized according to the specific requirements of the package structure 10. Figure 13 The thermal interface material 212 described above is similar in material and application method to thermal interface material 218. For example, a metal layer 422 may be placed on the lower surface of the dies 68A / B coupled to the back side of the substrate 300. In one embodiment, the metal layer 422 may include titanium, copper, nickel-vanadium, gold, combinations thereof, or the like. Thermal interface material 420 may be applied to the upper surface of metal layer 414 and / or the lower surface of metal layer 422. After the package structure 10 is placed in the first cavity 401 of the retainer 400, the dies 68A / 68B are coupled to the thermoelectric cooling module 410 via thermal interface material 420. In other embodiments, metal layers 422 and 414 are absent, and the thermoelectric cooling module 410 is directly coupled to the dies 68A / 68B via thermal interface material 420.

[0129] After the package structure 10 is inserted into and placed in the first cavity 401 of the retainer 400, electrical testing of the package structure 10 can be performed. During electrical testing, electrical signals, test patterns, or specific simulations can be applied to the package structure 10 via the printed circuit board 418 and the retainer 400 (e.g., via pins 405), and the corresponding responses can be carefully monitored. In this way, the functionality, reliability, and performance of the package structure 10 can be evaluated. During electrical testing, direct current can be applied to the semiconductor junction of the thermoelectric cooling module 410 (e.g., the contact between n-type and p-type materials) to absorb heat on the first side (e.g., the cooling side) of the thermoelectric cooling module 410 facing the package structure 10 and release heat to the second side (e.g., the heating side) of the thermoelectric cooling module 410, which is opposite to the first side. This temperature difference allows the thermoelectric cooling module 410 to cool the package structure 10 during electrical testing.

[0130] After electrical testing of the package structure 10, the package structure 10 can be removed from the first opening 401 of the retainer 400, thereby separating the member 15 from the package structure 10. In one embodiment, subsequent processes can be performed on the package structure 10. The spring mechanisms of each pin 405 allow the pin 405 to retract (e.g., via vertical movement of the top plunger 408 and / or the bottom plunger 408), and the pin 405 returns to its extended position when the package structure 10 is removed from the first opening 401 and the pressure on the pin 405 decreases.

[0131] Inserting the package structure 10 into the first cavity 401 of the retainer 400 offers several advantages, and establishes an electrical connection between the package structure 10 and the printed circuit board 418 via pins 405. The thermoelectric cooling module 410, located in the second cavity 403 of the retainer 400, physically and thermally contacts the lower surface of the dies 68A / B, and the dies 68A / B are coupled to the back side of the substrate 300 via a thermal interface material 420 located between the thermoelectric cooling module 410 and the dies 68A / B. In other embodiments, the thermoelectric cooling module 410 thermally contacts the dies 68A / B via a metal layer 414, the thermal interface material 420, and a metal layer 422. During electrical testing of the package structure 10, direct current can be applied to the semiconductor junction of the thermoelectric cooling module 410 (e.g., at the contact point between an n-type and a p-type material). These advantages include enhanced cooling of the package structure 10 (e.g., containing dies 68A / B on the back side of the substrate 300) from the back side of the substrate 300 during electrical testing. This enhanced cooling effect can be combined with package structures 10 employing more dies on the front and back sides of the substrate 300, as the enhanced cooling effect is suitable for accommodating the additional heat generated by the increased dies. Furthermore, the enhanced cooling effect of the package structure 10 (e.g., containing dies 68A / B on the back side of the substrate 300) from the back side of the substrate 300 effectively eliminates heat sinks and mitigates hot spots during electrical testing, thereby improving the overall temperature control and thermal management of the package structure 10. This allows power to be supplied from the back side of the substrate 300 to the package structure 10 without forming hot spots or heat sinks within the package structure 10.

[0132] In other embodiments, the printed circuit board 418 serves as part of the functional requirements of the final electronic product, and the printed circuit board 418 is permanently assembled with the retainer 400 into the component 15, which is then coupled to the package structure 10 to form the combined package structure 20 (e.g., Figure 14B(As shown). Printed circuit board 418 may include the necessary electronic components, circuitry, and connections required for the intended operation of the combined package structure 20. This includes microprocessors, memory, sensors, and other components. Furthermore, printed circuit board 418 may integrate various other devices and packages to extend its functionality and accommodate additional electronic components beyond the combined package structure 20. To couple package structure 10 to component 15, solder paste (such as fine solder particles and flux) may be applied to landing grid pads 308 and / or top plungers 408. Solder paste may be strategically placed in areas requiring electrical connection. Package structure 10 may then be inserted and positioned in the first cavity 401 of retainer 400, wherein a portion of package structure 10 is secured between the sidewalls of the first cavity 401 to ensure that top plungers 408 are properly aligned with the individual landing grid pads 308 on the back side of the substrate 300 of package structure 10. After the package structure 10 is placed in the first cavity 401 of the retainer 400, the top plungers 408 of each pin 405 physically and electrically contact the individual landing grid pads 308 on the substrate 300. Heat can then be applied to the assembled package structure 20 via a reflow process (such as a reflow soldering process) or a similar process. This melts the solder paste to facilitate the formation of solder joints between each pin 405 and the individual landing grid pads 308. In this manner, the package structure 10 is coupled together with the component 15 to form the assembled package structure 20. Furthermore, after the package structure 10 is placed in the first cavity 401 of the retainer 400 and coupled to the pins 405, the thermoelectric cooling module 410 physically contacts and couples to the lower surface of the die 68A / B on the back side of the substrate 300 via a thermal interface material 420 located between the thermoelectric cooling module 410 and the die 68A / B, similar to the manner described above.

[0133] When operating the package structure 20, direct current can be applied to the semiconductor junction of the thermoelectric cooling module 410 (e.g., the contact point between the n-type and p-type materials) to absorb heat from the first side (e.g., the cooling side) of the thermoelectric cooling module 410 facing the package structure 10 and release heat to the second side (e.g., the heating side) of the thermoelectric cooling module 410, with the second side of the thermoelectric cooling module 410 opposite to the first side. This temperature difference allows the thermoelectric cooling module 410 to cool the package structure 10 when operating the package structure 20.

[0134] Inserting the package structure 10 into the first cavity 401 of the retainer 400 offers several advantages, and coupling the package structure 10 to the retainer 400 to form a combined package structure 20 establishes an electrical connection between the package structure 10 and the printed circuit board 418 via pins 405. The thermoelectric cooling module 410, located in the second cavity 403 of the retainer 400, physically contacts the lower surface of the dies 68A / B, and the dies 68A / B are coupled to the back side of the substrate 300 via a thermal interface material 420 located between the thermoelectric cooling module 410 and the dies 68A / B. In other embodiments, the thermoelectric cooling module 410 thermally contacts the dies 68A / B via a metal layer 414, the thermal interface material 420, and the metal layer 422. Direct current can be applied to the semiconductor junction of the thermoelectric cooling module 410 (e.g., where n-type material contacts p-type material). These advantages include enhanced cooling of the package structure 10 (e.g., containing dies 68A / B on the back side of the substrate 300) from the back side of the substrate 300 when operating the combined package structure 20. This enhanced cooling effect can be combined with the package structure 10 employing more dies on the front and back sides of the substrate 300, as the enhanced cooling effect is suitable for accommodating the additional heat generated by the increased dies. Furthermore, the enhanced cooling effect of the package structure 10 (e.g., containing dies 68A / B on the back side of the substrate 300) from the back side of the substrate 300 effectively eliminates heat traps and mitigates hot spots when operating the combined package structure 20, thereby improving the overall temperature control and thermal management of the package structure 10. This further allows power to be supplied to the package structure 10 from the back side of the substrate 300 without forming hot spots or heat traps within the package structure 10.

[0135] Figure 15 This illustrates other embodiments following the placement of the encapsulation structure 10 within the first cavity 401 of the retainer 400. Unless otherwise specified, similar reference numerals in this embodiment (and those described later) denote... Figures 1 to 14B The components shown in the embodiments are similar and formed by similar processes. In summary, the manufacturing steps and feasible materials are not repeated here. Figure 15 The structure shown is Figure 14B The difference in the structure shown is that Figure 15In the illustrated structure, the thermoelectric cooling module 410 is not located in the second cavity 403. A metal block 424 (such as a copper block) may replace the thermoelectric cooling module 410 and be located in the second cavity 403, wherein the metal block 424 is bonded to the lower surface of the second cavity 403 using an adhesive layer 412 (such as a die bonding film or the like). The metal block 424 may include copper, silver, or the like, and its thickness T4 may be 1 mm to 3 mm. After the package structure 10 is placed in the first cavity 401 of the retainer 400, the metal block 424 physically contacts the lower surface of the dies 68A / B, and the dies 68A / B are coupled to the back side of the substrate 300 via a thermal interface material 420 located between the metal block 424 and the dies 68A / B. In one embodiment, a metal layer 414 may be located on the metal block 424, and a metal layer 422 may be located on the lower surface of the dies 68A / B coupled to the back side of the substrate 300. Metal layer 414 can physically and thermally contact metal layer 422 via a thermal interface material 420 located between the upper surface of metal layer 414 and the lower surface of metal layer 422. In one embodiment, metal layers 414 and 422 may include titanium, copper, nickel-vanadium, gold, combinations thereof, or the like. In other embodiments, metal layers 422 and 414 are absent, and the thermoelectric cooling module 410 is directly coupled to the dies 68A / 68B via the thermal dielectric material 420. The high thermal conductivity of the material of metal block 424 allows for rapid heat absorption and heat transfer from the packaging structure 10 (such as the die 68A coupled to the back side of substrate 300), thereby facilitating the cooling of the packaging structure 10.

[0136] After the package structure 10 is inserted into and placed in the first hole 401 of the retainer 400, electrical tests of the package structure 10 can be performed, such as when paired with... Figure 14B The above explanation clarifies that during electrical testing, the high thermal conductivity of the metal block 424 allows for rapid heat absorption and transfer from the package structure 10 (e.g., the dies 68A / B coupled to the back side of the substrate 300), thus facilitating the cooling of the package structure 10. After electrical testing of the package structure 10, it can be removed from the first hole 401 of the retainer 400, as described above. Figure 14B The above content is explained.

[0137] In other embodiments, the printed circuit board 418 serves as part of the functional requirements of the final electronic product, and is permanently assembled with and coupled to the retainer 400 to the package structure 10 to form a combined package structure 25. The printed circuit board 418 may include the necessary electronic components, circuitry, and connections required for the intended operation of the combined package structure 25. This includes microprocessors, memory, sensors, and other components. Furthermore, the printed circuit board 418 may also integrate various other devices and packages to extend its functionality and accommodate other electronic components beyond the combined package structure 25. After the package structure 10 is placed in the first cavity 401 of the retainer 400, a reflow process (and...) is employed. Figure 14B Similar to the reflow process described above, it is used to couple each of the pins 405 to an individual landing grid pad 308 to facilitate the formation of solder joints between each pin 405 and the individual landing grid pad 308 on the substrate 300. In this manner, the package structure 10 is coupled to the retainer 400 and the substrate 300 to form a combined package structure 25. Furthermore, after the package structure 10 is placed in the first cavity 401 of the retainer 400 and coupled to the pins 405, the metal block 424 physically contacts and is coupled to the lower surface of the die 68A / B on the back side of the substrate 300 via a thermal interface material 420 located between the die 68A / B and the metal block 424, similar to the manner described above.

[0138] When operating the package structure 25, the high thermal conductivity of the material of the metal block 424 allows it to quickly absorb heat and transfer it from the package structure 10 (such as the dies 68A / B coupled to the back side of the substrate 300) to facilitate cooling of the package structure 10.

[0139] Figure 16A and Figure 16B Other embodiments are shown. Unless otherwise specified, similar reference numerals in this embodiment (and the embodiments described below) denote... Figures 1 to 15 The components shown in the embodiments are similar and formed by similar processes. In summary, the process steps and feasible materials are not repeated here. Figure 16A The package structure 30 shown is Figure 13 The packaging structure 10 shown above is similar, except that before the electrical connector 312 couples the die 68A / B to the substrate 300, the die 68A / B is embedded in the thermoelectric cooling module 426. The operation method and materials of the thermoelectric cooling module 426 can be matched with... Figure 14A The operation method and materials of the thermoelectric cooling module 410 described above are similar.

[0140] The dies 68A / B can be located within the voids in the thermoelectric cooling module 426. Before placing the dies 68A / B into the voids, an adhesive layer 430 (such as a die bonding film) can be applied to the edge portions of the sidewalls and lower surface of the voids to bond the dies 68A / B to the lower surface and sidewalls of the voids in the thermoelectric cooling module 426. Furthermore, before placing the dies 68A / B into the voids, a thermal interface material 428 can be applied to the central portion of the lower surface of the dies 68A / B and / or the central portion of the lower surface of the voids. The material and application method of the thermal interface material 428 can be customized according to the specific requirements of the module. Figure 13 The thermal interface material 212 described above is similar in material and application method to the thermal interface material 218. After placing the grains 68A / B in the cavity, the grains 68A / B are coupled to the thermoelectric cooling module 426 and embedded in the thermoelectric cooling module 426, wherein the upper surface of the grains 68A / B can be flush with the upper surface of the thermoelectric cooling module 426.

[0141] After embedding the dies 68A / B in the thermoelectric cooling module 426, electrical connectors 312 are used to bond the dies 68A / B and the thermoelectric cooling module 426 to the back side of the substrate 300. The dies 68A / B coupled to the back side of the substrate 300 can be electrically coupled to other dies 68A / B of the package member 200 via the substrate 300, through-holes 74, and electrical connectors 120.

[0142] The bonding between the substrate 300 and the dies 68A / B on the back side of the substrate 300 can be solder bonding. In one embodiment, the method of bonding the dies 68A / B to the bonding pads of the redistribution structure 306 on the back side of the substrate 300 is a reflow process. During this reflow process, the electrical connectors 312 contact to physically and electrically couple the dies 68A / B to the substrate 300.

[0143] An underfill material 314 can be dispensed between the substrate 300 and the die 68A / B, and between the substrate 300 and the thermoelectric cooling module 426 coupled to the back side of the substrate 300. The underfill material 314 may surround the electrical connector 312. The underfill material 314 may be any acceptable material, such as polymers, epoxides, molded underfill layers, or the like.

[0144] In other embodiments, the thermoelectric cooling module 426 may be replaced by a metal block, which may include copper, silver, or the like. For example, the grains 68A / B may be located within cavities in the metal block. An adhesive layer 430 (such as a grain bonding film) may be used to bond the grains 68A / B to the lower surface and sidewalls of the cavities in the metal block, and the adhesive layer 430 may be placed on the edge portions of the sidewalls and lower surface of the cavities before the grains 68A / B are placed in the cavities. Furthermore, a thermal interface material 428 may be applied to the central portion of the lower surface of the grains 68A / B and / or the central portion of the lower surface of the cavities before the grains 68A / B are placed in the cavities.

[0145] Figure 16B The encapsulation structure 30 shown is inserted into and placed in the first cavity 401 of the retainer 400 of the component 15, wherein Figure 16B The component 15 shown is Figure 14B The difference of the above-described component 15 is that Figure 16B The component 15 shown does not include the thermoelectric cooling module 410, which is located in the second cavity 403 of the retainer 400. When the encapsulation structure 30 is inserted and placed in the first cavity 401 of the retainer 400, a portion of the encapsulation structure 30 is secured between the sidewalls of the first cavity 401 to ensure that the top plunger 408 is properly aligned with the individual landing grid array pads 308 on the back side of the substrate 300 of the encapsulation structure 30 (with...). Figure 14B (The top plunger 408 shown is aligned with the individual landing grid pads 308 on the back side of the substrate 300 of the package structure 10 in a similar manner as described above.) The retainer 400 is designed to firmly hold and support the package structure 30 during electrical testing and to prevent lateral movement of the package structure 30. After the package structure is placed in the first cavity 401 of the retainer 400, the top plunger 408 of each pin 405 makes physical and electrical contact with the individual landing grid pads 308 on the substrate 300 to ensure an electrical connection is formed between the package structure 30 and the printed circuit board 418 via the pin 405.

[0146] Furthermore, when the encapsulation structure 30 is inserted and placed in the first cavity 401 of the retainer 400, a portion of the die 68A / B and a portion of the thermoelectric cooling module 426 extend into the second cavity 403. For example, a portion of the thermoelectric cooling module 426 and a portion of the die 68A / B may extend into the second cavity 403, such that the lower surface of the thermoelectric cooling module 426 physically contacts the lower surface of the second cavity 403. After the encapsulation structure 30 is inserted and placed in the first cavity 401 and the second cavity 403 of the retainer 400, a portion of the encapsulation structure 30 may also protrude above the upper surface of the retainer 400 and above the first cavity 401. In one embodiment, a gap is located between the lower surface of the second cavity 403 and the lower surface of the thermoelectric cooling module 426. In one embodiment, a first gap is located between the first sidewall of the top 402 and the sidewall of the thermoelectric cooling module 426. In one embodiment, the second gap is located between the second sidewall of the top 402 and the sidewall of the thermoelectric cooling module 426, wherein the width of the first gap is greater than the width of the second gap, and wherein the first gap is higher than the second gap.

[0147] After the package structure 30 is inserted into and placed in the first cavity 401 and the second cavity 403 of the retainer 400, electrical testing of the package structure 30 can be performed (method and configuration). Figure 14B The electrical testing method for the package structure 10 is similar to that described above. During electrical testing, direct current can be applied to the semiconductor junction of the thermoelectric cooling module 426 (e.g., the contact between the n-type and p-type materials) to absorb heat from the sidewalls and upper surface of the thermoelectric cooling module 426 adjacent to the chips 68A / B, and release heat to the lower surface of the thermoelectric cooling module 426. This temperature difference allows the thermoelectric cooling module 426 to cool the package structure 30 (containing chips 68A / B) during electrical testing.

[0148] After electrical testing of the package structure 30, the package structure 30 can be removed from the first hole 401 and the second hole 403 of the retainer 400, thereby separating the component 15 from the package structure 30. In one embodiment, additional processes can then be performed on the package structure 30.

[0149] Inserting the package structure 30 into the first cavity 401 and the second cavity 403 of the retainer 400 offers several advantages for establishing an electrical connection between the package structure 30 and the printed circuit board 418 via pins 405. The package structure 30 may include a die 68A / B embedded in a thermoelectric cooling module 426. An adhesive layer 430 (such as a die bonding film) may be used to bond the die 68A / B to the lower surface and sidewalls of the cavity in the thermoelectric cooling module 426 to embed the die 68A / B in the thermoelectric cooling module 426. Before placing the die 68A / B in the cavity, the adhesive layer 430 may be placed on the edge portions of the sidewalls and lower surface of the cavity. Furthermore, before placing the die 68A / B in the cavity, a thermal interface material 428 may be applied to the central portion of the lower surface of the die 68A / B and / or the central portion of the lower surface of the cavity. The thermoelectric cooling module 426 and the dies 68A / B embedded in the thermoelectric cooling module 426 can then be coupled to the back side of the substrate 300. The thermoelectric cooling module 426 physically and thermally contacts the dies 68A / B via a thermal interface material 428. Direct current can be applied to the semiconductor junctions of the thermoelectric cooling module 426 (e.g., where n-type material contacts p-type material). These advantages include improved cooling of the package structure 30 (e.g., containing dies 68A / B on the back side of the substrate 300) from the back side of the substrate 300 during electrical testing. The improved cooling effect can be combined with the use of more dies on the front and back sides of the substrate 300 in the package structure 30, as the improved cooling effect is suitable for accommodating the additional heat generated by the increased dies. Furthermore, the improved cooling effect of the package structure 30 (e.g., containing dies 68A / B on the back side of the substrate 300) from the back side of the substrate 300 can effectively eliminate heat traps and alleviate hot spots during electrical testing, thereby improving the overall temperature control and thermal management of the package structure 30. This further allows power to be delivered from the back side of the substrate 300 to the package structure 30 without forming hot spots or heat traps in the package structure 30.

[0150] In other embodiments, the printed circuit board 418 may serve as part of the functional requirements of the final electronic product, and the printed circuit board 418 is permanently assembled with and coupled to the package structure 30 to form a combined package structure 35. The printed circuit board 418 may include the necessary electronic components, circuitry, and connections required for the intended operation of the combined package structure 35. This includes microprocessors, memory, sensors, and other components. Furthermore, the printed circuit board 418 may also integrate various other devices and packages to extend its functionality and accommodate other electronic components beyond the combined package structure 35. After the package structure 30 is placed in the first cavity 401 and the second cavity 403 of the fixture 400, a reflow process (and mating) may be employed. Figure 14BSimilar to the reflow process described above, it is used to couple each of the pins 405 to an individual landing grid pad 308 to facilitate the formation of solder joints between the respective pins 405 and the individual landing grid pads 308 on the substrate 300. In this manner, the package structure 30 is coupled to the retainer 400 and the substrate 300 to form a combined package structure 35. In one embodiment, after the package structure 30 is placed in the first cavity 401 and the second cavity 403 of the retainer 400 and coupled to the pins 405, the lower surface of the thermoelectric cooling module 426 of the package structure 30 physically contacts the lower surface of the second cavity 403 (such as the upper surface of the bottom 404 of the retainer 400).

[0151] Inserting and placing the package structure 30 into the first cavity 401 and the second cavity 403 of the retainer 400 offers several advantages and allows the package structure 30 to be coupled to the retainer 400 to establish an electrical connection between the package structure 30 and the printed circuit board 418 via pins 405. The package structure 30 may include dies 68A / B embedded in a thermoelectric cooling module 426. An adhesive layer 430 (such as a die bonding film) may be used to bond the dies 68A / B to the lower surface and sidewalls of the cavities in the thermoelectric cooling module 426 to embed the dies 68A / B in the thermoelectric cooling module 426. Before the dies 68A / B are placed in the cavities, the adhesive layer 430 may be located on the edge portions of the lower surface and the sidewalls of the cavities. Furthermore, before the dies 68A / B are placed in the cavities, a thermal interface material 428 may be applied to the central portion of the lower surface of the dies 68A / B and / or the central portion of the lower surface of the cavities. The thermoelectric cooling module 426 and the dies 68A / B embedded in the thermoelectric cooling module 426 are then coupled to the back side of the substrate 300. The thermoelectric cooling module 426 physically and thermally contacts the dies 68A / B via a thermal interface material 428. Direct current can be applied to the semiconductor junctions of the thermoelectric cooling module 426 (e.g., where n-type material contacts p-type material). These advantages include enhanced cooling of the package structure 30 (e.g., containing dies 68A / B on the back side of the substrate 300) from the back side of the substrate 300 when operating the combined package structure 35. The enhanced cooling effect can be combined with the use of more dies in the package structure 10 on the front and back sides of the substrate 300, as the enhanced cooling effect is suitable for accommodating the additional heat generated by the increased dies. Furthermore, the improved cooling effect of the package structure 10 (e.g., containing dies 68A / B on the back side of the substrate 300) from the back side of the substrate 300 effectively eliminates heat traps and alleviates hot spots when operating the package structure 35, thereby improving the overall temperature control and thermal management of the package structure 10. This further allows power to be supplied from the back side of the substrate 300 to the package structure 10 without forming hot spots or heat traps in the package structure 10.

[0152] Figure 17A and Figure 17BOther embodiments are shown. Unless otherwise specified, similar reference numerals in this embodiment (and the embodiments described below) denote... Figures 1 to 16B The components shown in the embodiments are similar and formed by similar processes. Therefore, the process steps and feasible materials will not be repeated here. Figure 17A The component 40 shown is used to establish a temporary electrical connection to Figure 13 The aforementioned package structure 10 is connected to specific test points on the printed circuit board 418. After establishing a temporary electrical connection, the electrical properties, functionality, and performance of the package structure 10 can be evaluated and tested.

[0153] Component 40 can be combined with Figure 14A Similar to component 15 described above, the difference being that component 40 does not contain the thermoelectric cooling module 410 located within the second cavity 403 of the retainer 400. Instead, component 40 includes a cold plate 446 (such as a heat exchanger designed to absorb heat from a particular component and remove heat) that extends through a portion of the first cavity 401 of the retainer 400, the second cavity 403 of the retainer 400, and the bottom 404 of the retainer 400. In one embodiment, the cold plate 446 may extend through the second cavity 403 and the bottom 404 of the retainer 400, but not through any portion of the first cavity 401. The cold plate 446 may also extend through the printed circuit board 418, protruding below the lower surface of the printed circuit board 418. In one embodiment, the cold plate 446 may physically contact the sidewalls of the bottom 404 of the retainer 400 and the sidewalls of the printed circuit board 418.

[0154] Cold plate 446 may include a thermally conductive material such as aluminum, copper, or the like. Cold plate 446 may include internal channels or paths through which cooling fluids such as water, a special coolant, or the like circulate. Cold plate 446 may include an inlet port 447 and an outlet port 449, which facilitate the entry and exit of cooling fluid, respectively. Cooling fluid may absorb heat from the component as it circulates through the internal channels.

[0155] The cold plate 446 can be secured by a combination of a back plate 450 and fasteners 452. For example, the back plate 450 may comprise metal or another rigid material and be located on either side of the printed circuit board 418 with the retainer 400, such that the upper surface of the back plate 450 physically contacts the lower surface of the cold plate 446. The back plate can serve as structural support for the cold plate 446. In some embodiments, additional support structures such as a support plate 448 may be employed to provide additional stability and fill the space between the printed circuit board 418 and the back plate 450. The support plate 448 and the back plate 450 may comprise similar materials. Fasteners 452 (such as screws) can be used to secure the cold plate 446. The fasteners 452 may extend through the printed circuit board 418, the support plate 448, and the back plate 450.

[0156] exist Figure 17BNext, the encapsulation structure 10 is inserted and placed into the first cavity 401 of the retainer 400 of the component 40. When the encapsulation structure 10 is inserted and placed into the first cavity 401 of the retainer 400, a portion of the encapsulation structure 10 is fixed between the sidewalls of the first cavity 401 to ensure that the top plunger 408 is properly aligned with the individual landing grid pads 308 on the back side of the substrate 300 of the encapsulation structure 10, and the alignment is consistent with the mating. Figure 14B The top plunger 408 described above is aligned with the individual landing grid pads 308 on the back side of the substrate 300 of the package structure 10 in a similar manner. The retainer 400 is designed to firmly hold and support the package structure 10 during electrical testing and to prevent lateral movement of the package structure 10. After the package structure 10 is inserted into and placed in the first hole 401 of the retainer 400, a portion of the package structure 10 may also protrude above the upper surface of the retainer 400 and above the first hole 401. After the package structure 10 is placed in the first hole 401 of the retainer 400, the top plunger 408 of each pin 405 makes physical and electrical contact with the individual landing grid pads 308 on the substrate 300 to ensure an electrical connection is established between the package structure 10 and the printed circuit board 418 via the pin 405. Furthermore, after the encapsulation structure 10 is placed in the first cavity 401 of the retainer 400, the cold plate 446 can be physically contacted and coupled to the lower surface of the die 68A / B on the back side of the substrate 300 via the thermal interface material 442 located between the cold plate 446 and the die 68A / B. The material and application method of the thermal interface material 442 can be matched with... Figure 13 The thermal interface material 212 described above is similar in material and application method to thermal interface material 218. For example, metal layer 444 may be located on the lower surface of die 68A / B, which is coupled to the back side of substrate 300. In one embodiment, metal layer 444 may include titanium, copper, nickel, vanadium, gold, combinations thereof, or the like. Thermal interface material 442 may be applied to the upper surface of cold plate 446 and / or the lower surface of metal layer 444. After the package structure 10 is placed in the first cavity 401 of retainer 400, die 68A / 68B is coupled to cold plate 446 via thermal interface material 442. Circulating cooling fluid in cold plate 446 absorbs heat from package structure 10 (e.g., containing die 68A / B coupled to the back side of substrate 300) and carries heat away from cold plate 446 to facilitate cooling of package structure 10.

[0157] After the package structure 10 is inserted into and placed in the first hole 401 of the retainer 400, electrical tests of the package structure 10 can be performed, such as when paired with... Figure 14BThe above description applies. During electrical testing, the circulating cooling fluid in the cold plate 446 absorbs heat from the package structure 10 (e.g., containing the back side of the substrate 300 coupled to the die 68A / B) and carries heat away from the cold plate 446 to facilitate cooling of the package structure 10. After performing electrical testing on the package structure 10, the package structure 10 can be removed through the first opening 401 of the retainer 400, thereby separating the component 40 from the package structure 10. In one embodiment, other processes can then be performed on the package structure 10.

[0158] Placing the package structure 10 in and inserting it into the first cavity 401 of the retainer 400 to establish an electrical connection between the package structure 10 and the printed circuit board 418 via pins 405 offers several advantages. A cold plate 446 may extend through a portion of the first cavity 401, a second cavity 403, and the bottom 404 of the retainer 400. In one embodiment, the cold plate 446 may extend through the second cavity 403 and the bottom 404 of the retainer 400, but not through any portion of the first cavity 401. The cold plate 446 may also extend through the printed circuit board 418, protruding below the lower surface of the printed circuit board 418. In one embodiment, the cold plate 446 may physically contact the sidewalls of the bottom 404 of the retainer 400 and the sidewalls of the printed circuit board 418. The cold plate 446 can physically contact the lower surface of the thermally contacting dies 68A / B, while the dies 68A / B are coupled to the back side of the substrate 300 via a thermal interface material 442 located between the cold plate 446 and the dies 68A / B. These advantages include improved cooling of the package structure 10 (e.g., containing dies 68A / B on the back side of the substrate 300) from the back side of the substrate 300 during electrical testing. The improved cooling effect allows for the incorporation of more dies in the package structure 10 on both the front and back sides of the substrate 300, as the improved cooling effect is suitable for accommodating the additional heat generated by the increased dies. Furthermore, the improved cooling effect of the package structure 10 (containing dies 68A / B on the back side of the substrate 300) from the back side of the substrate 300 effectively eliminates heat traps and alleviates hot spots during electrical testing, improving the overall temperature control and thermal management of the package structure 10. This allows power to be supplied from the back side of the substrate 300 to the package structure 10 without forming hot spots or heat traps in the package structure 10.

[0159] In other embodiments, the printed circuit board 418 serves as part of the functional requirements of the final electronic product, and the printed circuit board 418 is permanently assembled and coupled to the retainer 400 to the package structure 10 to form a combined package structure 45. The printed circuit board 418 may include the necessary electronic components, circuitry, and connections required for the intended operation of the combined package structure 45. This includes microprocessors, memory, sensors, and other components. Furthermore, the printed circuit board 418 may also integrate various other devices and packages to extend its functionality and accommodate other electronic components beyond the combined package structure 45. After the package structure 10 is placed in the first cavity 401 of the retainer 400, a reflow process (and mating) may be employed. Figure 14B Similar to the reflow process described above, it is used to couple each pin 405 to an individual landing grid pad 308 to facilitate the formation of solder joints between each pin 405 and the individual landing grid pad 308 on the substrate 300. In this manner, the package structure 10 is coupled to the retainer 400 and the substrate 300 to form a combined package structure 45. In one embodiment, after the package structure 10 is placed in the first cavity 401 of the retainer 400 to couple to the pin 405, the cold plate 446 can be physically contact-coupled to the lower surface of the dies 68A / B on the back side of the substrate 300 via a thermal interface material 442.

[0160] Inserting and placing the package structure 10 into the first cavity 401 of the retainer 400, and coupling the package structure 10 to the retainer 400 to establish an electrical connection between the package structure 10 and the printed circuit board 418 via pins 405, offers several advantages. A cold plate 446 may extend through a portion of the first cavity 401, a second cavity of the retainer 400, and the bottom 404 of the retainer 400. In one embodiment, the cold plate 446 may extend through the second cavity 403 and the bottom 404 of the retainer 400, but not through any portion of the first cavity 401. The cold plate 446 may extend through the printed circuit board 418, protruding below the lower surface of the printed circuit board 418. In one embodiment, the cold plate 446 may physically contact the sidewalls of the bottom 404 of the retainer 400 and the sidewalls of the printed circuit board 418. The upper surface of the cold plate 446 can be physically and thermally coupled to the lower surface of the chips 68A / B on the back side of the substrate 300 via a thermal interface material 442 located between the cold plate 446 and the chips 68A / B. These advantages include enhancing the cooling effect of the package structure 10 (e.g., containing chips 68A / B on the back side of the substrate 300) from the back side of the substrate 300 when operating the combined package structure 45. The enhanced cooling effect can be combined with the package structure 10 employing more chips on the front and back sides of the substrate 300, as the enhanced cooling effect can appropriately accommodate the additional heat generated by the increased chips. Furthermore, enhancing the cooling effect of the package structure 10 (e.g., containing chips 68A / B on the back side of the substrate 300) from the back side of the substrate 300 can effectively eliminate heat traps and alleviate hot spots when operating the combined package structure 45, thereby improving the overall temperature control and thermal management of the package structure 10. This allows for further power delivery from the back side of the substrate 300 to the package structure 10 without forming hot spots and heat traps in the package structure 10.

[0161] In one embodiment, a method of forming a semiconductor device includes forming a package structure, wherein the step of forming the package structure includes attaching a package member to a first side of a package substrate, wherein the package member includes a first die; attaching a second die to a back side of the package substrate; and inserting a portion of the package structure into a first cavity of a retainer, wherein the retainer includes a thermoelectric cooling module located in a second cavity of the retainer, wherein the second cavity of the retainer is located in the lower surface of the first cavity, wherein after the portion of the package structure is inserted into the first cavity of the retainer, the second die thermally contacts the thermoelectric cooling module, and wherein the retainer is coupled to a printed circuit board. In one embodiment, the package structure includes a heat sink attached to the package substrate, wherein the heat sink surrounds the package member. In one embodiment, after the portion of the package structure is inserted into the first cavity of the retainer, the package structure is electrically coupled to a printed circuit board via a plurality of pins of the retainer. In one embodiment, the method further includes applying an electrical signal to the package structure via the printed circuit board to test the package structure. In one embodiment, the step of testing the package structure further includes applying direct current to a plurality of semiconductor junctions of the thermoelectric cooling module. In one embodiment, the method further includes separating the package structure from the retainer after testing the package structure. In one embodiment, the width of the first cavity is greater than the width of the second cavity, and the first cavity is higher than the second cavity. In one embodiment, the first metal layer is located on the thermoelectric cooling module, and the second metal layer is located on the lower surface of the second die. In one embodiment, the method further includes applying a thermal interface material to the upper surface of the first metal layer or the lower surface of the second metal layer before inserting a portion of the packaging structure into the first cavity of the retainer.

[0162] In one embodiment, a method of forming a semiconductor device includes forming a package structure, wherein the steps of forming the package structure include bonding a first die and an interposer to a first side of a package substrate, wherein the interposer is located between the first die and the package substrate; bonding a thermoelectric cooling module and a second die to a back side of the package substrate, wherein the second die is embedded in the thermoelectric cooling module; and inserting a first portion of the package structure into a first cavity of a retainer and inserting a second portion of the package structure into a second cavity of the retainer, wherein the second cavity of the retainer is located in the lower surface of the first cavity, wherein the second portion of the package structure includes a portion of the thermoelectric cooling module and the second die, wherein the retainer is coupled to a printed circuit board. In one embodiment, the sidewall of the second die is attached to the sidewall of the thermoelectric cooling module via an adhesive layer. In one embodiment, a thermal interface material is located between the lower surface of the second die and the thermoelectric cooling module. In one embodiment, the thermal interface material includes indium. In one embodiment, after inserting the first portion of the package structure into the first cavity of the retainer and inserting the second portion of the package structure into the second cavity of the retainer, the package structure is electrically coupled to a printed circuit board via a plurality of pins of the retainer. In one embodiment, the method further includes applying an electrical signal to the package structure via a printed circuit board to test the package structure.

[0163] In one embodiment, the semiconductor device includes a package structure comprising: a package member bonded to a first side of a package substrate, the package member including a first die; and a second die bonded to a second side of the package substrate; and a retainer including a first cavity and a thermoelectric cooling module located below the first cavity, wherein a portion of the package structure is located within the first cavity, wherein the portion of the package structure includes a second die, and wherein the second die is in thermal contact with the thermoelectric cooling module. In one embodiment, the semiconductor device further includes a printed circuit board coupled to the retainer. In one embodiment, the package structure is electrically coupled to the printed circuit board using a plurality of pins of the retainer. In one embodiment, the pins include a top plunger and a bottom plunger. In one embodiment, the pins include a housing located between the top plunger and the bottom plunger. In one embodiment, the housing is located within the retainer. In one embodiment, the pins include a spring mechanism located within the housing. In one embodiment, the semiconductor device further includes a first metal layer located on the thermoelectric cooling module, and a second metal layer located on the lower surface of the second die. In one embodiment, the semiconductor device further includes a thermal interface material located between the first metal layer and the second metal layer. In one embodiment, the sidewall of the second grain is attached to the sidewall of the thermoelectric cooling module via an adhesive layer.

[0164] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, characterized in that, include: A package structure, including: A packaging component is attached to a first side of a packaging substrate, and the packaging component includes a first die; as well as A second die is bonded to the second side of the packaging substrate; and A fixture includes a first cavity and a thermoelectric cooling module located under the first cavity, wherein a portion of the encapsulation structure is located in the first cavity, wherein the portion of the encapsulation structure includes the second die, and wherein the second die is in thermal contact with the thermoelectric cooling module.

2. The semiconductor device as claimed in claim 1, characterized in that, It also includes a printed circuit board coupled to the fixture.

3. The semiconductor device as claimed in claim 2, characterized in that, The package structure uses multiple pins of the retainer to be electrically coupled to the printed circuit board.

4. The semiconductor device as claimed in claim 3, characterized in that, Each of the plurality of pins includes a top plunger and a bottom plunger.

5. The semiconductor device as claimed in claim 4, characterized in that, Each of the plurality of pins includes a housing located between the top plunger and the bottom plunger.

6. The semiconductor device as claimed in claim 5, characterized in that, The outer casing is located within the retainer.

7. The semiconductor device as claimed in claim 5, characterized in that, Each of the plurality of pins includes a spring mechanism located within the housing.

8. The semiconductor device as claimed in claim 2, characterized in that, It also includes a first metal layer on the thermoelectric cooling module and a second metal layer on the lower surface of the second grain.

9. The semiconductor device as claimed in claim 8, characterized in that, It also includes a thermal interface material located between the first metal layer and the second metal layer.

10. The semiconductor device as claimed in claim 1, characterized in that, The sidewall of the second grain is attached to the sidewall of the thermoelectric cooling module via an adhesive layer.

Images