Write to auxiliary circuits, memory, and electronic devices.

Abstract

This application relates to a write auxiliary circuit, a memory, and an electronic device. The write auxiliary circuit includes: a logic switching circuit configured such that its input terminal is connected to a power supply voltage, and its control terminal receives a level control signal to provide different voltages; an inverting amplifier configured such that its non-inverting input terminal is grounded, its inverting input terminal is connected to the output terminal of the logic switching circuit, and its output terminal is connected to the bit line and the inverted bit line to reduce the bit line potential; and a resistor selector configured such that its input terminal is connected to the inverting input terminal of the inverting amplifier, its control terminal receives a resistor control signal, and its output terminal is connected to the output terminal of the inverting amplifier to provide different feedback resistor values. By achieving a negative voltage output through the operational amplifier circuit, the gamma ratio and write quiescent noise margin are increased, effectively improving the write capability of the SRAM.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to a write auxiliary circuit, a memory, and an electronic device. Background Technology

[0002] Static RAM (SRAM) has become an indispensable memory solution in modern large-scale integrated circuits due to its advantages such as high-speed access performance, process compatibility, and design maturity. However, during the SRAM manufacturing process, due to process variation and feature size miniaturization, memory cells generally suffer from insufficient read and write operation capabilities.

[0003] To ensure correct SRAM write operations, existing technologies often employ auxiliary circuits such as Wordline Overdrive (WLOD), Transient Cell Supply Collapse (TVC), Transient Cell Ground Bump (TGB), and Negative Bitline (NBL) to enhance SRAM write capabilities.

[0004] Among them, the NBL scheme can effectively enhance the conduction characteristics of the access transistor by applying a negative transient voltage to the bitline, and is widely used in various memory cells. However, the existing auxiliary circuit has the problem of insufficient dynamic voltage regulation capability, and cannot flexibly adjust the gate-source voltage (VGS) of the MOS transistor according to the operation requirements. Utility Model Content

[0005] Therefore, it is necessary to provide a write auxiliary circuit, memory, or electronic device that can at least adjust the VGS voltage level of the MOSFET as needed, in order to address the problems mentioned in the background technology.

[0006] To address the aforementioned technical problems and other issues, according to some embodiments, one aspect of this application provides a write-aid circuit applied to a sensitive amplifier, comprising:

[0007] The logic switching circuit is configured such that: the input terminal is connected to the power supply voltage, and the control terminal is used to receive level control signals to provide different voltages;

[0008] The inverting amplifier is configured such that the non-inverting input is grounded, the inverting input is connected to the output of a logic switching circuit, and the output is connected to the bit line and the inverted bit line to reduce the bit line potential.

[0009] The resistor selector is configured such that its input is connected to the inverting input of the inverting amplifier, its control terminal is used to receive the resistor control signal, and its output is connected to the output of the inverting amplifier to provide different feedback resistor values.

[0010] In the write auxiliary circuit of the above embodiment, the logic switching circuit is connected to the inverting input of the inverting amplifier, and the resistor selector is connected across the inverting input and output of the inverting amplifier, together forming a negative voltage generation circuit based on the operational amplifier circuit. In this circuit, by combining the resistor selector and utilizing the relationship between the input and output of the inverting amplifier, the voltage provided by the logic switching circuit is divided into negative voltages with multiple levels, and a controllable negative voltage is applied to the target bit line to compensate for the threshold voltage (Vth) offset caused by process fluctuations; precise potential adjustment realizes the dynamic downward shift of the BL voltage, effectively enhancing the conduction current of the transmission tube in the sensitive amplifier and improving its driving capability.

[0011] In some embodiments, the logic switching circuit includes:

[0012] The power driver is configured such that: the first terminal forms the input terminal of the logic switching circuit and is connected to the power supply voltage; the second and third terminals form the control terminals of the logic switching circuit.

[0013] The first fixed resistor is configured such that its first end is connected to the fourth end of the power supply driver, and its second end forms the output of the logic switching circuit and is connected to the inverting input of the inverting amplifier.

[0014] In some embodiments, the power driver includes:

[0015] The first gating transistor is configured such that: its first terminal forms the first terminal of the power driver and is connected to the power supply voltage, and its control terminal forms the second terminal of the power driver, and it is in the on state when it receives the corresponding level control signal.

[0016] The second gating transistor is configured such that: its first terminal is connected to the first terminal of the first gating transistor, and its control terminal forms the third terminal of the power driver; and it is in the conducting state when it receives the corresponding level control signal.

[0017] The first NOT gate is configured such that its first terminal is connected to the third terminal of the second gating transistor, and its second terminal is connected to the third terminal of the first gating transistor.

[0018] The second NOT gate is configured such that its first terminal is connected to the second terminal of the first NOT gate, the second terminal forms the fourth terminal of the power supply driver and is connected to the first terminal of the first fixed resistor.

[0019] In the above embodiments, different signal processing paths are selected by controlling the first and second gating transistors to achieve precise control of the voltage logic state.

[0020] In some embodiments, the resistor gate includes:

[0021] The fixed resistor branch is configured such that: the first end forms the input terminal of the resistor selector and is connected to the inverting input terminal of the inverting amplifier; and the second end forms the output terminal of the resistor selector and is connected to the output terminal of the inverting amplifier.

[0022] At least one gating branch; wherein, one gating branch is configured such that: the first end is connected to the first end of the fixed resistor branch, the second end constitutes the control end of the resistor selector, and the third end is connected to the second end of the fixed resistor branch.

[0023] In the resistor selector of the above embodiment, the resistor selector formed by the parallel connection of the selected branch and the fixed resistor branch can achieve dynamic adjustment of the impedance value without interrupting the operation of the circuit by switching the control terminal signal.

[0024] In some embodiments, at least one gating branch includes: N gating branches, where N≥1 and N is an integer;

[0025] The Nth selection branch includes:

[0026] The (N+2)th selector transistor is configured such that: its first terminal forms the first terminal of the selector branch and is connected to the first terminal of the fixed resistor branch; its control terminal forms the second terminal of the selector branch; and it is in the on state when it receives the corresponding resistor control signal.

[0027] The (N+2)th fixed resistor is configured such that its first end is connected to the second end of the (N+2)th gating transistor, and its second end forms the third end of the gating branch and is connected to the second end of the fixed resistor branch.

[0028] In some embodiments, the first fixed resistor has the same resistance value as the fixed resistor branch;

[0029] The resistance of the (N+2)th fixed resistor is inversely proportional to the resistance of the first fixed resistor.

[0030] In the above embodiments, by setting multiple selection branches and setting fixed resistors with varying resistance values ​​within the selection branches, greater flexibility in impedance adjustment can be achieved, enabling more precise impedance adjustment.

[0031] In some embodiments, the first gate transistor, the second gate transistor, and the N+2th gate transistor have the same conductive channel type.

[0032] In some embodiments, the resistor control signal includes M sets of resistor control signals, where M ≥ 1 and M is an integer;

[0033] The number of resistor control signals is equal to the number of gating transistors in the gating branch, and one resistor control signal controls one gating transistor.

[0034] In the above embodiments, by having a resistor control signal correspond one-to-one with the gating transistor, the on / off state of each branch can be precisely and directly controlled, thereby improving response speed and reducing delay.

[0035] Another aspect of this application provides a memory comprising:

[0036] A storage array comprises several storage cells arranged in multiple rows and columns;

[0037] Several bit lines, each of which is electrically connected to a memory cell located in the same column;

[0038] Several write auxiliary circuits, as in any of the above embodiments, are connected one-to-one with each bit line.

[0039] Another aspect of this application provides an electronic device, including a write-assist circuit as in any of the above embodiments or a memory as in the above embodiments.

[0040] The write auxiliary circuit, memory, and electronic device provided in this application have the following unexpected technical effects:

[0041] An operational amplifier circuit is constructed using a logic switching circuit, an inverting amplifier, and a resistor selector. By controlling the conduction of different selector transistors and adjusting their resistance, a multi-level controllable negative voltage is provided to the target bit line, thereby flexibly and precisely reducing its potential and increasing the gate-source voltage of the transmission transistor in the sensitive amplifier, thus enhancing the driving capability of the transmission transistor. Since the pull-up transistor is unaffected, the increase in the gamma ratio of the conduction capability of the transmission transistor to the pull-up transistor can effectively expand the write static noise margin (SNM), ensuring robustness against noise interference during data writing.

[0042] In addition, compared to traditional negative bit line technology, integrated operational amplifiers and feedback networks replace large capacitors, saving area and making them suitable for high-density SRAM. Attached Figure Description

[0043] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained from these drawings without creative effort.

[0044] Figure 1 This is a schematic diagram of the circuit principle of a 6T sensitive amplifier.

[0045] Figure 2 This is a timing diagram illustrating the principle of negative line voltage in existing technology.

[0046] Figure 3 This is a structural block diagram of a writing auxiliary circuit provided in one embodiment of this application;

[0047] Figure 4 This is a structural block diagram of a logic switching circuit provided in one embodiment of this application;

[0048] Figure 5 This is a schematic diagram of the circuit principle of a power driver provided in one embodiment of this application;

[0049] Figure 6 This is a structural block diagram of a resistor selector provided in one embodiment of this application;

[0050] Figure 7 This is a schematic diagram of the circuit principle of a resistor selector provided in one embodiment of this application;

[0051] Figure 8 This is a schematic diagram of the writing auxiliary circuit and the sensitive amplifier provided in one embodiment of this application.

[0052] Explanation of reference numerals in the attached figures:

[0053] 10. Logic switching circuit; 11. Power driver; 111. First gating transistor; 112. Second gating transistor; 1311. First NOT gate; 114. Second NOT gate; 12. First fixed resistor; 20. Inverting amplifier; 30. Resistor gating circuit; 31. Fixed resistor branch; 311. Second fixed resistor; 32. Gating branch; 321. Third gating transistor; 322. Third fixed resistor; 323. Fourth gating transistor; 324. Fourth fixed resistor; 325. Fifth gating transistor; 326. Fifth fixed resistor; 327. Sixth gating transistor; 328. Sixth fixed resistor; 40. Sensitive amplifier. Detailed Implementation

[0054] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0056] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0057] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, the terms "first," "second," "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0058] In this application, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a direct connection or an indirect connection through an intermediate medium, or the internal connection of two components or the interaction between two components. For those skilled in the art, if the connected circuits, modules, units, etc., transmit electrical signals or data to each other, they should be understood as "electrical connection," "communication connection," etc.

[0059] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0060] Figure 1 The circuit diagram shows the principle of a 6T sensitive amplifier. Figure 1As shown, a traditional 6T bitcell includes six transistors. Pull-down transistors (PD) PD1 and PD2 are cross-coupled with pull-up transistors (PU) PU1 and PU2 to form a latch structure, which latches data at the internal storage nodes SNL and SNR of the sensitive amplifier. Pass gate transistors (PG) PG1 and PG2 have their gates connected to the word line WL, and their sources and drains are connected to the bit line BL and the internal storage node, respectively, for reading and writing data.

[0061] When a memory cell performs a write operation, the bit line BL voltage is pre-pulled up (pull down) to a high (low) level before the word line WL voltage is turned on. When the word line WL signal is charged to a high level, the transmission transistors PG1 and PG2 are turned on, and data is written to the internal memory node. NBL technology increases the gate-source voltage V of the transistor by reducing the source (bit line) voltage of the transmission transistors. GS This increases its saturation current during write operations, making data easier to write. The principle timing diagram is as follows: Figure 2 As shown, VSS is the ground voltage.

[0062] Currently, capacitive coupling is commonly used to provide a negative voltage to the bit line (BL). However, this negative voltage generation circuit requires a complex bit line voltage tracking circuit, increasing the design complexity. Furthermore, the passive nature of capacitive coupling means it cannot be dynamically adjusted, making it unsuitable for adapting to the changing needs of sensitive amplifiers, such as optimization under different process angles, temperatures, or voltage conditions.

[0063] Based on this, please refer to Figure 3 , Figure 3 This is a structural block diagram of a write auxiliary circuit provided in one embodiment of the present application. The write auxiliary circuit provided in this embodiment is applied to a sensitive amplifier and includes: a logic switching circuit 10, configured such that: the input terminal is connected to the power supply voltage VDD, and the control terminal is used to receive a level control signal to provide different voltages;

[0064] The inverting amplifier 20 is configured such that its non-inverting input is grounded, its inverting input is connected to the output of the logic switching circuit 10, and its output is connected to bit line BL and inverted bit line BLB, in order to reduce the potential of bit line BL.

[0065] The resistor selector 30 is configured such that its input terminal is connected to the inverting input terminal of the inverting amplifier 20, its control terminal is used to receive the resistor control signal, and its output terminal is connected to the output terminal of the inverting amplifier 20 to provide different feedback resistor values.

[0066] Specifically, the logic switching circuit 10, the inverting amplifier 20, and the resistor selector 30 form an operational amplifier circuit. Through the combination of logic switching and feedback resistor selection, the output voltage (bit line V) of the inverting amplifier 20 is dynamically adjusted. BL / BLBThis indirectly controls the gate-source voltage V of the transmission transistor PG1 or PG2. GS Compared to traditional capacitive coupling schemes, this avoids complex tracking circuits. Furthermore, it allows for adjustment of the transmission transistor's drive capability according to the requirements of the sensitive amplifier 40, compensating for the effects of process and temperature variations.

[0067] The following is combined Figures 4 to 8 The writing auxiliary circuit provided in this embodiment is described in detail.

[0068] Please see Figure 4 In an optional embodiment, the power driver 11 is configured such that: a first terminal forms the input terminal of the logic switching circuit 10 and is connected to the power supply voltage VDD; and a second and a third terminal form the control terminal of the logic switching circuit 10.

[0069] The first fixed resistor 12 is configured such that its first end is connected to the fourth end of the power driver 11, and its second end forms the output end of the logic switching circuit 10 and is connected to the inverting input end of the inverting amplifier 20.

[0070] Specifically, in the embodiment, Ra represents the resistance value of the first fixed resistor 12. It should be understood that the resistance value of the first fixed resistor 12 can be set according to the actual situation, and there is no limitation here.

[0071] Further, please refer to Figure 5 In some embodiments, the power driver 11 includes:

[0072] The first selection transistor 111 is configured such that: its first terminal forms the first terminal of the power driver 11 and is connected to the power supply voltage VDD; its control terminal forms the second terminal of the power driver 11; and it is in the on state when it receives the corresponding level control signal.

[0073] The second gating transistor 112 is configured such that its first terminal is connected to the first terminal of the first gating transistor, and its control terminal forms the third terminal of the power driver 11, and it is in the conducting state when it receives the corresponding level control signal.

[0074] The first NOT gate 1311 is configured such that its first terminal is connected to the third terminal of the second gating transistor 112, and its second terminal is connected to the third terminal of the first gating transistor 111.

[0075] The second NOT gate 114 is configured such that its first terminal is connected to the second terminal of the first NOT gate 1311, the second terminal forms the fourth terminal of the power driver 11 and is connected to the first terminal of the first fixed resistor 12.

[0076] When the first selection transistor 111 receives the first level control signal control1, it is in the on state;

[0077] When the second selection transistor 112 receives the second level control signal control2, it is in the on state.

[0078] Specifically, when the first selector transistor 111 is turned on, the power supply voltage VDD passes through the first selector transistor 111 and then through the first NOT gate 1311, resulting in a logic low voltage signal. When the second selector transistor 112 is turned on, the power supply voltage VDD passes through the second selector transistor 112 and then through the first NOT gate 1311 and the second NOT gate 114, resulting in a logic high voltage signal. The first selector transistor 111 and the second selector transistor 112 are not turned on simultaneously to ensure that the logic states of the two voltage signals do not conflict, thereby stabilizing the output.

[0079] Please see Figure 6 In some embodiments, the resistor selector 30 includes:

[0080] The fixed resistor branch 31 includes a second fixed resistor 311, which is configured such that: its first end forms the input terminal of the resistor selector 30 and is connected to the inverting input terminal of the inverting amplifier 20; and its second end forms the output terminal of the resistor selector 30 and is connected to the output terminal of the inverting amplifier 20.

[0081] At least one selector branch 32; wherein, the selector branch 32 is configured such that: the first end is connected to the first end of the fixed resistor branch 31, the second end constitutes the control end of the resistor selector 30, and the third end is connected to the second end of the fixed resistor branch 31.

[0082] Furthermore, in some embodiments, at least one gating branch 32 includes: N gating branches 32, where N≥1 and N is an integer;

[0083] The Nth bypass 32 includes:

[0084] The (N+2)th selector transistor is configured such that: its first terminal forms the first terminal of the selector branch 32 and is connected to the first terminal of the fixed resistor branch; its control terminal forms the second terminal of the selector branch 32; and it is in the conducting state when it receives the corresponding resistor control signal.

[0085] The (N+2)th fixed resistor is configured such that its first end is connected to the second end of the (N+2)th gating transistor, and its second end forms the third end of the gating branch 32 and is connected to the second end of the fixed resistor branch 31.

[0086] In an optional embodiment, the first fixed resistor 12 and the second fixed resistor 311 have the same resistance value;

[0087] The resistance of the (N+2)th fixed resistor is inversely proportional to the resistance of the first fixed resistor, 12.

[0088] In this design, Rb1 is used to replace the resistance value of the second fixed resistor 311.

[0089] Specifically, the fixed resistor branch 31 serves as the main path, while the selected branch 32 is activated by the resistance control signal 'control' to change the overall resistance value. Each selected branch includes a selection transistor and a fixed resistor. When the selection transistor is activated, the fixed resistor of the selected branch 32 is connected in parallel with the second fixed resistor 311, thereby adjusting the total resistance. Since the resistance value of the fixed resistor in the selected branch 32 is inversely proportional to the resistance value of the first fixed resistor 12, it means that when the selected branch is activated, the total resistance will change proportionally. Therefore, by selecting different selected branches 32 through the resistance control signal 'control', the controllable adjustment of the feedback resistance value can be achieved.

[0090] As an example, in this embodiment, the resistor selector 30 includes four selection branches, i.e., N=4, resulting in the following: Figure 7 The block diagram of the resistor selector 30 shown is shown.

[0091] It is understood that, in some embodiments, the resistor control signal includes M sets of resistor control signals, where M ≥ 1 and M is an integer;

[0092] The number of resistor control signals is equal to the number of gating transistors, and one resistor control signal controls one gating transistor.

[0093] The Mth resistor control signal is denoted as controlM.

[0094] In the first selection branch, there is a third selection transistor 321 and a third fixed resistor 322. The resistance value of the third fixed resistor 322 is replaced by Rb2. When the control terminal of the third selection transistor 321 receives the first resistor control signal control1, it is in the conducting state.

[0095] In the second selection branch, the fourth selection transistor 323 and the fourth fixed resistor 324 are used, and the resistance value of the fourth fixed resistor 324 is replaced by Rb3; when the control terminal of the third selection transistor 321 receives the second resistor control signal control2, it is in the conducting state.

[0096] In the third selection branch, there is a fifth selection transistor 325 and a fifth fixed resistor 326. The resistance value of the fifth fixed resistor 326 is replaced by Rb4. When the control terminal of the fifth selection transistor 325 receives the control signal control3 from the third resistor, it is in the conducting state.

[0097] In the fourth selection branch, there is a sixth selection transistor 327 and a sixth fixed resistor 328. The resistance value of the sixth fixed resistor 328 is replaced by Rb5. When the control terminal of the sixth selection transistor 327 receives the control signal control4 from the fourth resistor, it is in the conducting state.

[0098] In some embodiments, the first gate transistor 111, the second gate transistor 112, and the N+2th gate transistor have the same conductive channel type.

[0099] In the above embodiments, using the same type of transistors ensures consistency across different process corners and reduces performance fluctuations caused by differences in transistor parameters. Furthermore, the level control signal and resistance control signal correspond one-to-one with the gating transistor, avoiding complex decoding logic, reducing the complexity of the control circuit, and thus improving reliability.

[0100] Another aspect of this application provides a memory comprising:

[0101] A storage array comprises several storage cells arranged in multiple rows and columns;

[0102] A plurality of bit lines, each of which is electrically connected to a memory cell located in the same column; and a plurality of write auxiliary circuits as described in any of the above embodiments, which are connected one-to-one to each bit line.

[0103] For example, connecting the write auxiliary circuit provided in this application to the sensitive amplifier yields the following result: Figure 8 The circuit schematic is described above. Based on the input-output relationship of the inverting amplifier, it can be known that:

[0104]

[0105] Therefore, by controlling the conduction status of the gating transistor and the values ​​of resistors Rb and Ra in the control circuit, a fixed output voltage on the bit line BL / BLB is achieved. The correspondence between the power supply voltage VDD, the gating transistor, and the output voltage is shown in Table 1.

[0106] Table 1

[0107]

[0108] Another aspect of this application provides an electronic device, including a write-assist circuit as in any of the above embodiments or a memory as in the above embodiments.

[0109] In the aforementioned electronic devices, there is no need for large-area capacitors and complex tracking circuits that are traditionally capacitively coupled. The area of ​​the write auxiliary circuit is compact, and the level and feedback resistor can be switched in real time through level control signals and resistor control signals, adapting to various working modes such as high speed and low power consumption.

[0110] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation on the present invention.

[0111] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0112] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0113] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A writing auxiliary circuit, characterized in that, Applications in sensitive amplifiers, including: The logic switching circuit is configured such that: the input terminal is connected to the power supply voltage, and the control terminal is used to receive level control signals to provide different voltages; The inverting amplifier is configured such that its non-inverting input is grounded, its inverting input is connected to the output of the logic switching circuit, and its output is connected to the bit line and the inverting bit line of the sensitive amplifier to reduce the bit line potential. A resistor selector is configured such that its input terminal is connected to the inverting input terminal of the inverting amplifier, its control terminal is used to receive a resistor control signal, and its output terminal is connected to the output terminal of the inverting amplifier to provide different feedback resistor values.

2. The writing auxiliary circuit according to claim 1, characterized in that, The logic switching circuit includes: The power driver is configured such that: the first terminal constitutes the input terminal of the logic switching circuit and is connected to the power supply voltage; and the second and third terminals constitute the control terminals of the logic switching circuit. The first fixed resistor is configured such that its first end is connected to the fourth end of the power driver, and its second end forms the output end of the logic switching circuit and is connected to the inverting input end of the inverting amplifier.

3. The writing auxiliary circuit according to claim 2, characterized in that, The power driver includes: The first gating transistor is configured such that: its first terminal forms the first terminal of the power driver and is connected to the power supply voltage, and its control terminal forms the second terminal of the power driver; and it is in the on state when it receives a corresponding level control signal. The second gating transistor is configured such that: its first terminal is connected to the first terminal of the first gating transistor, and its control terminal constitutes the third terminal of the power driver; and it is in an on state when it receives a corresponding level control signal. The first NOT gate is configured such that its first terminal is connected to the third terminal of the second gating transistor, and its second terminal is connected to the third terminal of the first gating transistor. The second NOT gate is configured such that its first terminal is connected to the second terminal of the first NOT gate, the second terminal forms the fourth terminal of the power driver and is connected to the first terminal of the first fixed resistor.

4. The writing auxiliary circuit according to claim 2, characterized in that, The resistor selector includes: A fixed resistor branch is configured such that: a first terminal forms the input terminal of the resistor selector and is connected to the inverting input terminal of the inverting amplifier; and a second terminal forms the output terminal of the resistor selector and is connected to the output terminal of the inverting amplifier; and At least one selector branch; wherein, one of the selector branches is configured such that: a first end is connected to a first end of the fixed resistor branch, a second end constitutes the control end of the resistor selector, and a third end is connected to a second end of the fixed resistor branch.

5. The writing auxiliary circuit according to claim 4, characterized in that, The at least one gating branch includes: N gating branches, where N≥1 and N is an integer; The selection branch mentioned in Article N includes: The (N+2)th selector transistor is configured such that: its first terminal forms the first terminal of the selector branch and is connected to the first terminal of the fixed resistor branch; its control terminal forms the second terminal of the selector branch; and it is in an on state when it receives the corresponding resistor control signal. The (N+2)th fixed resistor is configured such that its first end is connected to the second end of the (N+2)th gating transistor, and its second end forms the third end of the gating branch and is connected to the second end of the fixed resistor branch.

6. The write auxiliary circuit according to any one of claims 1-5, characterized in that, The first fixed resistor and the fixed resistor branch have the same resistance value; and The resistance value of the (N+2)th fixed resistor is inversely proportional to the resistance value of the first fixed resistor.

7. The write auxiliary circuit according to any one of claims 1-5, characterized in that, The first gate transistor, the second gate transistor, and the N+2th gate transistor have the same conductive channel type.

8. The write auxiliary circuit according to any one of claims 1-5, characterized in that, The resistor control signal includes M sets of resistor control signals, where M ≥ 1 and M is an integer; The number of resistor control signals is equal to the number of gating transistors in the gating branch, and each resistor control signal controls one of the gating transistors.

9. A memory, characterized in that, include: A storage array comprises several storage cells arranged in multiple rows and columns; A plurality of bit lines, each of which is electrically connected to a memory cell located in the same column; as well as Several write auxiliary circuits as described in any one of claims 1-8 are connected one-to-one with each of the bit lines.

10. An electronic device, characterized in that, include: The write auxiliary circuit as described in any one of claims 1-8; or The memory as described in claim 9.

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