A charge pump circuit with overvoltage suppression function

Abstract

This utility model relates to the field of charge pump circuit technology, specifically a charge pump circuit with overvoltage suppression function. It includes: a charge pump comprising multiple cascaded cross-coupled charge pumps, each cross-coupled charge pump including multiple flying capacitors and a switch, the flying capacitors and the switches being electrically connected; a first driving circuit including a first inverter circuit and an adjustable current unit, the signal input terminal of the first inverter circuit receiving a control signal, and the output terminal of the first inverter circuit connected to the flying capacitors; the adjustable current unit is provided on the connection paths of the first inverter circuit to VDD1 and VSS; and a register, the output terminal of which is connected to the adjustable current unit. By setting the adjustable current unit in the first driving circuit, the charging amplitude of the flying capacitors can be controlled by adjusting the size of the adjustable current unit, thus avoiding the risk of overvoltage.

Description

Technical Field

[0001] This utility model relates to the field of charge pump circuit technology, and in particular to a charge pump circuit with overvoltage suppression function. Background Technology

[0002] like Figure 1 As shown, in existing technologies, traditional charge pump circuits, with VDD1 = 2.5V, operate in negative voltage mode with relatively good power supply conditions and small process corner deviations, resulting in VDD7 = -10V, VDD6 = -7.5V, VDD5 = -5V, and VDD4 = -2.5V. To avoid overvoltage issues in DNW and sub, S1a, S2a, S3a, and S4a use transistors with a withstand voltage of 2.5V; S1b, S2b, S3b, and S4b use transistors with a withstand voltage of 5V; S1c, S2c, S3c, and S4c use transistors with a withstand voltage of 12V; and S1d, S2d, S3d, and S4d use transistors with a withstand voltage of 12V. While 12V transistors offer high withstand voltage, they also have a large area and high on-resistance, leading to lower efficiency.

[0003] Cross-coupled charge pumps can generate negative voltage and are widely used in power management and driver chip circuits. Closed-loop charge pump circuits require consideration of stability, and the ripple is not small enough. Therefore, this patent proposes an open-loop charge pump combined with an LDO (Low Dropout Regulator) to achieve adjustable output, significantly reducing output ripple and improving PSRR. However, the output voltage of the open-loop charge pump varies considerably with the power supply voltage and manufacturing process. While generating negative voltage, a high-voltage transistor is needed to prevent overvoltage, but this results in low efficiency and a large switching transistor area. To address this technical problem, this invention is proposed to solve the voltage withstand capability issue of the switching transistor. Utility Model Content

[0004] In this section, as well as in the abstract and title of this application, some simplifications or omissions may be made to avoid obscuring the purpose of this section, the abstract, and the title of this application. Such simplifications or omissions shall not be used to limit the scope of this utility model.

[0005] To address the shortcomings of existing technologies, one objective of this utility model is to provide a charge pump circuit with overvoltage suppression function.

[0006] To achieve the above objectives, this utility model adopts the following technical solution: a charge pump circuit with overvoltage suppression function, comprising: a charge pump, which includes multiple cascaded cross-coupled charge pumps, each of the cross-coupled charge pumps including multiple flying capacitors and a switch, the flying capacitors and the switches being electrically connected; a first driving circuit, including a first inverter circuit and an adjustable current unit, the signal input terminal of the first inverter circuit receiving a control signal, the output terminal of the first inverter circuit being connected to the flying capacitors; the adjustable current unit being provided on the connection path between the first inverter circuit and VDD1 and VSS; and a register, the output terminal of which is connected to the adjustable current unit.

[0007] As a preferred embodiment of the charge pump circuit with overvoltage suppression function of this utility model, it further includes a low-dropout linear regulator, the output terminal of the charge pump is connected to the input terminal of the low-dropout linear regulator; each stage of the cross-coupled charge pump includes two flying capacitors and four switches; the four switches of each stage of the cross-coupled charge pump are sequentially turned on and off under the control of control signals of different phases.

[0008] As a preferred embodiment of the charge pump circuit with overvoltage suppression function of this utility model, wherein: the adjustable current unit in the first driving circuit is one of a variable resistor, an adjustable current source, an NMOS current limiting transistor, and a PMOS current limiting transistor.

[0009] As a preferred embodiment of the charge pump circuit with overvoltage suppression function of this utility model, the first inverter circuit includes a first inverter, the gate of the first PMOS of the first inverter is connected to the gate of the first NMOS and connected to the first input terminal, the source of the first PMOS is connected to VDD1, the source of the first NMOS is connected to VSS, and the drain of the first PMOS is connected to the drain of the first NMOS and connected to the first output terminal.

[0010] As a preferred embodiment of the charge pump circuit with overvoltage suppression function of this utility model, wherein: a third variable resistor is connected in series between the source of the first PMOS and the path of VDD1, and a fourth variable resistor is connected in series between the source of the first NMOS and the path of VSS.

[0011] As a preferred embodiment of the charge pump circuit with overvoltage suppression function of this utility model, the first inverter circuit further includes a second inverter. The gate of the second PMOS of the second inverter is connected to the gate of the second NMOS and is connected to the second input terminal. The source of the second PMOS is connected to VDD1, the source of the second NMOS is connected to VSS, and the drain of the second PMOS is connected to the drain of the second NMOS and is connected to the second output terminal.

[0012] As a preferred embodiment of the charge pump circuit with overvoltage suppression function of this utility model, wherein: a first variable resistor is connected in series between the source of the second PMOS and the path of VDD1, and a second variable resistor is connected in series between the source of the second NMOS and the path of VSS.

[0013] As a preferred embodiment of the charge pump circuit with overvoltage suppression function of this utility model, the output terminal of the register is connected to a first variable resistor and a third variable resistor.

[0014] As a preferred embodiment of the charge pump circuit with overvoltage suppression function of this utility model, the first output terminal and the second output terminal are both connected to the flying capacitor.

[0015] As a preferred embodiment of the charge pump circuit with overvoltage suppression function of this utility model, it further includes: a second driving circuit, which includes: a third inverter, comprising a third PMOS and a third NMOS, wherein the gates of the third PMOS and the third NMOS are connected and connected to the third input terminal, the drains of the third PMOS and the third NMOS are connected and connected to the third output terminal, and the third output terminal is connected to a flying capacitor; a fourth inverter, comprising a fourth PMOS and a fourth NMOS, wherein the gates of the fourth PMOS and the fourth NMOS are connected and connected to the fourth input terminal, the drains of the fourth PMOS and the fourth NMOS are connected and connected to the fourth output terminal, and the fourth output terminal is connected to a flying capacitor; the sources of the third PMOS and the fourth PMOS are connected to VDD1, and the sources of the third NMOS and the fourth NMOS are connected to VSS.

[0016] The beneficial effects of this utility model are as follows: by setting a first driving circuit, and by setting an adjustable current unit, such as a variable resistor or an adjustable current source, in the first driving circuit, the amplitude of the flying capacitor charging can be controlled by adjusting the size of the variable resistor or the adjustable current source, thereby avoiding the risk of overvoltage. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a circuit diagram of a conventional charge pump in the prior art.

[0019] Figure 2 This is a circuit diagram of the charge pump circuit with overvoltage suppression function of this utility model.

[0020] Figure 3The circuit diagrams show the first and second drive circuits of the charge pump circuit with overvoltage suppression function of this utility model.

[0021] Figure 4 This is a circuit diagram of the charge pump circuit with overvoltage suppression function of this utility model when a MOSFET is used as the switch.

[0022] Figure 5 This is a circuit diagram of the adjustable current unit of the charge pump circuit with overvoltage suppression function of this utility model when it is an adjustable current source.

[0023] In the diagram: 100, charge pump; 101, flying capacitor; 102, switch; 103, cross-coupled charge pump; 200, first drive circuit; 202, first inverter circuit; 202a, first inverter; 202b, first input terminal; 202c, first output terminal; 202d, third variable resistor; 202e, fourth variable resistor; 202f, second inverter; 202g, second input terminal; 202h, second output terminal; 202i, first variable resistor; 202d, third variable resistor; 203, adjustable current unit; 300, low dropout linear regulator; 400, second drive circuit; 401, third inverter; 401a, third input terminal; 401b, fourth output terminal. Detailed Implementation

[0024] To make the objectives, features, and advantages of this utility model more apparent and understandable, the specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings.

[0025] Many specific details are set forth in the following description in order to provide a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0026] Secondly, the term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that excludes other embodiments.

[0027] Example 1

[0028] See Figure 2 and Figure 4The first specific embodiment shows the main technical content. In the first embodiment, the technical solution includes a charge pump 100, a first driving circuit 200 and a register 500. The first driving circuit 200 is used to control the charging amplitude of the charge pump 100.

[0029] Specifically, the charge pump 100 includes multiple cascaded cross-coupled charge pumps 103. In this embodiment, the cross-coupled charge pumps 103 are arranged in four stages, and the four stages of cross-coupled charge pumps 103 are cascaded together. Therefore, the charge pump 100 in this embodiment includes a total of eight flying capacitors 101 and sixteen switches 102. The sixteen switches 102 correspond to S1a, S2a, S3a, S4a, S1b, S2b, S3b, S4b, S1c, S2c, S3c, S4c, S1d, S2d, S3d, and S4d in the figure, respectively. For example, there is a flying capacitor 101 between S1a and S3a, and there is a flying capacitor 101 between S2a and S4a, so that the flying capacitors 101 and the switches 102 are electrically connected. A negative voltage output is generated through VDD1 = 2.5V. The eight flying capacitors 101 are used to transfer charge in the circuit to realize voltage conversion and boosting. The primary function of the charge pump 100 is to boost or stabilize voltage. Simply put, it acts like a "voltage booster," increasing the absolute value of the input voltage to a higher value and stabilizing it at a certain level. The charge pump 100 ultimately outputs a stable voltage.

[0030] The first driving circuit 200 includes a first inverter circuit 202 and an adjustable current unit 203. The signal input terminal of the first inverter circuit 202 receives a control signal, which includes an alternating clock signal CLK and an inverted clock signal CLKB. The output terminal of the first inverter circuit 202 is connected to a flying capacitor 101. Adjustable current units 203 are provided on the connection paths between the first inverter circuit 202 and VDD1 and VSS. By adjusting the adjustable current unit 203, the charging amplitude of the flying capacitor 101 can be controlled to avoid overvoltage risks.

[0031] The output of register 500 is connected to the adjustable current unit 203, and register 500 is used to adjust the adjustable current unit 203.

[0032] like Figure 4 As shown, in some embodiments, switch 102 includes, but is not limited to, NMOS transistors, PMOS transistors, transmission gates, or other methods of implementing a switch, while switch 102 in this embodiment can be an NMOS transistor or a PMOS transistor.

[0033] The cross-coupled charge pump 103 is existing technology and will not be described in detail here. Taking one stage of the cross-coupled charge pump 103 as an example, consider the operation of switches S1a, S2a, S3a, and S4a: In the first half-cycle, when the clock signal CLK closes S1a and S4a, the two ends of the upper flying capacitor 101 are connected to VSS and the output of the first inverter 202a, respectively. The upper flying capacitor 101 begins to charge, like filling a bucket with water. The charging path is: VDD1 → upper flying capacitor 101 → ground VSS. In the second half-cycle, when the clock signal CLK opens S1a and S4a, the two ends of the upper flying capacitor 101 are connected to VDD4 and the output of the first inverter 202a, respectively. The upper flying capacitor 101 begins discharging at node VDD4. Since the first half of the cycle charges the voltage across the upper flying capacitor 101 to VDD1, the voltage across flying capacitor 101 cannot change abruptly. At this time, the output of the first inverter 202a is VSS, so VDD4 = VSS - VDD1 = -VDD1. The charging and discharging process of the lower flying capacitor 101 is complementary to that of the upper flying capacitor 101. That is, when the upper flying capacitor 101 is charging, the lower flying capacitor 101 is discharging, and vice versa.

[0034] Example 2

[0035] See Figures 2-4 The main technical content of the second specific implementation is shown. This embodiment is based on embodiment 1.

[0036] Specifically, it also includes a low-dropout linear regulator 300, with the output terminal of the charge pump 100 connected to the input terminal of the low-dropout linear regulator 300; the low-dropout linear regulator 300 further stabilizes the voltage output by the charge pump 100, ensuring that the output voltage VOUT7 is stable.

[0037] Each stage of the cross-coupled charge pump 103 includes two flying capacitors 101 and four switches 102; the four switches 102 of each stage of the cross-coupled charge pump 103 are turned on and off sequentially under the control of control signals of different phases.

[0038] Preferably, the adjustable current unit 203 in the first driving circuit 200 is one of a variable resistor, an adjustable current source, an NMOS current-limiting transistor, and a PMOS current-limiting transistor. In this embodiment, the adjustable current unit 203 is a variable resistor.

[0039] Preferably, the first inverter circuit 202 includes a first inverter 202a. The gate of the first PMOS transistor of the first inverter 202a is connected to the gate of the first NMOS transistor and is also connected to the first input terminal 202b. The source of the first PMOS transistor is connected to VDD1, the source of the first NMOS transistor is connected to VSS, and the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor and is also connected to the first output terminal 202c. The first input terminal 202b is used to input the clock signal CLK, and the first output terminal 202c is connected to the flying capacitor 101.

[0040] Preferably, a third variable resistor 202d is connected in series in the path between the source of the first PMOS and VDD1, and a fourth variable resistor 202e is connected in series in the path between the source of the first NMOS and VSS.

[0041] Preferably, the first inverter circuit 202 further includes a second inverter 202f. The gate of the second PMOS of the second inverter 202f is connected to the gate of the second NMOS and is also connected to the second input terminal 202g. The source of the second PMOS is connected to VDD1, the source of the second NMOS is connected to VSS, and the drain of the second PMOS is connected to the drain of the second NMOS and is also connected to the second output terminal 202h. The second input terminal 202g is used to input the inverse clock signal CLKB, and the second output terminal 202h is connected to the flying capacitor 101.

[0042] Preferably, a first variable resistor 202i is connected in series in the path between the source of the second PMOS and VDD1, and a second variable resistor 202j is connected in series in the path between the source of the second NMOS and VSS.

[0043] Furthermore, the output of register 500 is connected to the first variable resistor 202i and the third variable resistor 202d. Register 500 is used to adjust the first variable resistor 202i and the third variable resistor 202d.

[0044] This embodiment uses a variable resistor to control the charging amplitude of the flying capacitor 101, thereby avoiding the risk of overvoltage. It is assumed that the on-resistance of the BUF is negligible. The output voltage of the first driving circuit 200 is VDD91-e. -(t / RC) By adjusting the value of the variable resistor, we can control VDD5 to within 3.3V and VDD6 to within 5V. In this way, S1b, S2b, S3b, and S4b can use transistors with a withstand voltage of 3.3V to replace the 5V transistors, and S1c, S2c, S3c, and S4c can use transistors with a withstand voltage of 5V to replace the 12V transistors. This achieves both space saving and higher circuit efficiency.

[0045] In some embodiments, a second driving circuit 400 may also be included, comprising: a third inverter 401, including a third PMOS and a third NMOS, wherein the gates of the third PMOS and the third NMOS are connected and connected to a third input terminal 401a, the drains of the third PMOS and the third NMOS are connected and connected to a third output terminal 401b, and the third output terminal 401b is connected to the flying capacitor 101 above the end-cross-coupled charge pump 103; a fourth inverter 402, including a fourth PMOS and a fourth NMOS, wherein the gates of the fourth PMOS and the fourth NMOS are connected and connected to a fourth input terminal 402a, the drains of the fourth PMOS and the fourth NMOS are connected and connected to a fourth output terminal 402b, and the fourth output terminal 402b is connected to the flying capacitor 101 below the end-cross-coupled charge pump 103; the sources of the third PMOS and the fourth PMOS are connected to VDD1, and the sources of the third NMOS and the fourth NMOS are connected to VSS.

[0046] Example 3

[0047] See Figure 5 The main technical content of the third specific implementation is shown. This embodiment is based on embodiment 2.

[0048] This embodiment is basically the same as embodiment 2, except that the adjustable current unit 203 in this embodiment uses an adjustable current source, which is controlled by register 500. The output voltage is VDD2*I / (2Cf), where f is the switching frequency of the cross-coupled charge pump 103. For ease of analysis, we assume I = I1 = I2. By controlling the current, we keep VDD5 below 3.3V and VDD6 below 5V. Thus, S1b, S2b, S3b, and S4b use 3.3V transistors to replace 5V transistors, and S1c, S2c, S3c, and S4c use 5V transistors to replace 12V transistors, achieving both space saving and higher circuit efficiency.

[0049] Furthermore, simulations show that under the same aspect ratio, length, and bias conditions, the Ron of a 2.5V transistor is 48.6Ω, that of a 3.3V transistor is 48.7Ω, that of a 5V transistor is 81.0Ω, and that of a 12V transistor is 82.0Ω. The minimum possible lengths are 0.28µm, 0.5µm, 0.833µm, and 1.115µm, respectively. This means that to achieve the same on-resistance, the required area ratio for 3.3V, 5V, and 12V transistors is 13.6:24.4:67.5:91.4. Larger transistors also mean larger gate capacitance and switching losses. The solution proposed in this patent can reduce the area by 34% compared to traditional solutions.

[0050] It should be noted that the above embodiments are only used to illustrate the technical solution of this utility model and are not intended to limit it. Although this utility model has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solution of this utility model without departing from the spirit and scope of the technical solution of this utility model, and all such modifications or substitutions should be covered within the scope of the claims of this utility model.

Claims

1. A charge pump circuit with overvoltage suppression function, characterized in that: include, A charge pump (100) includes a plurality of cross-coupled charge pumps (103) cascaded in sequence, each of the cross-coupled charge pumps (103) including a plurality of flying capacitors (101) and switches (102), the flying capacitors (101) and the switches (102) being electrically connected; The first driving circuit (200) includes a first inverter circuit (202) and an adjustable current unit (203). The signal input terminal of the first inverter circuit (202) receives a control signal, and the output terminal of the first inverter circuit (202) is connected to the flying capacitor (101). The adjustable current unit (203) is provided on the connection path between the first inverter circuit (202) and VDD1 and VSS. The register (500) has its output connected to the adjustable current unit (203).

2. The charge pump circuit with overvoltage suppression function as described in claim 1, characterized in that: It also includes a low-dropout linear regulator (300), the output of which is connected to the input of the low-dropout linear regulator (300); Each stage of the cross-coupled charge pump (103) includes two flying capacitors (101) and four switches (102); the four switches (102) of each stage of the cross-coupled charge pump (103) are turned on and off sequentially under the control of control signals of different phases.

3. The charge pump circuit with overvoltage suppression function as described in claim 1 or 2, characterized in that: The adjustable current unit (203) in the first driving circuit (200) is one of a variable resistor, an adjustable current source, an NMOS current-limiting transistor, and a PMOS current-limiting transistor.

4. The charge pump circuit with overvoltage suppression function as described in claim 1 or 2, characterized in that: The first inverter circuit (202) includes a first inverter (202a). The gate of the first PMOS of the first inverter (202a) is connected to the gate of the first NMOS and is connected to the first input terminal (202b). The source of the first PMOS is connected to VDD1, the source of the first NMOS is connected to VSS, and the drain of the first PMOS is connected to the drain of the first NMOS and is connected to the first output terminal (202c).

5. The charge pump circuit with overvoltage suppression function as described in claim 4, characterized in that: A third variable resistor (202d) is connected in series between the source of the first PMOS and the path of VDD1, and a fourth variable resistor (202e) is connected in series between the source of the first NMOS and the path of VSS.

6. The charge pump circuit with overvoltage suppression function as described in claim 5, characterized in that: The first inverter circuit (202) further includes a second inverter (202f). The gate of the second PMOS of the second inverter (202f) is connected to the gate of the second NMOS and is connected to the second input terminal (202g). The source of the second PMOS is connected to VDD1, the source of the second NMOS is connected to VSS, and the drain of the second PMOS is connected to the drain of the second NMOS and is connected to the second output terminal (202h).

7. The charge pump circuit with overvoltage suppression function as described in claim 6, characterized in that: A first variable resistor (202i) is connected in series between the source of the second PMOS and the path of VDD1, and a second variable resistor (202j) is connected in series between the source of the second NMOS and the path of VSS.

8. The charge pump circuit with overvoltage suppression function as described in claim 7, characterized in that: The output of the register (500) is connected to the first variable resistor (202i) and the third variable resistor (202d).

9. The charge pump circuit with overvoltage suppression function as described in claim 6, characterized in that: Both the first output terminal (202c) and the second output terminal (202h) are connected to the flying capacitor (101).

10. The charge pump circuit with overvoltage suppression function as described in claim 1, characterized in that: It also includes a second drive circuit (400), which includes, The third inverter (401) includes a third PMOS and a third NMOS. The gates of the third PMOS and the third NMOS are connected and connected to the third input terminal (401a). The drains of the third PMOS and the third NMOS are connected and connected to the third output terminal (401b). The third output terminal (401b) is connected to the flying capacitor (101). The fourth inverter (402) includes a fourth PMOS and a fourth NMOS. The gates of the fourth PMOS and the fourth NMOS are connected and connected to the fourth input terminal (402a). The drains of the fourth PMOS and the fourth NMOS are connected and connected to the fourth output terminal (402b). The fourth output terminal (402b) is connected to the flying capacitor (101). The source terminals of the third and fourth PMOS are connected to VDD1, and the source terminals of the third and fourth NMOS are connected to VSS.

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