A switching mechanism and an imaging chip
By introducing a 10V switching circuit and control switches for some high-voltage transistors into the imaging chip, the problems of high design complexity and high power consumption in the prior art are solved, resulting in a simpler circuit design and lower power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- NANJING VPS SEMICONDUCTOR TECHNOLOGY CO LTD
- Filing Date
- 2025-06-04
- Publication Date
- 2026-05-26
AI Technical Summary
Existing imaging chips have complex switching circuit designs, high power consumption, and require high-voltage devices, which increases the layout area.
Design a switching mechanism that includes a 10V switching circuit, using some high-voltage transistors, and achieve voltage separation and transmission by controlling the switch, thereby reducing the use of high-voltage devices.
It reduces the design complexity and power consumption of imaging chips, decreases the layout area, and simplifies the use of high-voltage devices.
Smart Images
Figure CN224289771U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the technical field of imaging devices, and in particular to a switching mechanism and an imaging chip. Background Technology
[0002] In existing patent CN202311188198.6, a multi-channel word line driving circuit for a composite dielectric gate dual-transistor photodetector is proposed, such as... Figure 1 The diagram shows a word line driving circuit. To improve the consistency of pixel thresholds, pixels can be programmed and erased. This process is typically completed before the imaging chip leaves the factory. During programming, a positive high voltage (typically 10V) is applied to the pixel gate, and a negative voltage (typically -3V) is applied to the source and substrate. During erasure, a negative voltage (typically -3V) is applied to the pixel gate, and a high voltage (typically 10V) is applied to the source and substrate. The pixel's source and substrate are usually connected to ports, so voltage can be applied directly. Programming and erasing are usually performed before the chip leaves the factory, and no programming or erasure operation is required after leaving the factory. The -3V during erasure can be achieved by configuring EN_RST to be high and EN_RAMP and EN_EXP to be low, with the negative voltage of HVWLNC1 applied to the pixel's word line.
[0003] To output programmed positive high voltage, according to... Figure 1 The approach requires integrating the output programming high voltage and the ramp voltage generation (HVWLPC2) module together. The module that generates the 1V-5V ramp voltage operates in the 5V-6V voltage range. If the output programming high voltage is to be integrated, the ramp voltage generation module needs to be implemented using high-voltage devices and operate under high voltage, resulting in high design complexity, large layout area, and high power consumption. Utility Model Content
[0004] In view of the problems existing in the above-mentioned switching mechanisms and imaging chips, this utility model is proposed.
[0005] Therefore, one of the objectives of this utility model is to provide a switching mechanism, the purpose of which is to provide a 10V switching circuit specifically for programming.
[0006] To solve the above-mentioned technical problems, this utility model provides the following technical solution: a switching mechanism for a composite dielectric gate dual transistor, comprising,
[0007] The power input port is used to input the first voltage.
[0008] The ramp voltage port is used to input a ramp-shaped second voltage.
[0009] A first power supply port, which is connected to the power receiving port via a line, and also connected to the ramp voltage port via a line; and...
[0010] Multiple control switches, including a first switch and a second switch disposed between the power receiving port and the power supply port, and a third switch disposed between the ramp voltage port and the power supply port.
[0011] In a preferred embodiment of the switching mechanism of this utility model, the power connection port is connected to a ramp power supply voltage port via a line for supplying power to the ramp voltage generator.
[0012] The plurality of control switches also include a fourth switch and a fifth switch disposed between the power connection port and the ramp power supply voltage port;
[0013] The ramp power supply voltage port generates a second voltage, and the ramp power supply voltage port and the ramp voltage port are connected through a ramp voltage generator.
[0014] As a preferred embodiment of the switching mechanism described in this utility model, it further includes a level shifter, which includes an enable port, a first power supply voltage, a first output signal port, a second output signal port, and a second power supply voltage.
[0015] The first output signal port is connected to the third switch via a line;
[0016] The second output signal port is connected to the first switch and the second switch via a line;
[0017] The second power supply voltage is connected to the fourth and fifth switches.
[0018] In a preferred embodiment of the switching mechanism described in this utility model, the control switch is made of a PMOS transistor comprising a source, a drain, a gate, and an N-well.
[0019] The source and N-well of the first switch are connected to the power-on port via a line, the gate of the first switch is connected to the second output signal port via a line, and the drain of the first switch is connected to the source of the second switch via a line.
[0020] The gate of the second switch is connected to the second output signal port via a line, and the drain and N-well of the second switch are connected to the first power supply port via a line.
[0021] In a preferred embodiment of the switching mechanism of this utility model, the source of the third switch is connected to the ramp voltage port via a line, the gate of the third switch is connected to the first output signal port via a line, and the drain and N-well of the third switch are connected to the first power supply port via a line.
[0022] In a preferred embodiment of the switching mechanism of this utility model, the drain of the fourth switch is connected to the power-on port via a line, the gate of the fourth switch is connected to the ramp power supply voltage port via a line, the source of the fourth switch is connected to the drain of the fifth switch via a line, and the N-well of the fourth switch is connected to the N-well of the fifth switch via a line.
[0023] The source of the fifth switch is connected to the ramp power supply voltage port via a line, and the gate of the fifth switch is connected to the source of the fourth switch, the drain of the fifth switch, the N-well of the fourth switch, the N-well of the fifth switch, and the second power supply voltage via a line.
[0024] In a preferred embodiment of the switching mechanism described in this utility model, the drain output voltage of the fifth switch is the larger of the first voltage and the second voltage.
[0025] In a preferred embodiment of the switching mechanism described in this utility model, the first voltage input at the power connection port is 10V;
[0026] The ramp voltage port is used to input a second voltage of 1-5V for the ramp shape.
[0027] The advantages of this switching circuit are: when programming, a separate 10V switching circuit is designed, and only some transistors in the switching circuit need to use high-voltage devices, avoiding the need for a large number of high-voltage devices and a high-voltage power supply in the HVWLPC2 module.
[0028] Therefore, another objective of this invention is to provide an imaging chip, which includes a dedicated 10V switching circuit for programming.
[0029] To solve the above-mentioned technical problems, this utility model provides the following technical solution: an imaging chip, including the switching mechanism, and further comprising;
[0030] The main body, wherein the switching mechanism is located inside the main body;
[0031] An interface is provided on the main body and is connected to the power connection port via a line.
[0032] As a preferred embodiment of the imaging chip of this utility model, the body has a multi-channel word line driving circuit inside;
[0033] The multi-channel word line driving circuit is connected to the first power supply port via a line.
[0034] The beneficial effects of this utility model are as follows: A dedicated interface is configured in the main body, which can be connected to a 10V circuit configuration module before the product leaves the factory. This circuit configuration module is only connected when the pixels are programmed and erased. After the programming and erasure are completed, the product will be disconnected from the imaging chip before leaving the factory. This reduces the layout area, design complexity, and power consumption of the module that generates photosensitive voltage or ramp voltage in the imaging chip. Attached Figure Description
[0035] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0036] Figure 1 The existing word line driver circuit diagram is shown;
[0037] Figure 2 A schematic diagram of the overall structure of Embodiment 1 is shown;
[0038] Figure 3 A schematic diagram of the drain output voltage of the fifth switch in Embodiment 2 is shown;
[0039] Figure 4 A schematic diagram of the level shifter in Embodiment 2 is shown;
[0040] Figure 5 A schematic diagram of the control switch for Embodiment 2 is shown;
[0041] Figure 6 An overall schematic diagram of Embodiment 3 is shown;
[0042] Figure 7 A multi-channel word line driving circuit diagram of Embodiment 3 is shown.
[0043] In the diagram: 101, Power input port; 102, Ramp voltage port; 103, First power supply port; 104, Control switch; 104a, First switch; 104b, Second switch; 104c, Third switch; 105, Ramp power supply voltage port; 104d, Fourth switch; 104e, Fifth switch; 106, Level shifter; 106a, Enable port; 106b, First power supply voltage; 106c, First output signal port; 106d, Second output signal port; 106e, Second power supply voltage; 107, Ramp voltage generator; 201, Main body; 202, Interface; 203, Multi-channel word line driver circuit. Detailed Implementation
[0044] To enable those skilled in the art to better understand this utility model, the present utility model will be further described in detail below with reference to specific embodiments and accompanying drawings.
[0045] The terminology used in this invention refers to those general terms currently widely used in the art in consideration of the functionality of this invention; however, these terms may vary according to the intent, precedent, or new technology of those skilled in the art. Furthermore, specific terms may be chosen by the applicant, and in such cases, their detailed meanings will be described in the detailed description of this invention. Therefore, the terminology used in this specification should not be construed as simple names, but rather based on the meaning of the terms and the overall description of this invention.
[0046] Example 1, referring to Figure 2 This is the first embodiment of the present invention, which provides a switching mechanism, the mechanism comprising:
[0047] Power input port 101 is used to input a first voltage, wherein power input port 101 is HVPROG; ramp voltage port 102 is used to input a ramp-shaped second voltage, wherein ramp voltage port 102 is HVWLPC2.
[0048] The first power supply port 103 is connected to the power connection port 101 via a line, and is also connected to the ramp voltage port 102 via a line; wherein the first power supply port 103 is HVWLPC2'.
[0049] Multiple control switches 104 include a first switch 104a and a second switch 104b disposed between the power connection port 101 and the power supply port, and a third switch 104c disposed between the ramp voltage port 102 and the power supply port, wherein the first switch 104a is MP1, the second switch 104b is MP2, and the third switch 104c is MP3.
[0050] Furthermore, the power connection port 101 is used to input a first voltage of 10V; the ramp voltage port 102 is used to input a second voltage of 1-5V.
[0051] During use, when the first voltage is input at the power connection port 101, the first switch 104a and the second switch 104b are turned on, the third switch 104c is turned off, and the voltage of HVPROG is transmitted to HVWLPC2'. When the second voltage is input at the ramp voltage port 102, the first switch 104a and the second switch 104b are turned off, the third switch 104c is turned on, and the voltage of HVWLPC2 is transmitted to HVWLPC2'.
[0052] Example 2, refer to Figures 2-5This is the second embodiment of the present invention. This embodiment differs from the first embodiment in that the power connection port 101 is connected to a ramp power supply voltage port 105 via a line, wherein the ramp power supply voltage port 105 is VDD_RAMP. It should be noted that the power signal used to power the ramp voltage generator 107 can be introduced through the ramp power supply voltage port 105, or it can be introduced from another power port nearby in the circuit that is also more convenient.
[0053] The multiple control switches 104 also include a fourth switch 104d and a fifth switch 104e disposed between the power connection port 101 and the ramp power supply voltage port 105; wherein the fourth switch 104d is MP4 and the fifth switch 104e is MP5.
[0054] The ramp power supply voltage port 105 generates a second voltage. The ramp power supply voltage port 105 and the ramp voltage port 102 are connected through the ramp voltage generator 107. The second voltage generated by the ramp power supply voltage port 105 is input to the ramp voltage port 102 through the ramp voltage generator 107.
[0055] It also includes a level shifter 106, which includes an enable port 106a, a first supply voltage 106b, a first output signal port 106c, a second output signal port 106d, and a second supply voltage 106e, wherein the first supply voltage 106b is also referred to as the low voltage domain supply voltage, and the second supply voltage 106e is also referred to as the high voltage domain supply voltage.
[0056] The first output signal port 106c is connected to the third switch 104c via a line; the second output signal port 106d is connected to the first switch 104a and the second switch 104b via a line; the second power supply voltage 106e is connected to the fourth switch 104d and the fifth switch 104e.
[0057] Furthermore, such as Figure 5 As shown, the control switch 104 is made of a PMOS transistor including a source, drain, gate and N-well.
[0058] The source and N-well of the first switch 104a are connected to the power-on port 101 via a line, the gate of the first switch 104a is connected to the second output signal port 106d via a line, and the drain of the first switch 104a is connected to the source of the second switch 104b via a line.
[0059] The gate of the second switch 104b is connected to the second output signal port 106d via a line, and the drain and N-well of the second switch 104b are connected to the first power supply port 103 via a line.
[0060] The source of the third switch 104c is connected to the ramp voltage port 102 via a line, the gate of the third switch 104c is connected to the first output signal port 106c via a line, and the drain and N-well of the third switch 104c are connected to the first power supply port 103 via a line.
[0061] The drain of the fourth switch 104d is connected to the power-on port 101 via a line; the gate of the fourth switch 104d is connected to the ramp power supply voltage port 105 via a line; the source of the fourth switch 104d is connected to the drain of the fifth switch 104e via a line; and the N-well of the fourth switch 104d is connected to the N-well of the fifth switch 104e via a line.
[0062] The source of the fifth switch 104e is connected to the ramp power supply voltage port 105 via a line. The gate of the fifth switch 104e is connected to the source of the fourth switch 104d, the drain of the fifth switch 104e, the N-well of the fourth switch 104d, the N-well of the fifth switch 104e, and the second power supply voltage 106e via a line. The drain output voltage of the fifth switch 104e is the larger of the first voltage and the second voltage.
[0063] The enable port 106a is EN_PROG, the first power supply voltage 106b is VDD1, the electrical signal of the first output signal port 106c is VOP, the electrical signal of the second output signal port 106d is VON, and the drain output electrical signal of the fifth switch 104e and the electrical signal received by the second power supply voltage 106e are VT.
[0064] The first supply voltage 106b provides a low voltage domain for the enable port 106a, and the second supply voltage 106e provides a high voltage domain for the enable port 106a.
[0065] When the first voltage is input to the power connection port 101, the voltage at the power connection port 101 is greater than that at the ramp power supply voltage port 105, i.e., HVPROG > VDD_RAMP, VT is approximately equal to HVPROG, EN_PROG is at a high level with a value of VDD1, then VOP = VT, VON = 0. At this time, MP1 and MP2 are turned on, MP3 is turned off, and the voltage of HVPROG is transmitted to HVWLPC2'.
[0066] When no first voltage is input to the power connection port 101, HVPROG < VDD_RAMP, VT is approximately equal to VDD_RAMP, EN_PROG is low and has a value of 0, VOP = 0, VON = VT. At this time, MP2 is turned off, MP3 is turned on, and the voltage of HVWLPC2 is transmitted to HVWLPC2'.
[0067] The remaining structure is the same as that in Example 1.
[0068] Example 3, referring to Figure 6 and Figure 7 This is the third embodiment of the present invention, which provides an imaging chip, the chip comprising:
[0069] The switching mechanism also includes a body 201, which is located inside the body 201.
[0070] Interface 202 is located on the main body 201 and is connected to the power port 101 via a line.
[0071] The main body 201 has a multi-channel word line driving circuit 203 inside; the multi-channel word line driving circuit 203 is connected to the first power supply port 103 through a line.
[0072] Interface 202 is used to connect an external 10V circuit configuration module. This circuit configuration module is only connected when the pixels are programmed and erased. After programming and erasing are completed, the module will be disconnected from the imaging chip before the product leaves the factory.
[0073] During programming, when the circuit configuration module is connected to an external 10V voltage, the first voltage is input to the power port 101. At this time, HVPROG > VDD_RAMP, VT is approximately equal to HVPROG, EN_PROG is high and its value is VDD1, then VOP = VT, VON = 0. At this time, MP1 and MP2 are turned on, MP3 is turned off, and the voltage of HVPROG is transmitted to HVWLPC2' for programming operation. When not programming, and the first voltage is not input to the power port 101, HVPROG < VDD_RAMP, VT is approximately equal to VDD_RAMP, EN_PROG is low and its value is 0, VOP = 0, VON = VT. At this time, MP2 is turned off, MP3 is turned on, and the voltage of HVWLPC2 is transmitted to HVWLPC2'.
[0074] After leaving the factory, no programming is required. Power-on port 101 is either floating or grounded. VT is VGS (the voltage difference between the gate and source of the PMOS transistor) lower than VDD_RAMP. EN_PROG is always low, so VOP = 0 and VON = VT. At this time, MP3 is turned on and MP2 is turned off. The voltage of HVWLPC2 is transmitted to HVWLPC2'. Since the high and low levels of HVPROG and HVWLPC2' are uncertain, the N-well of MP1 is connected to HVPROG and the N-well of MP2 is connected to HVWLPC2'.
[0075] according to Figure 1In this way, the first voltage of the output programming is integrated with the module that generates HVWLPC1 or HVWLPC2. The module that generates HVWLPC2, which is 1V-5V, operates in the voltage range of 5V to 6V. If the first voltage of the output programming is to be integrated, the module that generates the ramp voltage HVWLPC2 needs to be implemented with high-voltage devices and operate under high voltage, which results in high design complexity, large layout area, and high power consumption.
[0076] In this embodiment, the switching mechanism only requires high-voltage transistors to be used in a portion of the transistors in the circuit. The module that generates HVWLPC2 uses high-voltage transistors over a large area, which significantly reduces design complexity, layout area, and power consumption.
[0077] It should be noted that the above embodiments are only used to illustrate the technical solution of this utility model and are not intended to limit it. Although this utility model has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solution of this utility model without departing from the spirit and scope of the technical solution of this utility model, and all such modifications or substitutions should be covered within the scope of the claims of this utility model.
Claims
1. A switching mechanism for a composite dielectric gate dual transistor, characterized in that: include, The power input port (101) is used to input the first voltage; A ramp voltage port (102) is used to input a ramp-shaped second voltage; The first power supply port (103) is connected to the power receiving port (101) via a line, and is also connected to the ramp voltage port (102) via a line; and, Multiple control switches (104) include a first switch (104a) and a second switch (104b) disposed between the power connection port (101) and the power supply port, and a third switch (104c) disposed between the ramp voltage port (102) and the power supply port.
2. The switching mechanism according to claim 1, characterized in that: The power connection port (101) is connected to a ramp power supply voltage port (105) via a line, which is used to supply power to the ramp voltage generator (107); The plurality of control switches (104) also include a fourth switch (104d) and a fifth switch (104e) disposed between the power connection port (101) and the ramp power supply voltage port (105); The ramp power supply voltage port (105) generates a second voltage, and the ramp power supply voltage port (105) and the ramp voltage port (102) are connected through a ramp voltage generator (107).
3. The switching mechanism according to claim 2, characterized in that: It also includes a level shifter (106), which includes an enable port (106a), a first supply voltage (106b), a first output signal port (106c), a second output signal port (106d), and a second supply voltage (106e). The first output signal port (106c) is connected to the third switch (104c) via a line; The second output signal port (106d) is connected to the first switch (104a) and the second switch (104b) via a line; The second power supply voltage (106e) is connected to the fourth switch (104d) and the fifth switch (104e).
4. The switching mechanism according to claim 3, characterized in that: The control switch (104) is made of a PMOS transistor including a source, drain, gate and N-well; The source and N-well of the first switch (104a) are connected to the power-on port (101) via a line, the gate of the first switch (104a) is connected to the second output signal port (106d) via a line, and the drain of the first switch (104a) is connected to the source of the second switch (104b) via a line. The gate of the second switch (104b) is connected to the second output signal port (106d) via a line, and the drain and N-well of the second switch (104b) are connected to the first power supply port (103) via a line.
5. The switching mechanism according to claim 4, characterized in that: The source of the third switch (104c) is connected to the ramp voltage port (102) via a line, the gate of the third switch (104c) is connected to the first output signal port (106c) via a line, and the drain and N-well of the third switch (104c) are connected to the first power supply port (103) via a line.
6. The switching mechanism according to claim 4 or 5, characterized in that: The drain of the fourth switch (104d) is connected to the power-on port (101) via a line; the gate of the fourth switch (104d) is connected to the ramp power supply voltage port (105) via a line; the source of the fourth switch (104d) is connected to the drain of the fifth switch (104e) via a line; and the N-well of the fourth switch (104d) is connected to the N-well of the fifth switch (104e) via a line. The source of the fifth switch (104e) is connected to the ramp power supply voltage port (105) via a line. The gate of the fifth switch (104e) is connected to the source of the fourth switch (104d), the drain of the fifth switch (104e), the N-well of the fourth switch (104d), the N-well of the fifth switch (104e), and the second power supply voltage (106e) via a line.
7. The switching mechanism according to claim 6, characterized in that: The drain output voltage of the fifth switch (104e) is the larger of the first voltage and the second voltage.
8. The switching mechanism according to any one of claims 1-5 and 7, characterized in that: The first voltage input at the power connection port (101) is 10V; The ramp voltage port (102) is used to input a second voltage of 1-5V for the ramp shape.
9. An imaging chip, characterized in that: Including the switching mechanism, and also including; The main body (201) has a switching mechanism located inside it. An interface (202) is provided on the main body (201) and is connected to the power connection port (101) via a line.
10. The imaging chip according to claim 9, characterized in that: The body (201) has a multi-channel word line driving circuit (203) inside; The multi-channel word line driving circuit (203) is connected to the first power supply port (103) via a line.