An encryption / decryption device with communication capabilities

Abstract

This utility model discloses an encryption / decryption device with communication functionality. The device includes a motherboard with a communication area and an encryption / decryption area. The communication area contains a first optical module, a first 10 Gigabit Ethernet controller, a first CPU, an FPGA, and a second optical module, all electrically connected in sequence. The encryption / decryption area contains a third optical module, a second 10 Gigabit Ethernet controller, and a second CPU, all electrically connected in sequence. The second and third optical modules are connected via optical fiber. In this utility model, the second CPU encrypts and decrypts the transmitted data, then the FPGA performs format verification, and finally forwards the encrypted data. This entire process achieves data encryption, ensuring the security of data transmission over the network. Furthermore, this utility model utilizes miniaturized devices such as the 10 Gigabit Ethernet controller and the 10 Gigabit optical module, significantly improving the data transmission rate. It also solves the problem of existing communication boards being bulky and inconvenient to carry.

Description

Technical Field

[0001] This utility model relates to the field of communications, specifically to an encryption / decryption device with communication functions. Background Technology

[0002] In recent years, with the development of computer network technology, data transmission via networks has become increasingly widespread, making data leakage a major concern. In real life, data transmission faces many threats that can lead to data loss or leakage. Once data is lost or leaked, it inevitably raises questions about users' trust in communication services, thus creating a significant demand for secure data transmission.

[0003] To improve data security, the most effective method currently is to encrypt and decrypt the data; only through encryption can data security be ensured. However, the company's communication boards, as the carriers of data transmission, have virtually no security measures in place, leaving them completely unprotected. This results in significant security risks such as interception and tampering of data transmissions within the network. Utility Model Content

[0004] Purpose of this utility model: The purpose of this utility model is to provide an encryption and decryption device with communication functions, solving the security problems of existing communication boards that lack any protection measures for data transmission security, leading to interception and tampering of data transmission in the network. This utility model ensures the security of data transmission in the network by adding an encryption and decryption area to the motherboard to encrypt and decrypt the transmitted data.

[0005] Technical solution: This utility model discloses an encryption / decryption device with communication function, comprising a motherboard, wherein a communication area and an encryption / decryption area are provided on the motherboard; the communication area is provided with a first optical module, a first 10 Gigabit Ethernet controller, a first CPU, an FPGA and a second optical module connected in sequence; the encryption / decryption area is provided with a third optical module, a second 10 Gigabit Ethernet controller and a second CPU connected in sequence; the second optical module and the third optical module are connected by optical fiber.

[0006] Furthermore, both the first CPU and the second CPU are i9-13950HX CPUs.

[0007] Furthermore, the first CPU is connected to the first solid-state drive and the first DDR4 memory; the second CPU is connected to the second solid-state drive and the second DDR4 memory.

[0008] Furthermore, both the communication area and the encryption / decryption area are equipped with a power input interface, which is used to input 42V / 160W power.

[0009] Furthermore, the first optical module, the second optical module, and the third optical module are all 10 Gigabit optical modules, and the model of the 10 Gigabit optical module is E25GSFP28SR.

[0010] Furthermore, the first 10 Gigabit Ethernet controller and the second 10 Gigabit Ethernet controller are both Intel 82599ES; the FPGA is an XC7K325T-2FFG676C.

[0011] Furthermore, the motherboard is fixedly mounted on the housing, which is an aluminum alloy housing.

[0012] Furthermore, the motherboard is also equipped with a gigabit debugging network port, a debugging serial port, a display interface, and a USB interface.

[0013] The beneficial effects of this utility model are as follows: In this utility model, the second CPU is used to encrypt and decrypt the transmitted data, then the FPGA performs format verification, and finally the encrypted data is forwarded. The whole process realizes data encryption and ensures the security of data transmission in the network. Moreover, this utility model uses miniaturized devices such as 10 Gigabit Ethernet controller and 10 Gigabit optical module, which greatly improves the data transmission rate. At the same time, it also solves the problem that existing communication boards occupy a lot of space and are not portable. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the structure of an encryption / decryption device with communication function according to the present invention. Detailed Implementation

[0015] The present invention will be further described below with reference to the accompanying drawings and embodiments:

[0016] like Figure 1 As shown, an encryption / decryption device with communication capabilities includes a motherboard 1, which is fixedly mounted on a casing made of aluminum alloy for easy installation and passive heat dissipation. The motherboard 1 is a PCIe card, meaning it can be inserted into a server or a personal PC. The motherboard 1 has a communication area and an encryption / decryption area; both areas have a power input interface 2 for receiving 42V / 160W power. The motherboard 1 also includes a gigabit Ethernet port, a serial port, a display interface, and a USB interface (not shown in the diagram) for easy operating system installation and software debugging.

[0017] The communication area is equipped with a first optical module 3, a first 10 Gigabit Ethernet controller 4, a first CPU 5, an FPGA 6, and a second optical module 7, which are connected in sequence. The first CPU 5 is connected to the first solid-state drive 8 and the first DDR4 memory 9. The first CPU 5 is an i9-13950HX CPU. The first solid-state drive 8 is 512GB and the first DDR4 memory 9 is 16GB.

[0018] The encryption / decryption zone contains a third optical module 10, a second 10 Gigabit Ethernet controller 11, and a second CPU 12, all electrically connected in sequence. The second CPU 12 is an i9-13950HX model CPU. The second CPU 12 is connected to a second solid-state drive 13 and a second DDR4 memory 14. The second solid-state drive 13 is 4TB, and the second DDR4 memory 14 is 32GB. The second optical module 7 is connected to the third optical module 10 via optical fiber. Specifically, the first optical module 3, the second optical module 7, and the third optical module 10 are all 10 Gigabit optical modules, model E25GSFP28SR; the first 10 Gigabit Ethernet controller 4 and the second 10 Gigabit Ethernet controller 11 are Intel 82599ES models; and the FPGA 6 is model XC7K325T-2FFG676C.

[0019] The first CPU 5 and the second CPU 12 are the core components of the communication area and encryption / decryption area, respectively, used to process network data streams and perform encryption / decryption functions, including data forwarding, etc. Both the first CPU 5 and the second CPU 12 require solid-state drives and DDR4 memory to form a small system and meet basic operating conditions; these are existing technologies. The FPGA 6 is used to verify the data format. The main function of the first 10 Gigabit Ethernet controller 4 and the second 10 Gigabit Ethernet controller 11 is to realize communication between the computer and the Ethernet network. This invention uses miniaturized devices such as 10 Gigabit Ethernet controllers and 10 Gigabit optical modules, greatly improving the data transmission rate. Moreover, the device has no size limitations; a compact design can solve the problem of existing communication boards occupying large spaces and being inconvenient to carry.

[0020] The principle behind the entire process is as follows:

[0021] Business data is transmitted via optical fiber to the first optical module 3, and then sent to the FPGA 6 via the first 10 Gigabit Ethernet controller 4 and the first CPU 5. The FPGA 6 verifies the data format and forwards the verified data to the second optical module 7. The second optical module 7 transmits the data via optical fiber to the third optical module 10. The third optical module 10 transmits the data via the second 10 Gigabit Ethernet controller 11 to the second CPU 12. The second CPU 12 performs data encryption and decryption to obtain encrypted ciphertext. The ciphertext is then transmitted via the second 10 Gigabit Ethernet controller 11 to the third optical module 10. The third optical module 10 transmits the ciphertext via optical fiber to the second optical module 7. The second optical module 7 then sends the ciphertext to the FPGA 6 for ciphertext format verification. After verification, it is sent to the first CPU 5. The first CPU 5 then forwards the data via the first 10 Gigabit Ethernet controller 4 to the first optical module 3. The first optical module 3 then transmits the ciphertext out via optical fiber.

[0022] In this invention, the second CPU 12 is used to encrypt and decrypt the transmitted data, then the FPGA 6 performs format verification, and finally forwards the encrypted data. The whole process realizes data encryption and ensures the security of data transmission in the network.

Claims

1. An encryption / decryption device with communication function, characterized in that: The system includes a motherboard, which has a communication area and an encryption / decryption area. The communication area contains a first optical module, a first 10 Gigabit Ethernet controller, a first CPU, an FPGA, and a second optical module that are electrically connected in sequence. The encryption / decryption area contains a third optical module, a second 10 Gigabit Ethernet controller, and a second CPU that are electrically connected in sequence. The second optical module and the third optical module are connected via optical fiber.

2. The encryption / decryption device with communication function according to claim 1, characterized in that: Both the first CPU and the second CPU are i9-13950HX CPUs.

3. The encryption / decryption device with communication function according to claim 2, characterized in that: The first CPU is connected to the first solid-state drive and the first DDR4 memory; the second CPU is connected to the second solid-state drive and the second DDR4 memory.

4. The encryption / decryption device with communication function according to claim 1, characterized in that: Both the communication area and the encryption / decryption area are equipped with a power input interface, which is used to input 42V / 160W power.

5. The encryption / decryption device with communication function according to claim 1, characterized in that: The first, second, and third optical modules are all 10 Gigabit optical modules, and the model of the 10 Gigabit optical module is E25GSFP28SR.

6. The encryption / decryption device with communication function according to claim 2, characterized in that: The first 10 Gigabit Ethernet controller and the second 10 Gigabit Ethernet controller are both Intel 82599ES; the FPGA is an XC7K325T-2FFG676C.

7. The encryption / decryption device with communication function according to claim 1, characterized in that: The motherboard is fixedly mounted on the outer casing, which is an aluminum alloy casing.

8. The encryption / decryption device with communication function according to claim 1, characterized in that: The motherboard is also equipped with a gigabit debugging network port, a debugging serial port, a display interface, and a USB interface.

Images