Ethernet dynamic bandwidth physically isolated communication devices
By achieving physical isolation through photoelectric conversion chips and combining it with multi-clock circuit design, the security and stability issues of existing communication equipment in the face of advanced threats are solved, resulting in a highly secure and stable communication device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHENOU COMM EQUIP
- Filing Date
- 2025-07-17
- Publication Date
- 2026-05-26
AI Technical Summary
When facing advanced persistent threats, existing communication equipment is at risk of having its logical isolation methods breached, making it impossible to prevent data leakage and illegal intrusion at the physical level. This makes it difficult to meet the extremely high security requirements of industries such as finance, power, and government.
Physical isolation is achieved by using photoelectric conversion chips, and combined with a multi-clock circuit design, including the first to fourth clock circuits, to provide independent clock signals for different modules, ensuring stable operation of the equipment.
It achieves the physical elimination of data leakage and illegal intrusion, improves the security and stability of network communication, meets the needs of high-security industries, and solves the shortcomings of traditional equipment in terms of security and stability.
Smart Images
Figure CN224289810U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a communication device, and more specifically to a communication device with Ethernet dynamic bandwidth physical isolation. Background Technology
[0002] With the rapid development of information technology, communication equipment is increasingly widely used in various fields, making network security and data transmission stability critical issues. In existing communication equipment, data interaction is mostly based on traditional network architectures. While there are some isolation measures between different network areas, these are primarily logical isolation methods, such as firewalls and access control lists. This logical isolation technology is vulnerable to breaches by advanced persistent threats (APTs) and malware attacks, failing to physically prevent data leaks and unauthorized intrusions, and thus failing to meet the extremely high security requirements of industries such as finance, power, and government. Utility Model Content
[0003] In view of the shortcomings of the existing technology, the purpose of this utility model is to provide a communication device that can effectively achieve physical isolation of Ethernet dynamic bandwidth physical isolation.
[0004] To achieve the above objectives, this utility model provides the following technical solution: a communication device with dynamic bandwidth physical isolation for Ethernet, comprising a main control circuit and a communication circuit, wherein the main control circuit is connected to the communication circuit to communicate with an external network through the communication circuit. The communication circuit is also connected to an isolation circuit, through which it communicates with the external network; the isolation circuit includes:
[0005] The photoelectric conversion chip M1 has an optical signal input pin and an electrical signal output pin. The optical signal input pin is connected to an external optical fiber network to receive optical signals, and the electrical signal output pin is connected to a communication circuit to output electrical signals.
[0006] As a further improvement of this utility model, the communication device also includes:
[0007] The first clock circuit is used to provide the clock required for the operation of the communication equipment.
[0008] The second clock circuit is used to provide the clock required for the operation of the communication equipment.
[0009] The third clock circuit is connected to the 10G optical path to provide the clock required for the 10G optical path to operate.
[0010] The fourth clock circuit, connected to the isolation circuit, provides the clock required for the operation of the photoelectric conversion chip M1.
[0011] As a further improvement of this utility model, the first clock circuit includes:
[0012] Clock chip X1 has an enable pin, a non-inverting input pin, an inverting input pin, and an output pin. The enable pin is connected to a power supply via a resistor R1. The non-inverting input pin is connected to the inverting input pin via a capacitor C1. The node between the non-inverting input pin and the capacitor C1 is connected to a power supply. The node between the inverting input pin and the capacitor C1 is grounded. The output pin is connected to a filter circuit to output a clock signal.
[0013] As a further improvement of this utility model, the filter circuit includes:
[0014] Resistors R66 and R70 are connected in series between the power supply and ground. The node between resistors R66 and R70 is connected to capacitor C4 and then connected to the output pin of clock chip X1. The node between resistors R66 and R70 is also used to output clock signals.
[0015] As a further improvement of this utility model, the third clock circuit includes:
[0016] The clock chip X4 has an enable pin, a non-inverting input pin, an inverting input pin, and an output pin. The enable pin is connected to a power supply via a resistor R4. The non-inverting input pin is connected to the inverting input pin via a capacitor C7. The node between the non-inverting input pin and the capacitor C7 is connected to the power supply. The node between the inverting input pin and the capacitor C7 is grounded. The output pin is connected to a capacitor C130 to output a clock signal.
[0017] The beneficial effects of this utility model are:
[0018] This invention, by setting up an isolation circuit and using a photoelectric conversion chip to achieve physical isolation, fundamentally eliminates the possibility of data leakage and illegal intrusion, greatly improving the security of network communication and better meeting the stringent network security requirements of industries such as finance, power, and government. Furthermore, this invention also incorporates multiple clock circuits to provide the necessary clocks for different parts of the communication equipment, ensuring stable operation of all components, improving data transmission stability, and addressing the shortcomings of traditional communication equipment in terms of security and stability. Attached Figure Description
[0019] Figure 1 This is a schematic diagram of the circuit setup for the Ethernet dynamic bandwidth physically isolated communication device of this utility model.
[0020] Figure 2 for Figure 1 Circuit diagram of the intermediate isolation circuit;
[0021] Figure 3 for Figure 1 Circuit diagrams of the first to fourth clock circuits. Detailed Implementation
[0022] The present invention will now be described in further detail with reference to the embodiments shown in the accompanying drawings.
[0023] Reference Figures 1 to 2 As shown, the Ethernet dynamic bandwidth physically isolated communication device of this embodiment includes a main control circuit 1 and a communication circuit 2. The main control circuit 1 is connected to the communication circuit 2, and the communication circuit 2 is also connected to an isolation circuit 3, which communicates with an external fiber optic network. The isolation circuit 3 includes a photoelectric conversion chip M1, whose optical signal input pin is connected to the external fiber optic network and its electrical signal output pin is connected to the communication circuit 2, realizing the conversion between optical and electrical signals. This structure achieves physical-level signal isolation through the photoelectric conversion chip M1, avoiding the risk of traditional logical isolation being breached, effectively improving the security of data transmission, and solving the problem of data leakage risk in the face of advanced threats in the background technology.
[0024] Furthermore, the device also includes a first clock circuit, a second clock circuit, a third clock circuit, and a fourth clock circuit. The first and second clock circuits provide the operating clock for the device, the third clock circuit is connected to the 10G optical path, and the fourth clock circuit provides the operating clock for the photoelectric conversion chip M1 of the isolation circuit 3. This multi-clock circuit design ensures stable operation of different modules under independent clock control, avoids clock signal interference, improves the stability and reliability of the device in high-speed data transmission, and solves the problem of unstable data transmission caused by clock synchronization issues in traditional devices in the background art.
[0025] Furthermore, refer to Figure 3 As shown, the first clock circuit includes a clock chip X1, whose enable pin is connected to the power supply through a resistor R1. A capacitor C1 is connected between the non-inverting input pin and the inverting input pin. The output pin outputs a clock signal through a filter circuit. The filter circuit consists of resistors R66 and R70 connected in series. The node between the two resistors is connected to the output pin of the clock chip X1 through a capacitor C4, and outputs the clock signal. This circuit effectively suppresses high-frequency noise in the clock signal through the combination of resistors and capacitors, ensuring the stability and accuracy of the output clock, providing a reliable clock reference for the core module of the device, and solving the data transmission error problem caused by unstable clock signals in the background technology.
[0026] Furthermore, refer to Figure 3As shown, the third clock circuit includes a clock chip X4, whose enable pin is connected to the power supply through resistor R4. A capacitor C7 is connected between the non-inverting input pin and the inverting input pin, and the output pin directly outputs the clock signal to the 10G optical path. This clock circuit is designed for 10G high-speed optical paths, providing a high-frequency, low-jitter clock signal to meet the stringent clock accuracy requirements of 10G networks. It ensures the synchronization and integrity of signals during high-speed data transmission, solving the data transmission delay and packet loss problems caused by the difficulty of clock synchronization in high-speed networks in the background technology.
[0027] In summary, this solution achieves physical layer data isolation through the photoelectric conversion chip M1 in isolation circuit 3, and, in conjunction with the independent and precise control of multiple clock circuits, constructs a communication device that combines high security and stability. 1) The physical isolation design eliminates the risk of data leakage at the hardware level, meeting the high-security requirements of industries such as finance and government; 2) The multiple clock circuits provide precise clocks for different modules, solving the clock synchronization problem in high-speed data transmission; 3) The filtering circuit optimizes clock signal quality, improving the device's anti-interference capability in complex network environments. This device effectively overcomes the security bottleneck of traditional logical isolation, achieving physically isolated communication under dynamic bandwidth, and possesses significant advantages such as high security, stable transmission, and strong anti-interference capability.
[0028] The above description is merely a preferred embodiment of this utility model. The protection scope of this utility model is not limited to the above embodiments. All technical solutions falling within the scope of this utility model's concept are protected. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principle of this utility model should also be considered within the protection scope of this utility model.
Claims
1. A communication device with Ethernet dynamic bandwidth physical isolation, comprising a main control circuit (1) and a communication circuit (2), wherein the main control circuit (1) is connected to the communication circuit (2) to communicate with an external network through the communication circuit (2), characterized in that: The communication circuit (2) is also connected to an isolation circuit (3), which communicates with an external network. The isolation circuit (3) includes: The photoelectric conversion chip M1 has an optical signal input pin and an electrical signal output pin. The optical signal input pin is connected to an external optical fiber network to receive optical signals, and the electrical signal output pin is connected to a communication circuit (2) to output electrical signals.
2. The communication device of claim 1, wherein: Also includes: The first clock circuit is used to provide the clock required for the operation of the communication equipment. The second clock circuit is used to provide the clock required for the operation of the communication equipment. The third clock circuit is connected to the 10G optical path to provide the clock required for the 10G optical path to operate. The fourth clock circuit is connected to the isolation circuit (3) to provide the clock required for the operation of the photoelectric conversion chip M1.
3. The communication device of claim 2, wherein: The first clock circuit includes: Clock chip X1 has an enable pin, a non-inverting input pin, an inverting input pin, and an output pin. The enable pin is connected to a power supply via a resistor R1. The non-inverting input pin is connected to the inverting input pin via a capacitor C1. The node between the non-inverting input pin and the capacitor C1 is connected to a power supply. The node between the inverting input pin and the capacitor C1 is grounded. The output pin is connected to a filter circuit to output a clock signal.
4. The communication device of claim 3, wherein: The filtering circuit includes: Resistors R66 and R70 are connected in series between the power supply and ground. The node between resistors R66 and R70 is connected to capacitor C4 and then connected to the output pin of clock chip X1. The node between resistors R66 and R70 is also used to output clock signals.
5. The communication device with dynamic bandwidth physical separation of Ethernet according to any one of claims 2 to 4, characterized in that: The third clock circuit includes: The clock chip X4 has an enable pin, a non-inverting input pin, an inverting input pin, and an output pin. The enable pin is connected to a power supply via a resistor R4. The non-inverting input pin is connected to the inverting input pin via a capacitor C7. The node between the non-inverting input pin and the capacitor C7 is connected to the power supply. The node between the inverting input pin and the capacitor C7 is grounded. The output pin is connected to a capacitor C130 to output a clock signal.