Integrated circuit devices

Abstract

Various embodiments of this utility model relate to an integrated circuit device, including: a conductive layer; a dielectric structure disposed above the conductive layer; a first conductive structure disposed within the dielectric structure and spaced apart from the conductive layer; a semiconductor structure disposed within the dielectric structure and extending vertically from the conductive layer to the first conductive structure; a first dielectric member disposed within the dielectric structure and extending vertically along the semiconductor structure from the conductive layer; a conductive member disposed within the dielectric structure, located between the conductive layer and the first conductive structure and spaced apart from both the conductive layer and the first conductive structure, and extending laterally from the first dielectric member; a second conductive structure disposed within the dielectric structure and extending vertically near the surface of the conductive member opposite to the conductive layer; and a second dielectric member disposed within the dielectric structure and at least partially surrounding the second conductive structure.

Description

Technical Field

[0001] This utility model relates to an integrated circuit device. Background Technology

[0002] From its inception, flash memory was a popular innovation in the field of storage technology due to its non-volatility, storage density, ability to be erased in blocks (as opposed to entire integrated circuit (IC) devices), erasability, and the ability to be written to and read at the page or single cell level. Over the years, significant development efforts have focused on enhancing manufacturing processes to improve storage density, operating speed, and device throughput. Utility Model Content

[0003] Some embodiments relate to integrated circuit (IC) devices. An IC device includes: a conductive layer; a dielectric structure disposed above the conductive layer; a first conductive structure disposed within the dielectric structure and spaced apart from the conductive layer; a semiconductor structure disposed within the dielectric structure and extending perpendicularly from the conductive layer to the first conductive structure; a first dielectric member disposed within the dielectric structure and extending perpendicularly from the conductive layer along the semiconductor structure; a conductive member disposed within the dielectric structure, located between and spaced apart from the conductive layer and the first conductive structure, and extending laterally from the first dielectric member; a second conductive structure disposed within the dielectric structure and extending perpendicularly near a surface of the conductive member opposite to the conductive layer; and a second dielectric member disposed within the dielectric structure and at least partially surrounding the second conductive structure to isolate the second conductive structure from the conductive member and the dielectric structure.

[0004] Some embodiments relate to another IC device. The IC device includes: a conductive layer; a dielectric structure disposed above the conductive layer; a first conductive structure disposed within the dielectric structure and spaced apart from the conductive layer; a semiconductor structure disposed within the dielectric structure and extending perpendicularly from the conductive layer to the first conductive structure; a first dielectric member disposed within the dielectric structure and extending perpendicularly from the conductive layer along the semiconductor structure; a plurality of conductive members disposed within the dielectric structure, located between the conductive layer and the first conductive structure and perpendicularly spaced apart from the conductive layer and the first conductive structure, and extending laterally from the first dielectric member; a plurality of second conductive structures disposed within the dielectric structure, each of the plurality of second conductive structures extending perpendicularly from a surface of a corresponding one of the plurality of conductive members relative to one of the conductive layers; and a plurality of second dielectric members disposed within the dielectric structure, each of the plurality of second dielectric members at least partially surrounding a corresponding one of the plurality of second conductive structures to isolate the corresponding one of the plurality of second conductive structures from the corresponding one of the plurality of conductive members and the dielectric structure. Attached Figure Description

[0005] The various aspects of this utility model can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0006] Figure 1 Schematic diagrams of some embodiments of the three-dimensional (3D) inverted flash memory structure according to the present invention are shown.

[0007] Figure 2A Cross-sectional views of some embodiments of an integrated circuit (IC) device including a single-transistor 3D inverted flash memory structure according to the present invention are shown.

[0008] Figure 2B Cross-sectional views of some embodiments of an IC device including a multi-transistor 3D inverted flash memory structure according to the present invention are shown.

[0009] Figures 3A to 3T Cross-sectional views of several embodiments of an IC device including a single-transistor 3D inverted flash memory structure according to the present invention are shown at various manufacturing stages.

[0010] Figures 4A to 4E Cross-sectional views at various manufacturing stages are shown for some embodiments of an IC device including a multi-transistor 3D inverted flash memory structure disclosed herein.

[0011] Figure 5 The formation according to the present invention is shown. Figures 3A to 3T Single-transistor 3D inverted flash memory structure and Figures 4A to 4E Methods of some embodiments of IC devices with multi-transistor 3D inverted flash memory structures. Detailed Implementation

[0012] This invention provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. These are merely examples and are not intended to be limiting. For instance, the following description of forming a first feature on or above a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not, in itself, define the relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one component or feature and another, as shown in the figures. In addition to the orientations depicted in the figures, spatially related terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptions used herein can be interpreted accordingly.

[0014] In a first flash memory integrated circuit (IC) structure that can form a floating-gate metal-oxide-semiconductor field-effect transistor (MOSFET) used as a memory cell, the floating gate is isolated between the control gate and the semiconductor channel region by bulk oxide and tunneling oxide, respectively. In operation, in the presence of a programming voltage, charge can be stored in the floating gate through the channel and tunneling oxide, thereby generating a programming cell with a first threshold voltage. Conversely, in the presence of an erase voltage, such charge can be released from the floating gate through the channel and tunneling oxide, thereby generating an erase cell with a second threshold voltage (e.g., less than the first threshold voltage). Therefore, a read voltage between the first and second threshold voltages can be used to perform a cell read, thereby generating a voltage indicating whether the cell is in a programming or erase state.

[0015] In some other flash memory IC devices, an "inverted" flash memory IC structure can be used, in which the tunneling oxide is located between the floating gate and the control gate, rather than between the floating gate and the channel as described above. A potential advantage of the inverted flash memory structure may be that some parameters, such as the cell's "storage margin" (e.g., the difference between a first threshold voltage and a second threshold voltage), can be adjusted by the dimensions of the control gate, tunneling oxide, etc.

[0016] In some cases, the storage density of flash memory devices can be increased by employing an IC manufacturing process that vertically stacks multiple memory cells of a first flash memory IC structure within a single IC die to form a three-dimensional (3D) flash memory IC structure. However, it has proven difficult to provide the aforementioned parameter adjustment capabilities using a similar 3D memory cell architecture employing an inverted flash memory IC structure.

[0017] To address these issues, this invention provides embodiments of 3D inverted flash memory IC devices that may include laterally extended floating gate structures. Figure 1 Schematic diagrams of some embodiments of a three-dimensional (3D) inverted flash memory structure 100 according to the present invention are shown. Unlike a vertically stacked inverted flash memory structure, in which multiple layers of the structure are stacked vertically on top of each other, the 3D inverted flash memory structure 100 typically includes multiple layers laterally positioned relative to each other. Figure 1 As shown, the 3D inverted flash memory structure 100 may, from right to left, sequentially include a semiconductor structure 110 serving as a transistor channel (TC), a first dielectric member 116 serving as block oxide (BO), a conductive member 106 serving as a floating gate (FG), a second dielectric member 108 serving as tunnel oxide (TO), and a second conductive structure 118 serving as a control gate (CG). In some embodiments, the conductive layer 102 and the conductive structure 104 (e.g., serving as the source and drain of a transistor) may be located at opposite ends of the semiconductor structure 110. Although Figure 1 A source electrode is depicted above the semiconductor structure 110, and a drain electrode is depicted below the semiconductor structure 110, but the positions of the source and drain electrodes may be reversed. A dielectric structure (DS) 103 may surround at least a portion of the inverted flash memory structure 100.

[0018] In some embodiments, as described below, some structures or components of the 3D inverted flash memory structure may be oriented perpendicularly to each other. For example, a control gate structure may extend perpendicularly toward the floating gate structure and may be isolated from the floating gate structure by a tunneling dielectric material layer substantially surrounding the control gate structure. This structure can be used in single-transistor inverted flash memory structures employing a single floating gate and an associated control gate and an associated tunneling dielectric, as well as in multi-transistor inverted flash memory structures comprising two or more floating gate structures, each floating gate structure being associated with a separate control gate and tunneling dielectric.

[0019] When using such a structure, as described in more detail in some embodiments below, a relatively large storage margin can be provided by adjusting the control gate and floating gate of the flash memory structure, the thickness of the tunneling dielectric, and other structural features. Furthermore, this benefit is possible while implementing the vertical stacking of multiple transistors used in 3D flash memory structures.

[0020] Figure 2A Cross-sectional views of some embodiments of an integrated circuit (IC) device 200A including a single-transistor 3D inverted flash memory structure according to the present invention are shown. As shown, the conductive layer 102 may serve as a substrate for the remainder of the inverted flash memory cell structure or as a layer supported by a substrate, as described below. In some embodiments, the conductive layer 102 may operate as a first source-drain structure (e.g., a source) for the single-transistor inverted flash memory structure.

[0021] A dielectric structure 103 may be disposed above the conductive layer 102, with the remaining components of the inverted flash memory structure located within the dielectric structure 103. More specifically, a first conductive structure 104 (e.g., a second source-drain region, such as a drain) may be disposed above the conductive layer 102. A semiconductor structure 110 extending substantially vertically from the conductive layer 102 to the first conductive structure 104 may couple the conductive layer 102 and the first conductive structure 104. Furthermore, in some embodiments, the semiconductor structure 110 may extend laterally along the lower surface of the first conductive structure 104. In some embodiments, the semiconductor structure 110 may serve as a transistor channel between the source (e.g., the conductive layer 102) and drain (e.g., the first conductive structure 104) of a transistor.

[0022] In some embodiments, within the dielectric structure 103, the first dielectric member 116 may extend vertically from the conductive layer 102 along a vertically extending portion of the semiconductor structure 110 to a laterally extending portion of the semiconductor structure 110. Therefore, in some embodiments, the semiconductor structure 110 may isolate the first dielectric member 116 from the first conductive structure 104. In some embodiments, the first dielectric member 116 may be used as a bulk dielectric (e.g., bulk oxide) in a flash memory transistor structure.

[0023] Furthermore, in some embodiments, the conductive member 106 disposed within the dielectric structure 103 may extend laterally from the first dielectric member 116 and may serve as a floating gate of a flash memory transistor structure. Therefore, in some embodiments, the first dielectric member 116 (e.g., bulk oxide) may isolate the conductive member 106 (e.g., floating gate) from the semiconductor structure 110 (e.g., transistor channel) at a first end of the conductive member 106.

[0024] In some embodiments, near the second end of the conductive member 106, a second dielectric member 108 may be disposed within the dielectric structure 103 and substantially surround the vertically extending second conductive structure 118, thereby isolating the second conductive structure 118 from the conductive member 106. In some embodiments, the second dielectric member 108 may serve as a tunneling dielectric (e.g., tunneling oxide), while the second conductive structure 118 may serve as a control gate of a flash memory transistor structure. Furthermore, in some embodiments, the second conductive structure 118 may not use a separate contact structure to connect to other electronic circuitry (e.g., for reading, programming, and / or erasing flash memory cells).

[0025] In some embodiments, also as Figure 2A As shown, a first conductive contact structure 112 is disposed within the dielectric structure 103 and extends vertically from the conductive layer 102, and a second conductive contact structure 114 extends vertically from the first conductive structure 104. Therefore, in some embodiments, the first conductive contact structure 112 and the second conductive contact structure 114 may provide electrical connectivity between the source and drain of the flash memory transistor and other circuitry (e.g., control circuitry for programming, erasing, and / or reading the flash memory structure).

[0026] In some embodiments, given the structure of the IC device 200A, relative to the operation of the flash memory, adjustments to various structural aspects (e.g., the thickness of the second dielectric member 108, the surface area of ​​the second dielectric member 108 in contact with the conductive member 106, the width of the second conductive structure 118, etc.) can affect the size of the storage margin and other parameters of interest (e.g., the speed of programming, erasing and reading operations, the amount of charge stored in the floating gate during programming, the amount of time the stored charge remains in the floating gate, etc.).

[0027] Figure 2B Cross-sectional views of some embodiments of an IC device 200B including a multi-transistor 3D inverted flash memory structure according to the present invention are shown. In some embodiments, in Figure 2B The above combination is depicted in IC device 200B. Figure 2AThe IC device 200A discusses several identical components (e.g., conductive layer 102, dielectric structure 103, first conductive structure 104, semiconductor structure 110, first dielectric member 116, first conductive contact structure 112, and second conductive contact structure 114). However, instead of... Figure 2A The depicted single conductive member 106, single second dielectric member 108, and single second conductive structure 118, Figure 2B This includes multiple sets (e.g., three sets) of such components.

[0028] More specifically, each of the three conductive members 106A, 106B, and 106C extends laterally from the same single first dielectric member 116 at its first end and is isolated from the conductive layer 102, the first conductive structure 104, and each other. Furthermore, in some embodiments, each of the three conductive members 106A, 106B, and 106C contacts a corresponding second dielectric member 108A, 108B, and 108C near its second end opposite the first end. Additionally, in some embodiments, each second dielectric member 108A, 108B, and 108C substantially surrounds a corresponding second conductive structure 118A, 118B, and 118C. Furthermore, each group of components (e.g., a first group including conductive component 106A, second dielectric component 108A, and second conductive structure 118A; a second group including conductive component 106B, second dielectric component 108B, and second conductive structure 118B; and a third group including conductive component 106C, second dielectric component 108C, and second conductive structure 118C) is isolated from each other within dielectric structure 103. Therefore, in some embodiments, each group of components may constitute a separate transistor in the flash memory structure, wherein the separate transistor also includes a shared barrier dielectric (e.g., first dielectric component 116), channel (e.g., semiconductor structure 110), source (e.g., conductive layer 102), and drain (e.g., first conductive structure 104). Such a structure can be useful when a memory cell represented by three transistors is configured to be programmed, erased, and / or read at different times.

[0029] In some embodiments, the lateral lengths of conductive members 106A, 106B, and 106C can vary, such that each successive conductive member can be laterally shorter than the preceding conductive member from its lowest to its highest position. Therefore, in Figure 2BIn this configuration, conductive member 106A may be the longest, conductive member 106C may be the shortest, and conductive member 106B may have an intermediate lateral length. In some embodiments, arranging conductive members 106A, 106B, and 106C in this manner facilitates access to each conductive member 106A, 106B, and 106C from above. Therefore, the correspondence between dielectric members and conductive structures (e.g., second dielectric member 108A and second conductive structure 118A; conductive member 106B and second dielectric member 108B and second conductive structure 118B; second dielectric member 108C and second conductive structure 118C) may also be arranged from deepest to shallowest depth from left to right to be compatible with the depth of conductive members 106A, 106B, and 106C within the IC device 200B.

[0030] Although Figure 2B The diagram shows three sets of components representing three transistors, but other embodiments may include two or more such sets of components to establish a corresponding number of transistors using a single source and drain configuration.

[0031] Figures 3A to 3T It shows Figure 2A A cross-sectional view of the IC device 200A according to some embodiments of the present invention, which includes multiple manufacturing stages of a single-transistor 3D inverted flash memory structure. Although Figures 3A to 3T The actions are described as a series of actions, but it should be understood that these actions are not limiting, as the order of actions within each series may be changed in other embodiments, and the disclosed methods are also applicable to other structures. In other embodiments, some actions shown and / or described may be omitted, in whole or in part.

[0032] For example, Figure 3A A conductive layer 102 is shown, which can serve as a substrate for the remaining structural components of the IC device 200A or as a layer disposed above a substrate. In some embodiments, the conductive layer 102 may include one or more of titanium nitride (TiN), titanium (Ti), tungsten (W), molybdenum (Mo), niobium (Nb), tantalum nitride (TaN), ruthenium (Ru), aluminum (Al), titanium aluminide (TiAl), palladium (Pd), platinum (Pt), nickel (Ni), and polysilicon (poly-Si), or other metals or alloys. Furthermore, in some embodiments, the thickness D1 of the conductive layer 102 may range from 1 nanometer to 20 nanometers.

[0033] Figure 3B The formation (e.g., deposition) of the dielectric material ultimately contained in the dielectric structure 103 on the conductive layer 102 is illustrated. In some embodiments, the dielectric material may include silicon oxide (SiO2). xThe dielectric material can be, for example, silicon dioxide (SiO2), or another oxide or dielectric material. Furthermore, in some embodiments, the thickness D2 of this portion of the dielectric structure 103 can range from 1 nanometer to 10 nanometers.

[0034] Figure 3C A conductive layer is shown formed (e.g., deposited) on a first dielectric material of dielectric structure 103, which ultimately becomes conductive member 106. In some embodiments, this conductive layer may include one or more of titanium nitride (TiN), titanium (Ti), tungsten (W), molybdenum (Mo), niobium (Nb), tantalum nitride (TaN), ruthenium (Ru), aluminum (Al), titanium aluminide (TiAl), palladium (Pd), platinum (Pt), nickel (Ni), polycrystalline silicon (poly-Si), or other metals or alloys. Furthermore, in some embodiments, the thickness D3 of this conductive layer may be in the range of 1 nanometer to 20 nanometers.

[0035] Figure 3D The removal (e.g., photolithography and associated etching 302) of conductive member 106 and dielectric structure 103 is shown to expose a portion of conductive layer 102. In some embodiments, such removal results in the definition of a second end of conductive member 106, as described above.

[0036] Figure 3E An additional dielectric material 304 is shown formed (e.g., deposited) onto the dielectric structure 103. In some embodiments, such a dielectric material 304 may be referenced above. Figure 3B The same as mentioned (e.g., silicon dioxide (SiO2) x (e.g., silicon dioxide (SiO2), or another oxide or dielectric material). In some embodiments, the thickness D4 of the additional dielectric material 304 may be in the range of 1 nanometer to 10 nanometers.

[0037] Figure 3F The removal (e.g., photolithography and associated etching 306) of dielectric structure 103 and conductive member 106 is shown to expose another portion of conductive layer 102. In some embodiments, as discussed below, this removal can provide a surface on which the first dielectric member 116 and semiconductor structure 110 are formed. Moreover, in some embodiments, the removal can define a first end of conductive member 106 opposite to a second end of conductive member 106, and thus configure the lateral extent of conductive member 106.

[0038] For example, Figure 3GThe diagram shows the formation (e.g., conformal deposition) of a first dielectric layer, which ultimately forms a first dielectric member 116. In some embodiments, such formation may result in a dielectric material covering the dielectric structure 103, the first end of the conductive member 106, and the exposed portion of the conductive layer 102. Additionally, in some embodiments, the first dielectric member 116 (e.g., operating as a bulk oxide) may include silicon nitride (SiN), silicon dioxide (SiO2), hafnium oxide (HfO2), zirconium dioxide (ZrO2), hafnium zirconium oxide (HfZrO), aluminum oxide (Al2O3), titanium oxide (TiO2), magnesium oxide (MgO), lanthanum oxide (La2O3), and niobium oxide (NbO). x) Alternatively, a multilayer of the aforementioned materials (e.g., HfO2 / Al2O3). Furthermore, in some embodiments, the thickness D5 of the first dielectric member 116 may range from 5 nanometers to 20 nanometers.

[0039] Figure 3H The diagram illustrates the removal (e.g., etching 308, such as blanket etching or “spacer-like” etching 308) of a lateral portion of the first dielectric layer to form the first dielectric member 116. In some embodiments, this removal results in a vertically oriented portion of the first dielectric layer remaining along one side of the dielectric structure 103 and the first end of the conductive member 106 to provide the first dielectric member 116.

[0040] Figure 3I A semiconductor layer is shown formed (e.g., conformally deposited), ultimately forming a semiconductor structure 110. In some embodiments, the semiconductor layer may cover exposed portions of the dielectric structure 103, the first dielectric member 116, and the conductive layer 102. In some embodiments, the semiconductor layer may include silicon (Si), germanium (Ge), silicon-germanium (SiGe), indium gallium zinc oxide (IGZO), or indium oxide (InO). x Indium zinc oxide (IZO), indium tin oxide (ITO), tin oxide (SnO) x ( ), nickel oxide (NiO), copper oxide (Cu2O), or combinations thereof. Furthermore, in some embodiments, the semiconductor layer thickness D6 can range from 1 nanometer to 20 nanometers.

[0041] Figure 3J A section is shown where a lateral portion of the semiconductor layer has been removed (e.g., photolithography and associated etching 310) to form the semiconductor structure 110. In some embodiments, the semiconductor structure 110 includes a portion extending vertically from the conductive layer 102 and extending alongside and above the first dielectric member 116. Furthermore, in some embodiments, the semiconductor structure 110 may also extend laterally over a portion of the dielectric structure 103.

[0042] Figure 3KThe formation (e.g., deposition 312) of additional dielectric material to dielectric structure 103 is illustrated. As described above, such additional dielectric material may include silicon oxide (SiO2). x The dielectric material may be silicon dioxide (SiO2), or another oxide or dielectric material. In some embodiments, the upper surface of the dielectric structure 103 substantially matches the upper surface of the semiconductor structure 110. Furthermore, in some embodiments, the upper surfaces of the dielectric structure 103 and the semiconductor structure 110 may also be planarized (e.g., using chemical mechanical planarization (CMP)).

[0043] Figure 3L The diagram illustrates the formation (e.g., deposition) of a conductive layer on a dielectric structure 103 and a semiconductor structure 110 to create a first conductive structure 104. In some embodiments, the first conductive structure 104 may comprise one or more of titanium nitride (TiN), titanium (Ti), tungsten (W), molybdenum (Mo), niobium (Nb), tantalum nitride (TaN), ruthenium (Ru), aluminum (Al), titanium aluminide (TiAl), palladium (Pd), platinum (Pt), nickel (Ni), polycrystalline silicon (poly-Si), or other metals or alloys. Furthermore, in some embodiments, the thickness D7 of this conductive layer may range from 1 nanometer to 20 nanometers.

[0044] Figure 3M The removal (e.g., photolithography and associated etching 314) is shown. Figure 3L One or more portions of the conductive layer formed in the semiconductor structure 110 are used to create a first conductive structure 104. In some embodiments, the first conductive structure 104 may extend laterally beyond either end of the upper surface of the semiconductor structure 110.

[0045] Figure 3N An example is shown of forming (e.g., deposition 316) additional dielectric material to dielectric structure 103. In some embodiments, this additional dielectric material may be the same as the lower portion of dielectric structure 103 and may include silicon oxide (SiO2). x ), such as silicon dioxide (SiO2), or another oxide or dielectric material.

[0046] Figure 3O A trench 318 formed (e.g., photolithography and associated etching) within the dielectric structure 103 is shown, which may extend to the conductive member 106.

[0047] Figure 3PA second dielectric layer is shown formed (e.g., conformally deposited), which ultimately becomes the second dielectric member 108. In some embodiments, the second dielectric layer covers the upper surface of the dielectric structure 103 and the sidewalls and bottom of the trench 318. Furthermore, in some embodiments, the second dielectric layer (e.g., operating as a tunneling oxide) may include silicon nitride (SiN), silicon dioxide (SiO2), hafnium oxide (HfO2), zirconium dioxide (ZrO2), hafnium zirconium oxide (HfZrO), aluminum oxide (Al2O3), titanium oxide (TiO2), magnesium oxide (MgO), lanthanum oxide (La2O3), and niobium oxide (NbO). x Alternatively, the material can be a multilayer selected from the above materials (e.g., HfO2 / Al2O3). Furthermore, in some embodiments, the thickness D8 of the first dielectric member 116 can be in the range of 5 nanometers to 10 nanometers.

[0048] Figure 3Q The diagram illustrates the formation (e.g., filling) of a conductive material in trench 318 to form a second conductive structure 118. As described above, the conductive material may include one or more of titanium nitride (TiN), titanium (Ti), tungsten (W), molybdenum (Mo), niobium (Nb), tantalum nitride (TaN), ruthenium (Ru), aluminum (Al), titanium aluminide (TiAl), palladium (Pd), platinum (Pt), nickel (Ni), polycrystalline silicon (poly-Si), or other metals or alloys.

[0049] Figure 3R The planarization (e.g., blanket etching 320 and / or planarization) of the upper surface of the second dielectric layer and conductive material is shown to form a second conductive structure 118 and a second dielectric member 108 in a trench 318, the second dielectric member 108 surrounding the second conductive structure 118.

[0050] Figure 3S The diagram shows a first contact trench 322 formed within a dielectric structure 103 and extending to a conductive layer 102, and a second contact trench 324 formed within a dielectric structure 103 and extending to a first conductive structure 104.

[0051] Figure 3TThe diagram illustrates forming (e.g., filling) conductive material into a first contact trench 322 and a second contact trench 324 to form a first conductive contact structure 112 and a second conductive contact structure 114, respectively, thereby producing an IC device 200A. Similar to the conductive structures described above, the first conductive contact structure 112 and the second conductive contact structure 114 may include one or more of titanium nitride (TiN), titanium (Ti), tungsten (W), molybdenum (Mo), niobium (Nb), tantalum nitride (TaN), ruthenium (Ru), aluminum (Al), titanium aluminide (TiAl), palladium (Pd), platinum (Pt), nickel (Ni), and polysilicon (poly-Si), or other metals or alloys. Additionally, the resulting upper surface of the IC device 200A may be planarized (e.g., using CMP) (e.g., it is intended to fabricate other circuitry thereon, such as other flash memory structures, programming and / or erasing control circuitry, read circuitry, etc.).

[0052] Although Figures 3A to 3T It shows Figure 2A The IC device 200A includes multiple manufacturing stages for a single-transistor 3D inverted flash memory structure, but in some embodiments, at least some of these stages are applicable to multi-transistor 3D inverted flash memory structures. Figure 2B The manufacture of IC device 200B. For this purpose, Figures 4A to 4E Cross-sectional views of several embodiments of an IC device 200B including a multi-transistor 3D inverted flash memory structure according to the present invention are shown at various early manufacturing stages.

[0053] For example, Figure 4A This illustrates the formation (e.g., deposition) of multiple conductive layers and dielectric material on conductive layer 102, to... Figures 3A to 3C In a similar manner to a single transistor, a base is provided for multiple (e.g., three) conductive components 106A, 106B, and 106C. More specifically, in some embodiments, a first dielectric material, a first conductive material, a second dielectric material, a second conductive material, a third dielectric material, and a third conductive material may be sequentially deposited on conductive layer 102 to ultimately form conductive components 106A, 106B, and 106B. As described above, the first, second, and third dielectric materials may include silicon oxide (SiO2). x For example, silicon dioxide (SiO2), or another oxide or dielectric material. Additionally, the first, second, and third conductive materials may include one or more of titanium nitride (TiN), titanium (Ti), tungsten (W), molybdenum (Mo), niobium (Nb), tantalum nitride (TaN), ruthenium (Ru), aluminum (Al), titanium aluminide (TiAl), palladium (Pd), platinum (Pt), nickel (Ni), polycrystalline silicon (poly-Si), or other metals or alloys. In some embodiments, the thickness of the conductive layer 102 may be in conjunction with the above. Figure 3AThe thickness D1 discussed is the same. Furthermore, in some embodiments, the thickness between the conductive layer 102 and the conductive member 106A, or the dielectric structure 103, may be similar to thickness D2, as described above. Figure 3B As described. Furthermore, in some embodiments, the thickness of each of the conductive members 106A, 106B, and 106C may be similar. Figure 3C The thickness D3 of the conductive component 106.

[0054] Figure 4B Displayed corresponding to Figure 3D The removal of dielectric structure 103 and conductive members 106A, 106B, and 106C during the manufacturing stages (e.g., photolithography and associated etching) (e.g., in a staged, step-like, or ladder-like manner). More specifically, in some embodiments, a first etching 402 may remove a portion of the third conductive member 106C and the underlying dielectric material, extending downward to the second conductive member 106B. A second etching 404 may remove a small portion of the second conductive member 106B and the underlying dielectric material, extending downward to the first conductive member 106A. Subsequently, a third etching 406 may remove a smaller portion of the first conductive member 106A and the underlying dielectric material, extending downward to the conductive layer 102. In some embodiments, such etching may define a second end of each of the conductive members 106A, 106B, and 106C. For example, as the conductive layer 102 moves upward, the lateral extent or length of each of the advancing conductive members 106A, 106B, and 106C can become smaller (e.g., to place the second conductive structures 118A, 118B, and 118C and the associated second dielectric members 108A, 108B, and 108C in a vertical path that allows upward movement through the dielectric structure 103).

[0055] Figure 4C It shows the corresponding Figure 3E The additional dielectric material is formed (e.g., fill 408) to the dielectric structure 103 in a manner described in the stages. In some embodiments, the thickness of the additional dielectric material may be similar. Figure 3E The thickness D4 is shown.

[0056] Figure 4D It shows the corresponding Figure 3F The dielectric structure 103 and conductive members 106A, 106B, and 106C are removed (etched 410) to expose a portion of the conductive layer 102. Furthermore, in some embodiments, such etching may define a first end of the conductive members 106A, 106B, and 106C.

[0057] Figure 4EA first dielectric layer is shown to be formed (e.g., conformally deposited) over the first ends of dielectric structure 103, conductive members 106A, 106B, and 106C, and the exposed portion of conductive layer 102, to interact with... Figure 3G The corresponding method ultimately forms the first dielectric component 116. In some embodiments, the thickness of the first dielectric layer can be similar. Figure 3G The thickness D5 is depicted.

[0058] After that, Figure 2B IC device 200B Figure 4E The subsequent additional manufacturing stages can substantially follow the same principles as... Figure 2A The manufacturing of IC device 200A is related to Figures 3H to 3T The process, materials, dimensions, etc. More specifically, Figure 3H to 3T Each operation of the associated conductive member 106, second dielectric member 108, and second conductive structure 118 of IC device 200A can be applied in a corresponding manner to the conductive members 106A, 106B, and 106C, second dielectric members 108A, 108B, and 108C, and second conductive structures 118A, 118B, and 118C of IC device 200B.

[0059] Figure 5 The formation according to the present invention is shown. Figures 3A to 3T The 200A is an IC device with a single-transistor 3D inverted flash memory structure. Figures 4A to 4E Methods 500 of some embodiments of the IC device 200B with a multi-transistor 3D inverted flash memory structure. Although the methods and other methods shown and / or described herein are illustrated as a series of actions or events, it should be understood that the invention is not limited to the illustrated order or actions. Therefore, in some embodiments, these actions may be performed in a different order than shown, and / or may be performed simultaneously. Furthermore, in some embodiments, the illustrated actions or events may be subdivided into multiple actions or events that may be performed at separate times or simultaneously with other actions or sub-actions. In some embodiments, some illustrated actions or events may be omitted, and other actions or events not shown may be included.

[0060] At action 502, for example, a dielectric structure (e.g., dielectric structure 103) is provided above a conductive layer (e.g., conductive layer 102), wherein one or more conductive members (e.g., conductive member 106 or conductive members 106A, 106B and 106C) are located within the dielectric structure, and the one or more conductive members extend laterally and are isolated from each other and from the conductive layer. Figures 3A to 3E and Figures 4A to 4C Cross-sectional views corresponding to some embodiments of action 502 are shown.

[0061] In action 504, the dielectric structure and one or more conductive members are etched to expose a portion of the conductive layer and the first end of each of the one or more conductive members. Figure 3F and Figure 4D Cross-sectional views corresponding to some embodiments of action 504 are shown.

[0062] In action 506, a first dielectric layer (e.g., associated with the first dielectric member 116) is conformally formed on a first end of each of the dielectric structure, one or more conductive members, and a portion of the conductive layer. Figure 3G and Figure 4E Cross-sectional views corresponding to some embodiments of action 506 are shown.

[0063] In action 508, the lateral portion of the first dielectric layer is etched to form a first dielectric member (e.g., first dielectric member 116) extending vertically from the conductive layer. Figure 3H Cross-sectional views corresponding to some embodiments of action 508 are shown.

[0064] In action 510, a semiconductor layer (e.g., associated with semiconductor structure 110) is conformally formed on portions of the dielectric structure, the first dielectric member, and the conductive layer. Figure 3I Cross-sectional views corresponding to some embodiments of action 510 are shown.

[0065] In action 512, the semiconductor layer is etched to form a semiconductor structure (e.g., semiconductor structure 110) that extends vertically from the conductive layer and extends alongside and above the first dielectric member. Figure 3J Cross-sectional views corresponding to some embodiments of action 512 are shown.

[0066] In action 514, a first conductive structure (e.g., first conductive structure 104) is formed on the dielectric structure and the semiconductor structure. Figure 3K and Figure 3L Cross-sectional views corresponding to some embodiments of action 514 are shown.

[0067] In action 516, one or more trenches (e.g., trench 318) are formed within the dielectric structure, each of the one or more trenches extending to a corresponding one of the one or more conductive members. Figure 3O Cross-sectional views corresponding to some embodiments of action 516 are shown.

[0068] At action 518, a second dielectric layer (e.g., associated with the second dielectric member 108) is conformally formed over the dielectric structure, and the second dielectric layer extends to the bottom of one or more trenches. Figure 3P Cross-sectional views corresponding to some embodiments of action 518 are shown.

[0069] In action 520, a conductive material (e.g., associated with the second conductive structure 118) is formed on the second dielectric layer in each of one or more trenches. Figure 3Q Cross-sectional views corresponding to some embodiments of action 520 are shown.

[0070] In action 522, the second dielectric layer and conductive material are planarized to form a second conductive structure (e.g., second conductive structure 118) and a second dielectric member (e.g., second dielectric member 108) in each of one or more trenches, the second dielectric member surrounding the second conductive structure. Figure 3R Cross-sectional views corresponding to some embodiments of action 522 are shown.

[0071] Some embodiments relate to integrated circuit (IC) devices. An IC device includes: a conductive layer; a dielectric structure disposed above the conductive layer; a first conductive structure disposed within the dielectric structure and spaced apart from the conductive layer; a semiconductor structure disposed within the dielectric structure and extending perpendicularly from the conductive layer to the first conductive structure; a first dielectric member disposed within the dielectric structure and extending perpendicularly from the conductive layer along the semiconductor structure; a conductive member disposed within the dielectric structure, located between and spaced apart from the conductive layer and the first conductive structure, and extending laterally from the first dielectric member; a second conductive structure disposed within the dielectric structure and extending perpendicularly near a surface of the conductive member opposite to the conductive layer; and a second dielectric member disposed within the dielectric structure and at least partially surrounding the second conductive structure to isolate the second conductive structure from the conductive member and the dielectric structure.

[0072] In some embodiments, the structure further includes: a first conductive contact structure disposed within the dielectric structure and extending perpendicularly from the conductive layer; and a second conductive contact structure disposed within the dielectric structure and extending perpendicularly from the first conductive structure away from the conductive layer. In some embodiments, the second conductive structure is laterally disposed between the first conductive contact structure and the second conductive contact structure. In some embodiments, a portion of the semiconductor structure further extends laterally along the surface of the first conductive structure facing the conductive layer and isolates the first conductive structure from the first dielectric member. In some embodiments, the vertical distance between the portion of the semiconductor structure and the conductive member is in the range of 1 nanometer to 10 nanometers. In some embodiments, the vertical distance between the conductive member and the conductive layer is in the range of 1 nanometer to 10 nanometers.

[0073] Some embodiments relate to another IC device. The IC device includes: a conductive layer; a dielectric structure disposed above the conductive layer; a first conductive structure disposed within the dielectric structure and spaced apart from the conductive layer; a semiconductor structure disposed within the dielectric structure and extending perpendicularly from the conductive layer to the first conductive structure; a first dielectric member disposed within the dielectric structure and extending perpendicularly from the conductive layer along the semiconductor structure; a plurality of conductive members disposed within the dielectric structure, located between the conductive layer and the first conductive structure and perpendicularly spaced apart from the conductive layer and the first conductive structure, and extending laterally from the first dielectric member; a plurality of second conductive structures disposed within the dielectric structure, each of the plurality of second conductive structures extending perpendicularly from a surface of a corresponding one of the plurality of conductive members relative to one of the conductive layers; and a plurality of second dielectric members disposed within the dielectric structure, each of the plurality of second dielectric members at least partially surrounding a corresponding one of the plurality of second conductive structures to isolate the corresponding one of the plurality of second conductive structures from the corresponding one of the plurality of conductive members and the dielectric structure.

[0074] In some embodiments, the structure further includes: a first conductive contact structure disposed within the dielectric structure and extending perpendicularly from the conductive layer; and a second conductive contact structure disposed within the dielectric structure and extending perpendicularly from the first conductive structure away from the conductive layer. In some embodiments, each of the plurality of second conductive structures is laterally disposed between the first conductive contact structure and the second conductive contact structure. In some embodiments, when starting from the first of the plurality of conductive members closest to the conductive layer, each of the second to the last of the plurality of conductive members is laterally shorter than the immediately preceding conductive member. In some embodiments, a portion of the semiconductor structure further extends laterally along the surface of the first conductive structure facing the conductive layer and isolates the first conductive structure from the first dielectric member.

[0075] Some embodiments relate to a method of forming an IC device. The method includes: providing a dielectric structure over a conductive layer, wherein one or more conductive members are located within the dielectric structure and the one or more conductive members extend laterally and are isolated from the conductive layer; etching the dielectric structure and the one or more conductive members to expose a portion of the conductive layer and a first end of each of the one or more conductive members; conformally forming a first dielectric layer on the dielectric structure, the first end of each of the one or more conductive members, and the portion of the conductive layer; etching a plurality of laterally lateral portions of the first dielectric layer to form a first dielectric member extending vertically from the conductive layer; conformally forming a semiconductor layer on the dielectric structure, the first dielectric member, and the portion of the conductive layer; and etching the semiconductor layer. The method comprises: forming a semiconductor structure extending vertically from the conductive layer and extending beside and above the first dielectric member; forming a first conductive structure on the dielectric structure and the semiconductor structure; forming one or more trenches within the dielectric structure, each of the one or more trenches extending to a corresponding one of the one or more conductive members; conformally forming a second dielectric layer above the dielectric structure, the second dielectric layer extending to the bottom of the one or more trenches; forming a conductive material on the second dielectric layer in each of the one or more trenches; and planarizing the second dielectric layer and the conductive material to form a second conductive structure and a second dielectric member in each of the one or more trenches, the second dielectric member surrounding the second conductive structure.

[0076] In some embodiments, the method further includes: forming an additional dielectric material on the dielectric structure prior to forming the one or more trenches; forming a first contact trench within the dielectric structure extending to the conductive layer; forming a second contact trench within the dielectric structure extending to the first conductive structure; filling the first contact trench with the conductive material to form a first conductive contact structure; and filling the second contact trench with the conductive material to form a second conductive contact structure. In some embodiments, the one or more trenches are located between the first contact trench and the second contact trench. In some embodiments, each of the one or more trenches extends close to a second end of a corresponding one of the one or more conductive members, the second end being opposite to the first end. In some embodiments, when the one or more conductive members comprise at least two conductive members, the lateral length of each of the one or more conductive members is less than the lateral length of any remaining one of the one or more conductive members closer to the conductive layer. In some embodiments, the semiconductor layer comprises two or more layers of different semiconductor materials. In some embodiments, the thickness of the semiconductor layer is in the range of 1 nanometer to 20 nanometers. In some embodiments, the thickness of the first dielectric layer is in the range of 5 nanometers to 20 nanometers. In some embodiments, the thickness of each of the one or more conductive components is in the range of 1 nanometer to 20 nanometers; and the thickness of the second dielectric layer is in the range of 5 nanometers to 10 nanometers.

[0077] It should be understood that in the written description and the appended claims, the terms "first," "second," "third," etc., are merely general designations used for ease of description to distinguish different components within a series of figures. In themselves, these terms do not imply any temporal order or structural proximity of the components and are not intended to describe corresponding components in different illustrated embodiments and / or not shown embodiments. For example, a "first dielectric layer" described in conjunction with the first figure may not necessarily correspond to a "first dielectric layer" described in conjunction with another figure, and may not necessarily correspond to an embodiment of a "first dielectric layer" not shown in the figures.

[0078] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of the present invention. Those skilled in the art will understand that they can readily use the present invention as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. An integrated circuit device, characterized by include: Conductive layer; A dielectric structure is disposed above the conductive layer; A first conductive structure is disposed within the dielectric structure and spaced apart from the conductive layer; A semiconductor structure disposed within the dielectric structure and extending perpendicularly from the conductive layer to the first conductive structure; A first dielectric member is disposed within the dielectric structure and extends perpendicularly from the conductive layer along the semiconductor structure; A conductive member is disposed within the dielectric structure, located between and separated from the conductive layer and the first conductive structure, and extends laterally from the first dielectric member; A second conductive structure is disposed within the dielectric structure and extends perpendicularly from near the surface of the conductive member opposite to the conductive layer; as well as A second dielectric member is disposed within the dielectric structure and at least partially surrounds the second conductive structure to isolate the second conductive structure from the conductive member and the dielectric structure.

2. The integrated circuit device of claim 1, wherein, Also includes: A first conductive contact structure is disposed within the dielectric structure and extends perpendicularly from the conductive layer; as well as A second conductive contact structure is disposed within the dielectric structure and extends perpendicularly from the first conductive structure away from the conductive layer.

3. The integrated circuit device of claim 2, wherein, The second conductive structure is laterally disposed between the first conductive contact structure and the second conductive contact structure.

4. The integrated circuit device according to claim 1, characterized in that, A portion of the semiconductor structure further extends laterally along the surface of the first conductive structure facing the conductive layer and isolates the first conductive structure from the first dielectric member.

5. The integrated circuit device according to claim 4, characterized in that, The vertical distance between the portion of the semiconductor structure and the conductive member is in the range of 1 nanometer to 10 nanometers.

6. The integrated circuit device according to claim 1, characterized in that, The vertical distance between the conductive component and the conductive layer is in the range of 1 nanometer to 10 nanometers.

7. An integrated circuit device, characterized in that, include: Conductive layer; A dielectric structure is disposed above the conductive layer; A first conductive structure is disposed within the dielectric structure and spaced apart from the conductive layer; A semiconductor structure disposed within the dielectric structure and extending perpendicularly from the conductive layer to the first conductive structure; A first dielectric member is disposed within the dielectric structure and extends perpendicularly from the conductive layer along the semiconductor structure; Multiple conductive components are disposed within the dielectric structure, located between the conductive layer and the first conductive structure and perpendicularly spaced apart from the conductive layer and the first conductive structure, and extending laterally from the first dielectric component; A plurality of second conductive structures are disposed within the dielectric structure, each of the plurality of second conductive structures extending perpendicularly from the vicinity of the surface of a corresponding one of the plurality of conductive members relative to the conductive layer; as well as A plurality of second dielectric members are disposed within the dielectric structure, each of the plurality of second dielectric members at least partially surrounding a corresponding one of the plurality of second conductive structures to isolate the corresponding one of the plurality of second conductive structures from the corresponding one of the plurality of conductive members and the dielectric structure.

8. The integrated circuit device according to claim 7, characterized in that, Also includes: A first conductive contact structure is disposed within the dielectric structure and extends perpendicularly from the conductive layer; as well as A second conductive contact structure is disposed within the dielectric structure and extends perpendicularly from the first conductive structure away from the conductive layer.

9. The integrated circuit device according to claim 8, characterized in that, Each of the plurality of second conductive structures is laterally disposed between the first conductive contact structure and the second conductive contact structure.

10. The integrated circuit device according to claim 7, characterized in that, When starting from the first of the plurality of conductive members closest to the conductive layer, each of the second to the last of the plurality of conductive members is laterally shorter than the immediately preceding one of the plurality of conductive members.

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