A composite substrate suitable for high-performance computing

Abstract

This utility model provides a composite substrate suitable for high-performance computing, relating to the semiconductor field, comprising: a first substrate having a through-groove along its thickness direction; a second substrate disposed in the through-groove, with a buffer zone between the first and second substrates, the first and second substrates being electrically connected through the buffer zone; an ASIC chip disposed above the second substrate, the ASIC chip being electrically connected to both the first and second substrates; and a DRAM chip disposed above the second substrate, the DRAM chip being electrically connected to both the first and second substrates. The first substrate is an organic substrate, and the second substrate is a glass substrate. This application utilizes the smooth surface of the glass substrate, which enables narrower linewidths and spacings, to combine the glass substrate and the organic substrate, thereby reducing the size of the composite substrate suitable for high-performance computing while maintaining the same interconnect speed.

Description

Technical Field

[0001] This utility model relates to the semiconductor field, and in particular to a composite substrate suitable for high-performance computing. Background Technology

[0002] In the field of high-performance computing, high-speed interconnection is usually required between ASIC chips and DRAM to achieve high-speed communication. However, conventional organic substrates have poor surface flatness and high requirements for line width and line spacing, and usually require very large dimensions to achieve high-speed signal interconnection.

[0003] In order to achieve product miniaturization, how to reduce the size of the substrate while ensuring the speed of interconnect signal transmission has become an urgent problem to be solved. Utility Model Content

[0004] This invention provides a composite substrate suitable for high-performance computing, which aims to solve the problem that the size of existing substrates cannot be further reduced due to the high linewidth requirements when realizing high-speed signal interconnection.

[0005] To achieve the above objectives, embodiments of this utility model provide a composite substrate suitable for high-performance computing, comprising:

[0006] A first substrate, wherein a through groove is formed along the thickness direction;

[0007] A second substrate is disposed in the through slot, and the second substrate is electrically connected to the first substrate;

[0008] A buffer zone is provided between the first substrate and the second substrate, and the first substrate and the second substrate are electrically connected through the buffer zone;

[0009] An ASIC chip is disposed above the second substrate, and the ASIC chip is electrically connected to the first substrate and the second substrate respectively;

[0010] A DRAM chip is disposed above the second substrate, and the DRAM chip is electrically connected to the first substrate and the second substrate respectively;

[0011] The first substrate is an organic substrate, and the second substrate is a glass substrate.

[0012] Preferably, the buffer is made of shape memory alloy.

[0013] Preferably, the buffer is made of a shape memory polymer with conductive properties.

[0014] Preferably, the ASIC chip is electrically connected to the first substrate and the second substrate through microbumps;

[0015] The DRAM chip is electrically connected to the first substrate and the second substrate through microbumps.

[0016] Preferably, the lower ends of the first substrate and the second substrate are respectively provided with planting balls.

[0017] The above-mentioned solution of this utility model has the following beneficial effects:

[0018] This application utilizes the smooth surface of the glass substrate, which enables narrower linewidths and spacings, to combine the glass substrate with the organic substrate. While maintaining the same interconnect speed, the size of the composite substrate suitable for high-performance computing can be reduced.

[0019] Other features and advantages of this invention will be described in detail in the following detailed description section. Attached Figure Description

[0020] Figure 1 This is a top view of the present invention;

[0021] Figure 2 yes Figure 1 Sectional view along the AA direction.

[0022] [Explanation of Labels in the Attached Image]

[0023] 1-First substrate, 2-Second substrate, 3-Buffer zone, 4-ASIC chip, 5-DRAM chip, 6-Micro bump, 7-Ball placement. Detailed Implementation

[0024] To make the technical problems, technical solutions and advantages of this utility model clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.

[0025] like Figure 1 and Figure 2As shown, an embodiment of this utility model provides a composite substrate suitable for high-performance computing, including a first substrate 1, a second substrate 2, an ASIC chip 4, and a DRAM chip 5. The first substrate 1 has a through-slot formed at its center along its thickness direction. The second substrate 2 is located within this through-slot. A buffer zone 3 is provided between the first substrate 1 and the second substrate 2, maintaining electrical connection between the two substrates. The ASIC chip 4 (Application Specific Integrated Circuit) is located above the second substrate 2 and is electrically connected to both the first substrate 1 and the second substrate 2. The DRAM chip 5 (Dynamic Random Access Memory) is located above the second substrate 2 and is electrically connected to both the first substrate 1 and the second substrate 2.

[0026] The aforementioned first substrate 1 is an organic substrate and the second substrate 2 is a glass substrate.

[0027] In this application, the glass substrate has a smooth and flat surface, which enables narrower line widths and spacings, significantly increasing wiring density. While achieving the same interconnect speed, it allows for smaller composite substrates suitable for high-performance computing, which is beneficial for product miniaturization.

[0028] Preferably, the buffer zone 3 is made of shape memory alloy.

[0029] Preferably, the buffer zone 3 is made of a shape memory polymer with conductive properties, such as a shape memory polymer that achieves conductivity by adding conductive fillers.

[0030] Meanwhile, the ASIC chip 4 is electrically connected to the first substrate 1 and the second substrate 2 via microbumps 6, and the DRAM chip 5 is also electrically connected to the first substrate 1 and the second substrate 2 via microbumps 6. Memory alloys can change shape based on temperature. Since the expansion coefficients of the two glass substrates and the organic substrate are different, adding a buffer zone 3 between them can reduce the probability of deformation of the composite substrate suitable for high-performance computing and improve the reliability of the connection between the microbumps 6 and the first substrate 1 and the second substrate 2.

[0031] Preferably, the lower ends of the first substrate 1 and the second substrate 2 are respectively provided with planting balls 7.

[0032] The above description is the preferred embodiment of this utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this utility model, and these improvements and modifications should also be considered within the protection scope of this utility model.

Claims

1. A composite substrate suitable for high-performance computing, characterized in that, include: The first substrate (1) has a through groove along its thickness direction; The second substrate (2) is disposed in the through slot, and a buffer zone (3) is disposed between the first substrate (1) and the second substrate (2), and the first substrate (1) and the second substrate (2) are electrically connected through the buffer zone (3); An ASIC chip (4) is disposed above the second substrate (2), and the ASIC chip (4) is electrically connected to the first substrate (1) and the second substrate (2) respectively. A DRAM chip (5) is disposed above the second substrate (2), and the DRAM chip (5) is electrically connected to the first substrate (1) and the second substrate (2) respectively. The first substrate (1) is an organic substrate, and the second substrate (2) is a glass substrate.

2. The composite substrate suitable for high-performance computing according to claim 1, characterized in that: The buffer (3) is made of shape memory alloy.

3. The composite substrate suitable for high-performance computing according to claim 1, characterized in that: The buffer (3) is made of a shape memory polymer with conductive properties.

4. The composite substrate suitable for high-performance computing according to claim 1, characterized in that: The ASIC chip (4) is electrically connected to the first substrate (1) and the second substrate (2) through microbumps (6); The DRAM chip (5) is electrically connected to the first substrate (1) and the second substrate (2) through microbumps (6).

5. The composite substrate suitable for high-performance computing according to claim 1, characterized in that: The lower ends of the first substrate (1) and the second substrate (2) are respectively provided with planting balls (7).

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