A graphics processing system based on embedded dual-core ARM chip control

Abstract

The utility model discloses a kind of graphic processing systems based on embedded dual-core ARM chip control, it is related to embedded graphic processing technical field, and the problem of low processing efficiency, poor real-time performance and signal processing complexity existing in current graphic processing system is solved.A kind of graphic processing systems based on embedded dual-core ARM chip control, containing embedded dual-core ARM chip circuit, figure input module, figure processing module, figure storage module, figure output module, data interaction module, alarm module and display module;The utility model is provided with dual-core ARM chip circuit, and main core is responsible for figure rendering, and coordination core is responsible for system control and real-time signal processing, in combination with FPGA hardware acceleration unit and high-speed parallel bus, through multi-source signal synchronous circuit and multiple input and output interfaces, support multi-source signal input and high-resolution output, meet the graphic processing demand under complex scene.

Description

Technical Field

[0001] This utility model relates to the field of graphics processing technology, specifically to a graphics processing system based on an embedded dual-core ARM chip. Background Technology

[0002] Graphics processing systems based on embedded dual-core ARM chips have a wide range of applications. These systems collect various data from graphics input devices and transmit the data to the embedded dual-core ARM chip and related processing modules via a high-speed parallel bus, helping users to achieve graphics rendering, processing, and output functions.

[0003] In summary, graphics processing systems based on embedded dual-core ARM chips have many advantages; however, they also have some disadvantages and drawbacks, including the following:

[0004] 1. Data processing efficiency issues: Existing graphics processing systems based on embedded dual-core ARM chips have a problem where communication delays may occur between the main core and the co-core in the specific working process of graphics rendering and real-time signal processing, which affects the graphics processing speed and response timeliness.

[0005] 2. Storage capacity limitation: The storage capacity and bandwidth of the graphics processing system based on the embedded dual-core ARM chip are low when processing large-scale graphics data, which makes it inconvenient for users to perform fast storage and retrieval operations on large amounts of graphics data.

[0006] In summary, graphics processing systems based on embedded dual-core ARM chips still need improvement in key areas such as data processing collaboration and storage performance. Continuous optimization of the technology is required to enhance the overall processing power and stability of the system. Utility Model Content

[0007] The purpose of this invention is to provide a graphics processing system based on an embedded dual-core ARM chip, in order to solve the problems of slow processing speed, low efficiency, poor stability and insufficient scalability of existing graphics processing systems.

[0008] To achieve the above-mentioned technical effects, the present invention adopts the following technical solution:

[0009] A graphics processing system based on an embedded dual-core ARM chip includes:

[0010] The embedded dual-core ARM chip circuit consists of an ARM Cortex-A53 main core and an ARM Cortex-M7 co-core. The main core is responsible for graphics rendering, and the co-core is responsible for system control and real-time signal processing. The two cores are interconnected through a high-speed parallel bus and integrated on a PCB substrate.

[0011] The graphics input module is equipped with a multi-source signal synchronization circuit and supports HDMI, VGA and USB input interfaces. The signals from each interface are uniformly converted into LVDS signals by a level conversion chip and then input to the dual-core ARM chip.

[0012] The graphics processing module consists of FPGA hardware and a dual-core ARM chip working together. The FPGA has a built-in hardware acceleration unit for real-time image edge detection and color space conversion.

[0013] The graphics storage module uses LPDDR4 memory chips and NAND Flash, which are integrated on the system motherboard through multi-layer stacking packaging technology, with a storage bandwidth of 16GB / s.

[0014] The graphics output module integrates a DisplayPort 1.4 output interface and is equipped with an LVDS to DisplayPort conversion circuit, supporting 4K@60Hz resolution output;

[0015] The data interaction module expands the connectivity of external devices based on the PCIe 3.0 interface and is equipped with physical isolation circuitry to prevent signal crosstalk.

[0016] The alarm module consists of a temperature sensor and a voltage monitoring chip. When the system temperature exceeds 85℃ or the power supply voltage fluctuates by more than ±5%, it triggers a buzzer and an LED warning light.

[0017] The display module has a built-in 7-inch OLED touchscreen and is directly connected to a dual-core ARM chip via a MIPI-DSI interface, supporting real-time status monitoring and interactive operation.

[0018] The output terminal of the graphics input module is connected to the input terminal of the embedded dual-core ARM chip circuit. The output terminal of the main core in the embedded dual-core ARM chip circuit is connected to the input terminal of the graphics processing module. The output terminal of the graphics processing module is connected to the input terminal of the graphics storage module. The output terminal of the graphics storage module is connected to the input terminal of the graphics output module. The output terminal of the co-core in the embedded dual-core ARM chip circuit is connected to the input terminals of the data interaction module and the alarm module. The input terminal of the display module is connected to the output terminals of the main core and the co-core in the embedded dual-core ARM chip circuit, respectively.

[0019] As a further description of the above technical solution:

[0020] The embedded dual-core ARM chip circuit integrates a hardware watchdog timer, supporting independent monitoring of both cores. When a deadlock occurs in the main core or co-core, it can trigger a system reset. The reset signal is transmitted through a dedicated wiring layer to ensure anti-interference capability. The high-speed parallel bus adopts a 128-bit bidirectional data transmission design, supporting communication bandwidth of up to 2GB / s between ARM Cortex-A53 and ARM Cortex-M7 cores. The bus protocol adopts the AXI4 standard.

[0021] As a further description of the above technical solution:

[0022] The FPGA hardware acceleration unit includes a configurable logic block (CLB) array, supports dynamic reconfiguration technology, and can switch between image edge detection and color space conversion functions according to the processing task requirements. The multi-layer stacked packaging technology adopts a through-silicon via (TSV) three-dimensional integration process, with LPDDR4 chips stacked on top of NAND Flash and vertical interconnection achieved through micro-bumps. The package thickness does not exceed 1.2mm.

[0023] As a further description of the above technical solution:

[0024] The graphics input module includes an HDMI receiver chip, a VGA analog-to-digital converter circuit, and a USB 3.0 controller. Each interface signal is converted into an LVDS signal by a level conversion chip and then input to the LVDS receiver interface of the dual-core ARM chip circuit through an FPC cable. The level conversion chip of the graphics input module supports the HDCP2.2 content protection protocol, the HDMI interface supports 4K@30Hz input, the VGA interface supports 1920×1080@60Hz input, and the USB interface conforms to the USB3.1 Gen1 standard.

[0025] As a further description of the above technical solution:

[0026] The graphics storage module uses 3D TLC NAND Flash with a capacity of 128GB; the LPDDR4 memory chip has a capacity of 4GB, an operating voltage of 1.1V, and supports data self-refresh function.

[0027] As a further description of the above technical solution:

[0028] The graphics output module integrates a DisplayPort 1.4 transmitter chip and an LVDS to DisplayPort conversion circuit. It receives the LVDS signal output from the dual-core ARM chip circuit, processes it, and transmits it to the DisplayPort interface via a coaxial cable. It supports 4K@60Hz resolution output. The conversion circuit integrates a jitter cancellation unit and adopts Spread Spectrum Clocking technology to control signal jitter within 0.15UI and conversion delay <2ms.

[0029] As a further description of the above technical solution:

[0030] The data interaction module's PCIe 3.0 interface is configured with 4 independent channels, each with a transmission rate of 8GT / s. The physical isolation circuit adopts a combination design of electromagnetic shield and common-mode choke, with an isolation of >60dB@1GHz.

[0031] As a further description of the above technical solution:

[0032] The alarm module includes a temperature sensor, a voltage monitoring chip, a buzzer, and an LED warning light. The temperature sensor is located inside the system and monitors the system temperature; the voltage monitoring chip is located on the PCB substrate and monitors the power supply voltage; the buzzer is located on the front panel of the system and is used for audible alarm; the LED warning light is located on the front panel of the system, has an IP65 protection rating, and supports red / yellow dual-color warning.

[0033] As a further description of the above technical solution:

[0034] The 7-inch OLED touchscreen of the display module adopts On-Cell touch technology, with a resolution of 1920×1200, a pixel density of 326PPI, supports 10-finger touch, is covered with Gorilla Glass, has an anti-glare coating, a brightness adjustment range of 100-800 nits, a refresh rate of 60Hz, and a color gamut coverage of DCI-P3 98%.

[0035] The beneficial effects of this utility model are as follows:

[0036] This invention utilizes an embedded dual-core ARM chip circuit, enabling the ARM Cortex-A53 main core and the ARM Cortex-M7 co-core to work collaboratively, effectively solving the problems of low graphics processing efficiency and weak multitasking capabilities of traditional single-core chips. The graphics input module is equipped with a multi-source signal synchronization circuit and a level conversion chip supporting the HDCP2.2 protocol, significantly enhancing the system's compatibility with different graphics input devices and the stability of signal transmission. The graphics processing module, where the FPGA hardware and the dual-core ARM chip work in tandem, greatly improves the real-time performance and specificity of graphics processing. The data interaction module, based on the CIe 3.0 interface, is equipped with a physical isolation circuit, expanding external device connectivity and effectively preventing signal crosstalk, thus enhancing system stability and reliability. The display module features a built-in 7-inch OLED touchscreen, employing On-Cell touch technology, supporting 10-finger touch and high-resolution display, facilitating real-time status monitoring and interactive operation for users. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0038] Figure 1 This is an overall structural diagram of a graphics processing system based on an embedded dual-core ARM chip controlled by the present invention.

[0039] Figure 2 This is an application diagram of an embodiment of the graphics processing system based on an embedded dual-core ARM chip controlled by this utility model;

[0040] Figure 3 This is a structural diagram of a graphics input module of a graphics processing system based on an embedded dual-core ARM chip controlled by the present invention.

[0041] Figure 4 This is a circuit diagram of a graphics input module for a graphics processing system based on an embedded dual-core ARM chip controlled by the present invention.

[0042] The diagram shows: Graphics input module-2, graphics processing module-3, graphics storage module-4, graphics output module-5, data interaction module-6, alarm module-7, display module-8, HDMI receiver chip-201, VGA analog-to-digital conversion circuit-202 and USB 3.0 controller-203, temperature sensor-701, voltage monitoring chip-702, buzzer-703, and LED warning light-704. Detailed Implementation

[0043] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0044] A graphics processing system based on an embedded dual-core ARM chip includes:

[0045] The embedded dual-core ARM chip circuit consists of an ARM Cortex-A53 main core 101 and an ARM Cortex-M7102 co-core. The main core is responsible for graphics rendering, and the co-core is responsible for system control and real-time signal processing. The two cores are interconnected through a high-speed parallel bus and integrated on a PCB substrate.

[0046] Graphics input module 2 is equipped with a multi-source signal synchronization circuit and supports HDMI, VGA and USB input interfaces. The signals from each interface are converted into LVDS signals by a level conversion chip and then input to the dual-core ARM chip.

[0047] The graphics processing module 3 consists of FPGA hardware and a dual-core ARM chip working together. The FPGA has a built-in hardware acceleration unit for real-time image edge detection and color space conversion.

[0048] The graphics storage module 4 uses LPDDR4 memory chips and NAND Flash, which are integrated on the system motherboard through multi-layer stacking packaging technology, with a storage bandwidth of 16GB / s.

[0049] Graphics output module 5 integrates a DisplayPort 1.4 output interface and is equipped with an LVDS to DisplayPort conversion circuit, supporting 4K@60Hz resolution output;

[0050] Data interaction module 6 expands the external device connectivity based on the PCIe 3.0 interface and is equipped with physical isolation circuitry to prevent signal crosstalk;

[0051] Alarm module 7 consists of a temperature sensor and a voltage monitoring chip. When the system temperature exceeds 85℃ or the power supply voltage fluctuates by more than ±5%, it triggers a buzzer and an LED warning light.

[0052] Display module 8 has a built-in 7-inch OLED touchscreen and is directly connected to a dual-core ARM chip via a MIPI-DSI interface, supporting real-time status monitoring and interactive operation.

[0053] The output terminal of the graphics input module 2 is connected to the input terminal of the embedded dual-core ARM chip circuit. The output terminal of the main core in the embedded dual-core ARM chip circuit 2 is connected to the input terminal of the graphics processing module 3. The output terminal of the graphics processing module 3 is connected to the input terminal of the graphics storage module 4. The output terminal of the graphics storage module 4 is connected to the input terminal of the graphics output module 5. The output terminal of the co-core in the embedded dual-core ARM chip circuit is connected to the input terminals of the data interaction module 6 and the alarm module 7. The input terminal of the display module 8 is connected to the output terminals of the main core and the co-core in the embedded dual-core ARM chip circuit, respectively.

[0054] Furthermore, the embedded dual-core ARM chip circuit integrates a hardware watchdog timer, supporting independent monitoring of both cores. When a deadlock occurs in the main core or co-core, it can trigger a system reset. The reset signal is transmitted through a dedicated wiring layer to ensure anti-interference capability. The high-speed parallel bus adopts a 128-bit bidirectional data transmission design, supporting a communication bandwidth of up to 2GB / s between ARM Cortex-A53 and ARM Cortex-M7 cores. The bus protocol adopts the AXI4 standard.

[0055] In a specific embodiment, when constructing a graphics processing system based on an embedded dual-core ARM chip, the first step is to install the chip circuitry. The embedded dual-core ARM chip circuitry is precisely installed on a customized PCB substrate, ensuring that the ARM Cortex-A53 main core 101 and the ARM Cortex-M7 co-core 102 are correctly interconnected via a high-speed parallel bus. The chip circuitry uses BGA packaging with immersion gold plating. During the soldering process, a specific temperature control curve is strictly followed. In the preheating stage, the temperature increases at a rate of 1-3°C per minute to 150-160°C and is maintained for 60-120 seconds. In the reflow stage, the temperature rapidly rises to 217-230°C and is maintained for 40-90 seconds to ensure solder joint quality and effectively avoid problems such as cold solder joints and short circuits. Next, a watchdog timer is configured. During the chip circuit design stage, a hardware watchdog timer is integrated. The circuit must be independently connected to the dual cores to monitor the operating status of the main core and the co-core separately. The watchdog timer is set to a 1.6-second period. If the main core or co-core experiences a deadlock and fails to feed the watchdog within the specified 1.6-second time, the watchdog timer will trigger a system reset. The reset signal line uses differential transmission and is arranged on a dedicated routing layer. This routing layer uses a 0.2mm thick copper layer and is spaced at least 2H from the signal lines to effectively enhance anti-interference capabilities. Testing shows that in an environment with electromagnetic interference in the 100MHz-1GHz frequency band, the bit error rate of signal transmission can be controlled within 10⁻⁻⁶. 9 Finally, the high-speed parallel bus configuration is described. The high-speed parallel bus employs a 128-bit bidirectional data transmission design, using microstrip lines with a line width of 0.3mm and a spacing of 0.4mm. The bus connects the data ports of the ARM Cortex-A53 and ARM Cortex-M7, ensuring an inter-core communication bandwidth of 2GB / s. The bus protocol adopts the AXI4 standard, and a corresponding AXI4 interface IP core is configured in the FPGA to achieve data read / write control. In actual testing, the data read / write success rate reaches over 99.9%.

[0056] Furthermore, the FPGA hardware acceleration unit includes a configurable logic block (CLB) array that supports dynamic reconfiguration technology, switching between image edge detection and color space conversion functions according to processing task requirements; the multi-layer stacked packaging technology adopts a through-silicon via (TSV) three-dimensional integration process, with LPDDR4 chips stacked on top of NAND Flash, and vertical interconnection achieved through micro-bumps, with a package thickness not exceeding 1.2mm.

[0057] In a specific embodiment, in a graphics processing system based on an embedded dual-core ARM chip, FPGA device selection, initialization, and multi-layer stacking packaging technology are core aspects ensuring high-performance system operation. The FPGA has a large-scale CLB array providing over 500K logic unit resources, achieving high-speed data transmission of 8GB / s with the ARM chip via a PCIe 3.0 interface. After power-on, the ARM main core drives the loading of configuration data from the SPI Flash, defaulting to image edge detection mode. The internal dynamic reconstruction control module receives ARM co-core instructions via the AXI4-Lite bus, completing the switching between edge detection and color space conversion functions within 200ms, saving 40% of hardware resources compared to fixed logic designs. During image data processing, the FPGA's convolution operation efficiency reaches 1200GMAC / s in edge detection mode, and 120 million pixels per second in color conversion mode, a three-fold speed improvement over traditional solutions. The multi-layer stacked packaging technology utilizes Through Silicon Vias (TSV) technology. In the NAND Flash and LPDDR4 chip stacking, 5μm diameter TSV vias achieve a 10:1 aspect ratio, coupled with ±2μm bonding precision, ensuring vertical interconnect parasitic capacitance is below 0.5pF. 30μm diameter microbumps, formed through reflow soldering, create an ultra-low resistance connection of 0.1Ω, enabling a storage bandwidth of 16GB / s, a 2.5-fold improvement over traditional packaging. The package is molded from low-expansion-coefficient epoxy resin, and its 1.2mm ultra-thin design saves 60% of space. After rigorous testing, the data transmission error rate is as low as 1e-12. Performance remains undiminished after high-temperature storage, thousands of temperature cycles, and triaxial mechanical vibration. It can operate stably for over 10 years in industrial-grade environments ranging from -40℃ to 85℃, significantly improving system integration, data processing efficiency, and environmental adaptability.

[0058] Furthermore, the graphics input module 2 includes an HDMI receiver chip 201, a VGA analog-to-digital converter circuit 202, and a USB 3.0 controller 203. After each interface signal is converted into an LVDS signal by a level conversion chip, it is input to the LVDS receiver interface of the dual-core ARM chip circuit 1 through an FPC cable. The level conversion chip of the graphics input module 2 supports the HDCP 2.2 content protection protocol, the HDMI interface supports 4K@30Hz input, the VGA interface supports 1920×1080@60Hz input, and the USB interface conforms to the USB 3.1 Gen 1 standard.

[0059] In a specific embodiment, at the interface configuration level, the HDMI receiver chip is the TI DS90UB913, which has four HDMI 2.0 input channels, supports 4K@30Hz signal reception and HDCP 2.2 key handshake verification, and the 5V TVS diode at the interface can achieve ±8kV electrostatic protection; the VGA analog-to-digital conversion circuit uses the AD9955 chip, with three 10-bit analog channels supporting 1920×1080@60Hz input, and the built-in clock recovery circuit enables a conversion accuracy of 0.1%, and the interface ferrite bead filter suppresses power ripple to within 50mV; the USB 3.0 controller is the VIA VL812, which supports the USB 3.1 Gen1 standard and four 5Gbps SuperSpeed ​​channels, and the 15kV ESD protection device can resist high-frequency electromagnetic interference, with a data buffer capacity of 256KB to ensure a device enumeration success rate of ≥99.9%. In terms of level conversion and signal transmission, the TI TXB0108 level conversion chip supports a wide voltage conversion range of 1.2V-3.3V with a bidirectional transmission delay of <5ns, converting HDMI / VGA / USB signals to a unified 1.8V LVDS level. The LVDS signal is transmitted through a 30AWG FPC cable with a transmission loss of <3dB within 200mm. The 100Ω±5Ω impedance matching ensures that the signal eye diagram opening is ≥80%. With the terminating resistor on the ARM chip side, the bit error rate is controlled below 1e-10. The module is integrated using a 60mm×40mm 4-layer PCB board with a 0.2mm gap between the top signal layer and the bottom ground layer, a power layer internal resistance of <50mΩ, and a microstrip line width designed at 100mA / mm to ensure no signal reflection at a peak transmission rate of 1.6GB / s. In functional testing, the HDMI channel decryption latency is <100μs, the RGB data distortion of the VGA conversion circuit is <0.5%, and the USB controller throughput reaches 450MB / s. Signal integrity testing shows that the LVDS signal rise / fall time is ≤500ps, electromagnetic compatibility testing meets the CISPR 22 Class B standard, the response time during multi-source signal switching is <20ms, and there is no data loss or conflict. Compared with traditional hybrid interface solutions, the integration level is improved by 30%, and the signal transmission stability is improved by 40%, fully meeting the compatibility and reliability requirements of high-definition multi-source input scenarios.

[0060] Furthermore, the graphics storage module 4 uses 3D TLC NAND Flash with a capacity of 128GB; the LPDDR4 memory chip has a capacity of 4GB, an operating voltage of 1.1V, and supports data self-refresh function.

[0061] In a specific embodiment, the NAND Flash uses Samsung K9KBN8U0EM-CCK0 3D TLC chips with a single chip capacity of 128GB. It supports the ONFI 3.0 interface standard and has a data transfer rate of 400MT / s. Combined with the NAND controller of the ARM chip, it achieves sequential write speeds of 200MB / s and sequential read speeds of 250MB / s, with performance fluctuations of <5% within a temperature range of -40℃ to 85℃. The LPDDR4 memory chip has a single chip capacity of 4GB, operates at a low voltage of 1.1V, supports a data transfer rate of 3200Mbps and a data self-refresh function, and is connected to the ARM memory controller through a 16-bit data bus. Combined with a low-noise LDO regulator, the power supply noise is controlled below 30mV to ensure the stability of high-frequency data transmission. In the storage module circuit design, an independent power management circuit provides 3.3V power to the NAND Flash with a DC-DC conversion efficiency of 90% and ripple ≤50mV, and provides 1.1V power to the LPDDR4 with LDO noise ≤30mV. The power and ground planes of the multi-layer PCB are spaced 0.15mm apart, forming a low-impedance power distribution system to reduce the impact of power fluctuations on storage operations. Regarding signal integrity, the NAND Flash data lines, address / control lines, and LPDDR4 data lines all employ strict impedance control, with a wiring length matching error <50mil, ensuring signal rise / fall times ≤300ps, data setup / hold time margin >150ps, and a bit error rate below 1e-12. The module integrates a 30mm×30mm 6-layer PCB board with BGA-packaged solder balls of 0.4mm diameter and 0.8mm spacing, achieving high-density electrical connections. Functional testing showed zero data loss after 72 hours of backup battery power, and LPDDR4 operated continuously for 24 hours at 3200Mbps without errors. Reliability testing showed that after high-temperature storage at 125℃ for 1000 hours, 1000 temperature cycles from -40℃ to 85℃, and triaxial 20g vibration, the module maintained a read / write performance retention rate of >98%, achieving a storage bandwidth of 16GB / s, 2.5 times higher than traditional planar packaging solutions. The package thickness is only 1.2mm, reducing space occupation by 40%. This solution, through high-speed transmission interfaces, precise power management, and strict signal integrity design, achieves efficient storage and stable access to graphics data, meeting the stringent requirements of 4K@60Hz graphics processing for storage bandwidth and reliability, with a mean time between failures (MTBF) exceeding 100,000 hours in complex industrial environments.

[0062] Furthermore, the graphics output module 5 integrates a DisplayPort 1.4 transmitter chip and an LVDS to DisplayPort conversion circuit. It receives the LVDS signal output from the dual-core ARM chip circuit 1, processes it, and transmits it to the DisplayPort interface via a coaxial cable, supporting 4K@60Hz resolution output. The conversion circuit integrates a jitter elimination unit and adopts Spread Spectrum Clocking technology, controlling signal jitter within 0.15UI and conversion delay <2ms.

[0063] In this specific embodiment, the DisplayPort 1.4 transmitter chip is the Parade PS8301, which supports 4K@60Hz resolution output. It integrates four 8.1Gbps main link channels with a total bandwidth of 32.4Gbps, meeting the high-speed transmission requirements of 4K video data. It connects to external devices via the DisplayPort interface, and a 5V TVS diode at the interface provides ±8kV electrostatic protection. Internal pre-emphasis and equalization circuits improve signal attenuation compensation by 40%, ensuring an eye diagram opening of ≥75% at 8.1Gbps. The LVDS to DisplayPort conversion circuit uses the TI DS90UB914 chip. The 100Ω±5Ω impedance matching design at the input ensures stable LVDS signal reception. The integrated jitter cancellation unit and Spread Spectrum Clocking technology control signal jitter to 0.15UI, with a conversion delay of only 1.8ms, a 28% reduction compared to traditional solutions, meeting the low-latency requirements for real-time graphics output. In signal processing and transmission design, the coaxial cable adopts a double-shielded structure. The inner low-loss dielectric layer ensures that the insertion loss of the 8.1Gbps signal is <0.5dB and the return loss is >15dB, while the outer grounded shielding layer suppresses electromagnetic radiation to below 30dBμV / m. The DisplayPort interface hot-plug detection circuit has a response time of <50μs, ensuring plug-and-play functionality. In functional testing, the color distortion of the 4K@60Hz signal after conversion is <0.3%, and the frame rate stability error is <0.1%. Signal integrity testing shows that the DisplayPort signal rise / fall time is ≤400ps, and the timing margin is >200ps, meeting the VESA DisplayPort 1.4 standard. There are no black screen or screen distortion issues, and the device enumeration success rate is 100%. The above technical solution achieves lossless transmission of 4K@60Hz high-definition signals through a 32.4Gbps ultra-high-speed transmission channel, 0.15UI ultra-low jitter control, and dual-shielded anti-interference design. It increases bandwidth by 2 times and reduces latency by 50% compared to traditional HDMI solutions. It can operate continuously for 100,000 hours without failure in an industrial-grade environment of -40℃ to 85℃, improving the compatibility and reliability of high-end display devices.

[0064] Furthermore, the PCIe 3.0 interface of the data interaction module 6 is configured with 4 independent channels, each with a transmission rate of 8GT / s. The physical isolation circuit adopts a combination design of electromagnetic shield and common mode choke, with an isolation of >60dB@1GHz.

[0065] In a specific embodiment, the PCIe 3.0 interface controller uses the PLX PEX8747 chip, supporting four independent channels, each with a transmission rate of 8GT / s and a total bandwidth of 32GT / s. It connects to the ARM chip's PCIe controller via an x4 lane. The built-in error detection and correction mechanism can control the data transmission error rate below 1e-12. The physical isolation circuit employs a combination of a copper alloy electromagnetic shield and a 1.2μH high-permeability ferrite common-mode choke. The shield is fully bonded to the PCB board, and the common-mode choke operates at frequencies above 1GHz, achieving an isolation level of >60dB@1GHz, which improves anti-interference capability by 50% compared to traditional single-stage filtering schemes. In the circuit design, an independent power management circuit provides 3.3V power to the controller. The DC-DC converter efficiency reaches 92%, with an output ripple ≤40mV. The power and ground plane spacing on the multi-layer PCB is 0.15mm, reducing the power impedance to below 20mΩ, ensuring power supply stability under high-frequency operation. In terms of signal integrity, the data line adopts a differential microstrip line structure (0.3mm line width, 0.3mm spacing, impedance 100Ω±5Ω), with a wiring length matching error of <30mil. The reference ground plane design ensures a signal crosstalk suppression ratio of over 25dB, guaranteeing a signal eye diagram opening of ≥85% and a timing margin of >180ps at 8GT / s. During functional testing, the PCIe 3.0 tester verified that the module transmitted continuously for 24 hours at full speed (32GT / s) without data errors. The physical isolation circuit achieved a measured isolation of 62dB in the 1GHz band, exceeding the design specification by 2dB. Signal integrity testing showed a signal rise / fall time of ≤350ps, fully complying with PCIe 3.0 electrical standards. After environmental reliability testing, the module remained functional after 1000 hours of storage at 125℃, 1000 temperature cycles, and 20g triaxial vibration, with data transmission rate fluctuations of <1%. Multi-device compatibility testing showed a 100% success rate with no communication timeouts or data misalignments. The above solution, through a 32GT / s ultra-high-speed data channel, a 60dB high isolation anti-interference design, and strict signal integrity optimization, improves the external device connectivity by 4 times compared to the traditional PCIe 2.0 solution, reduces the risk of signal crosstalk by 60%, and enables stable and reliable high-speed data interaction with a mean time between failures (MTBF) of over 150,000 hours, meeting the long-term stable operation requirements in harsh environments.

[0066] Furthermore, the alarm module 7 includes a temperature sensor 701, a voltage monitoring chip 702, a buzzer 703, and an LED warning light 704. The temperature sensor 701 is located inside the system and monitors the system temperature; the voltage monitoring chip 702 is located on the PCB substrate and monitors the power supply voltage; the buzzer 703 is located on the front panel of the system and is used for audible alarm; the LED warning light 704 is located on the front panel of the system, adopts an IP65 protection rating, and supports red / yellow dual-color warning.

[0067] In a specific embodiment, the temperature sensor is a Melexis MLX90614 infrared sensor, which supports non-contact temperature measurement from -40℃ to 330℃ with an accuracy of ±0.5℃. It can complete one temperature acquisition within 500ms. It is connected to the ARM co-core via the I²C bus and installed within 5mm of the heating element to ensure real-time monitoring of the system's hot spot temperature. The voltage monitoring chip is a Texas Instruments LM2936Z, covering a monitoring range of 2.7V to 13.2V. It can respond to voltage fluctuations within 10μs and acquires the power bus voltage in real time through a 1% accuracy voltage divider resistor network. When the fluctuation exceeds ±5%, it triggers an interrupt signal from the ARM co-core within 0.1ms. The buzzer uses a 3V-24V piezoelectric device with a sound frequency of 1kHz-5kHz. The drive circuit uses a PNP transistor to achieve a 20mA drive current, and the alarm volume is ≥85dB. The LED warning light is a red / yellow dual-color high-brightness device with a 20mA operating current, 3.3V power supply, and IP65 protection rating to withstand dust and low-pressure water spray. The brightness reaches 2000mcd, ensuring visibility in harsh environments. The temperature sensor I²C bus is equipped with a 4.7kΩ pull-up resistor, and the 0.2mm line width and 0.2mm spacing wiring is kept away from high-speed signal lines. It is equipped with a 3.3V LDO regulator to ensure signal stability. The voltage monitoring chip uses 1206 packaged metal film resistors for voltage division, which are placed close to the power input terminal, and the line voltage drop is <50mV. The buzzer drive circuit has a 1kΩ current-limiting resistor in series with the base to ensure that the transistor operates in the saturation region. The LED drive circuit has a 220Ω current-limiting resistor to control the current fluctuation within ±5%. In functional testing, the temperature sensor, calibrated in a constant temperature chamber, exhibited an error ≤ ±0.3℃ within the range of -40℃ to 85℃; the adjustable power supply simulated voltage fluctuations, with an overvoltage / undervoltage response time <200μs; upon alarm command triggering, the buzzer sounded within 0.5ms, and the LED warning light illuminated within 1ms. Reliability testing showed that the module passed 1000 hours of high-temperature storage at 125℃, 1000 cycles of temperature cycling from -40℃ to 85℃, and 20g triaxial vibration testing, with no component detachment and parameter drift <1%; electromagnetic compatibility testing met the CISPR 22 Class B standard, with radiated emissions ≤40dBμV / m, immunity ≥20V / m, and a mean time between failures (MTBF) exceeding 150,000 hours. This solution, through ±0.5℃ high-precision temperature measurement, 10μs-level voltage fluctuation response, and IP65 protection design, improves fault detection speed by 3 times and enhances environmental adaptability by 50% compared to traditional alarm solutions. Non-contact temperature monitoring avoids the aging problems of contact sensors, dual threshold alarms cover more than 95% of abnormal system scenarios, and an 85dB buzzer and a 2000mcd warning light ensure the reliability of human-machine interaction, effectively improving the system's fault early warning capability and operation and maintenance efficiency.

[0068] Furthermore, the 7-inch OLED touchscreen of the display module 8 adopts On-Cell touch technology, with a resolution of 1920×1200, a pixel density of 326PPI, supports 10-finger touch, is covered with Gorilla Glass, has an anti-glare coating, a brightness adjustment range of 100-800 nits, a refresh rate of 60Hz, and a color gamut coverage of DCI-P3 98%.

[0069] In a specific embodiment, the 7-inch OLED touchscreen employs On-Cell touch technology, with a resolution of 1920×1200 (2K level), a pixel density of 326 PPI, and supports 10-point touch. It connects directly to the ARM chip via a MIPI-DSI interface, and a 2.5Gbps / lane transmission rate ensures that a frame of 1080P image data is transmitted within 16ms. The AMOLED self-emissive panel achieves an ultra-high contrast ratio of 100,000:1, 50 times higher than traditional LCDs. Combined with a DCI-P3 98% wide color gamut and a 60Hz refresh rate, the dynamic image response time is ≤1ms, and the color reproduction error is <1.5ΔE. The screen is covered with 0.55mm thick Gorilla Glass, and the anti-glare coating ensures a reflectivity of <5% and a light transmittance of ≥90%. The automatic brightness adjustment range of 100-800 nits adapts to ambient temperatures from -40℃ to 85℃, and the ambient light sensor response time is <200ms. The touch module employs capacitive technology, offering ±2mm touch accuracy and <8ms response time. It supports glove operation and wet hand recognition, achieving 100% accuracy for simultaneous 10-finger touch recognition. The MIPI-DSI signal line utilizes a 15-pin differential microstrip line, with a transmission loss of <2dB within 150mm of FPC cabling. Combined with dual LDO voltage regulators, it ensures a data transmission error rate of <1e-11. The touch signal shielding layer is grounded, achieving a crosstalk suppression ratio >30dB. A 0.2mm gap between the power and ground layers controls the power impedance below 50mΩ, ensuring signal stability under high-frequency drive. The module is integrated into the system's front panel and connects to the motherboard via a 30AWG FPC cable. Its ultra-thin 1.2mm package meets miniaturization requirements. In functional testing, the text edge jaggedness rate at 2K resolution was <0.1%, 10-finger touch showed no frame drops, and automatic brightness adjustment adapted within 200ms to sudden changes in ambient light. Reliability testing showed that after 1000 cycles of temperature cycling from -40℃ to 85℃, 20g triaxial vibration, and 1 million touch durability tests, the screen had no bright or dark spots, touch coordinate drift was <0.5mm, and brightness decay was <5%. Electromagnetic compatibility testing met CISPR 22 Class B standards, with radiated emissions ≤35dBμV / m and immunity ≥25V / m. The technical solution achieves professional-grade color performance through an ultra-high contrast ratio of 100000:1 and a 98% DCI-P3 wide color gamut. Anti-glare and wide brightness range design improves visibility in strong light environments by 40%, and ±2mm touch accuracy and <8ms response time meet the precise operation requirements of industrial control. On-Cell technology reduces the thickness by 30% compared to external touch solutions. Its glass and IP65 protection can withstand dust, low-pressure water spray, and impact from a drop of 1 meter. With a lifespan of 1 million touch cycles and an MTBF of 150,000 hours, it offers twice the reliability of similar solutions, making it a highly efficient human-computer interaction core module that balances display performance, user experience, and environmental adaptability.

[0070] In summary, the graphics processing system based on an embedded dual-core ARM chip of this invention achieves fast, efficient, and stable graphics processing by using an embedded dual-core ARM chip and combining various functional modules. It also has good scalability and can meet the graphics processing needs of different fields.

[0071] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A graphics processing system based on an embedded dual-core ARM chip, characterized in that, include: The embedded dual-core ARM chip circuit consists of an ARM Cortex-A53 main core (101) and an ARM Cortex-M7 (102) co-core. The main core is responsible for graphics rendering, and the co-core is responsible for system control and real-time signal processing. The two cores are interconnected through a high-speed parallel bus and integrated on a PCB substrate. The graphics input module (2) is equipped with a multi-source signal synchronization circuit and supports HDMI, VGA and USB input interfaces. The signals of each interface are uniformly converted into LVDS signals by a level conversion chip and then input to the dual-core ARM chip. The graphics processing module (3) is a combination of FPGA hardware and dual-core ARM chip. The FPGA has a built-in hardware acceleration unit for real-time image edge detection and color space conversion. The graphics storage module (4) uses LPDDR4 memory chips and NAND Flash, and is integrated on the system motherboard through multi-layer stacking packaging technology, with a storage bandwidth of 16GB / s; The graphics output module (5) integrates a DisplayPort 1.4 output interface and is equipped with an LVDS to DisplayPort conversion circuit, supporting 4K@60Hz resolution output; The data interaction module (6) expands the external device connection capability based on the PCIe 3.0 interface and is equipped with physical isolation circuit to prevent signal crosstalk; The alarm module (7) consists of a temperature sensor and a voltage monitoring chip. When the system temperature exceeds 85°C or the power supply voltage fluctuates by more than ±5%, it triggers a buzzer and an LED warning light. The display module (8) has a built-in 7-inch OLED touch screen, which is directly connected to the dual-core ARM chip through the MIPI-DSI interface and supports real-time status monitoring and interactive operation. The output terminal of the graphics input module (2) is connected to the input terminal of the embedded dual-core ARM chip circuit. The output terminal of the main core in the embedded dual-core ARM chip circuit is connected to the input terminal of the graphics processing module (3). The output terminal of the graphics processing module (3) is connected to the input terminal of the graphics storage module (4). The output terminal of the graphics storage module (4) is connected to the input terminal of the graphics output module (5). The output terminal of the co-core in the embedded dual-core ARM chip circuit (1) is connected to the input terminals of the data interaction module (6) and the alarm module (7). The input terminal of the display module (8) is connected to the output terminals of the main core and the co-core in the embedded dual-core ARM chip circuit, respectively.

2. The graphics processing system based on an embedded dual-core ARM chip as described in claim 1, characterized in that: The embedded dual-core ARM chip circuit integrates a hardware watchdog timer, supporting independent monitoring of both cores. When a deadlock occurs in the main core or co-core, it can trigger a system reset. The reset signal is transmitted through a dedicated wiring layer to ensure anti-interference capability. The high-speed parallel bus adopts a 128-bit bidirectional data transmission design, supporting communication bandwidth of up to 2GB / s between ARM Cortex-A53 and ARM Cortex-M7 cores. The bus protocol adopts the AXI4 standard.

3. The graphics processing system based on an embedded dual-core ARM chip control according to claim 1, characterized in that: The FPGA hardware acceleration unit includes a configurable logic block (CLB) array, supports dynamic reconfiguration technology, and can switch between image edge detection and color space conversion functions according to the processing task requirements. The multi-layer stacked packaging technology adopts a through-silicon via (TSV) three-dimensional integration process, with LPDDR4 chips stacked on top of NAND Flash and vertical interconnection achieved through micro-bumps. The package thickness does not exceed 1.2mm.

4. The graphics processing system based on an embedded dual-core ARM chip as described in claim 1, characterized in that: The graphics input module (2) includes an HDMI receiver chip (201), a VGA analog-to-digital converter circuit (202), and a USB 3.0 controller (203). Each interface signal is converted into an LVDS signal by a level conversion chip and then input to the LVDS receiver interface of the dual-core ARM chip circuit (1) through an FPC cable. The level conversion chip of the graphics input module (2) supports the HDCP2.2 content protection protocol, the HDMI interface supports 4K@30Hz input, the VGA interface supports 1920×1080@60Hz input, and the USB interface conforms to the USB3.1 Gen1 standard.

5. A graphics processing system based on an embedded dual-core ARM chip as described in claim 1, characterized in that: The graphics storage module (4) uses 3D TLC NAND Flash with a capacity of 128GB; the LPDDR4 memory chip has a capacity of 4GB, an operating voltage of 1.1V, and supports data self-refresh function.

6. A graphics processing system based on an embedded dual-core ARM chip as described in claim 1, characterized in that: The graphics output module (5) integrates a DisplayPort 1.4 transmitting chip and an LVDS to DisplayPort conversion circuit. It receives the LVDS signal output by the dual-core ARM chip circuit (1), processes it, and transmits it to the DisplayPort interface through a coaxial cable. It supports 4K@60Hz resolution output. The conversion circuit integrates a jitter elimination unit and adopts Spread Spectrum Clocking technology. The signal jitter is controlled within 0.15UI and the conversion delay is <2ms.

7. A graphics processing system based on an embedded dual-core ARM chip as described in claim 1, characterized in that: The data interaction module (6) has a PCIe 3.0 interface with 4 independent channels, each with a transmission rate of 8GT / s. The physical isolation circuit adopts a combination design of electromagnetic shield and common mode choke, with an isolation of >60dB@1GHz.

8. A graphics processing system based on an embedded dual-core ARM chip as described in claim 1, characterized in that: The alarm module (7) includes a temperature sensor (701), a voltage monitoring chip (702), a buzzer (703), and an LED warning light (704). The temperature sensor (701) is located inside the system and monitors the system temperature. The voltage monitoring chip (702) is located on the PCB substrate and monitors the power supply voltage. The buzzer (703) is located on the front panel of the system and is used for sound alarm. The LED warning light (704) is located on the front panel of the system, adopts IP65 protection level, and supports red / yellow dual-color warning.

9. A graphics processing system based on an embedded dual-core ARM chip as described in claim 1, characterized in that: The 7-inch OLED touch screen of the display module (8) adopts On-Cell touch technology, with a resolution of 1920×1200, a pixel density of 326PPI, supports 10-finger touch, is covered with Gorilla Glass, has an anti-glare coating, a brightness adjustment range of 100-800 nits, a refresh rate of 60Hz, and a color gamut coverage of DCI-P3 98%.

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