Goa driving unit, goa driving circuit and display device
By introducing a capacitive coupling mechanism into the inverting module, the problem of poor pull-down sustaining effect in the GOA driver unit is solved, the level sustaining capability of the pull-down control node is improved, the effect of the pull-down sustaining module is enhanced, and the stability and reliability of the GOA driver unit are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- ZHEJIANG LAIBAO DISPLAY TECHNOLOGY CO LTD
- Filing Date
- 2025-05-30
- Publication Date
- 2026-05-29
AI Technical Summary
The existing pull-down sustaining module in the GOA driver unit has poor pull-down sustaining effect, mainly because the transistor channel width-to-height ratio used to access the preset high-level signal in the inverting module is small, resulting in insufficient level of the intermediate sustaining node and the pull-down control node, which affects the pull-down sustaining effect.
A first capacitor is connected between the intermediate sustain node and the pull-down control node of the inverting module. Through the principle of capacitive coupling, the level of the intermediate sustain node and the pull-down control node is increased, thereby enhancing the pull-down sustaining effect of the pull-down sustaining module.
Capacitive coupling improves the level maintenance capability of the pull-down control node, enhances the pull-down maintenance effect of the pull-down maintenance module, and improves the stability and reliability of the GOA driver unit.
Smart Images
Figure CN224304336U_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of display technology, and in particular relates to a GOA driving unit, a GOA driving circuit and a display device. Background Technology
[0002] Integrating gate driver on array (GOA) circuitry onto a glass substrate involves integrating the gate driver circuitry of the display panel onto the glass substrate, forming a scanning drive for the display panel. Compared to traditional gate chip-based driving technologies, GOA driving technology can significantly reduce manufacturing costs and reduce the left and right bezels of the display panel. A GOA driving circuit typically includes cascaded multi-stage GOA driving units. Each stage of the GOA driving unit drives one row of pixel units on the display panel. By cascading multiple stages of GOA driving units, line-by-line scanning of the display panel can be achieved.
[0003] The pull-down sustaining effect of the pull-down sustaining module in the GOA driver unit typically depends on the level of the high-level pull-down control signal output by the inverting module. However, because the channel width-to-height ratio of the transistor used to access the preset high-level signal in the existing inverting module is small, the high level output by this transistor to the intermediate sustaining node is relatively low. This results in a low level of the high-level pull-down control signal output by the transistor controlled by the intermediate sustaining node, thus leading to poor pull-down sustaining effect of the pull-down sustaining module. Summary of the Invention
[0004] In view of this, embodiments of this application provide a GOA driving unit, a GOA driving circuit, and a display device to solve the technical problem of poor pull-down sustaining effect of the pull-down sustaining module in the existing GOA driving unit.
[0005] In a first aspect, embodiments of this application provide a GOA driving unit, including:
[0006] A pull-up control module, connected to a pull-up control node, is used to output a pull-up control signal to the pull-up control node based on a first input signal;
[0007] A pull-up module, connected to the pull-up control node and the output node, is used to output a gate drive signal from the output node according to the pull-up control signal and the scan clock signal;
[0008] A pull-down module, connected to the pull-up control node, is used to pull the pull-up control node down to a low level according to a high-level second input signal;
[0009] An inverting module, connected to the pull-up control node and the pull-down control node, is used to invert the pull-up control signal according to a preset high-level signal and output the inverted signal of the pull-up control signal to the pull-down control node; a first capacitor is connected between the intermediate sustaining node in the inverting module and the pull-down control node, and the first capacitor is used to maintain the level of the high-level inverted signal at the level of the preset high-level signal;
[0010] A pull-down sustaining module, connected to the pull-up control node, the pull-down control node, and the output node, is used to maintain the pull-up control node and the output node at a low level according to the high-level inverted signal;
[0011] A reset module, connected to the pull-up control node and the output node, is used to pull the pull-up control node and the output node down to a low level according to a high-level reset signal.
[0012] In one alternative implementation of the first aspect, the pull-up control module includes a first transistor;
[0013] The gate and source of the first transistor are used to receive the first input signal, and the drain of the first transistor is connected to the pull-up control node.
[0014] In one alternative implementation of the first aspect, the pull-up module includes a second transistor and a second capacitor;
[0015] The gate of the second transistor and the first terminal of the second capacitor are both connected to the pull-up control node, the source of the second transistor is used to connect to the scan clock signal, and the drain of the second transistor and the second terminal of the second capacitor are both connected to the output node.
[0016] In one alternative implementation of the first aspect, the pull-down module includes a third transistor;
[0017] The gate of the third transistor is used to receive the second input signal, the source of the third transistor is connected to the pull-up control node, and the drain of the third transistor is connected to the low-level terminal.
[0018] In one optional implementation of the first aspect, the inverting module includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and the first capacitor; the sixth transistor is the output stage pull-up transistor in the inverting module.
[0019] The gate, source, and source of the fourth transistor are used to connect to the preset high-level signal. The drain, source, and gate of the fourth transistor are connected to the first terminal of the first capacitor. The gate of the fifth transistor and the gate of the seventh transistor are connected to the pull-up control node. The drain of the sixth transistor, the second terminal of the first capacitor, and the source of the seventh transistor are connected to the pull-down control node. The drains of the fifth transistor and the seventh transistor are connected to the low-level terminal.
[0020] In one alternative implementation of the first aspect, the pull-down sustaining module includes an eighth transistor and a ninth transistor;
[0021] The gate of the eighth transistor and the gate of the ninth transistor are both connected to the pull-down control node. The source of the eighth transistor is connected to the pull-up control node. The source of the ninth transistor is connected to the output node. The drains of the eighth transistor and the drains of the ninth transistor are connected to a low-level terminal.
[0022] In one alternative implementation of the first aspect, the reset module includes a tenth transistor and an eleventh transistor;
[0023] The source of the tenth transistor is connected to the pull-up control node, the source of the eleventh transistor is connected to the output node, the gates of the tenth and eleventh transistors are used to receive the reset signal, and the drains of the tenth and eleventh transistors are connected to a low-level terminal.
[0024] In one optional implementation of the first aspect, the inverting module includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, the first capacitor, and a twelfth transistor; the sixth transistor is the output stage pull-up transistor in the inverting module.
[0025] The gate, source, and source of the fourth transistor are used to connect to the preset high-level signal. The drain, gate, source, and gate of the twelfth transistor are all connected to the first terminal of the first capacitor. The drain of the twelfth transistor is connected to the source of the fifth transistor. The gate of the fifth transistor and the gate of the seventh transistor are all connected to the pull-up control node. The drain of the sixth transistor, the second terminal of the first capacitor, and the source of the seventh transistor are all connected to the pull-down control node. The drains of the fifth transistor and the seventh transistor are connected to the low-level terminal.
[0026] Secondly, embodiments of this application provide a GOA driving circuit, including cascaded multi-stage GOA driving units as described in any optional implementation of the first aspect; the first input signal connected to each stage of the GOA driving unit is the gate driving signal output by the upper k-stage GOA driving unit, and the second input signal connected to each stage of the GOA driving unit is the gate driving signal output by the lower j-stage GOA driving unit; k and j are positive integers.
[0027] Thirdly, embodiments of this application provide a display device including the GOA driving circuit described in the second aspect.
[0028] Implementing the GOA driving unit, GOA driving circuit, and display device provided in the embodiments of this application has the following beneficial effects:
[0029] The GOA driving unit provided in this application embodiment connects a first capacitor between the intermediate sustaining node and the pull-down control node of the inverting module. When the intermediate sustaining node is at a high level, it can not only pull the pull-down control node up to the level of a preset high-level signal, but also charge the first capacitor, causing the level across the first capacitor to rise. Due to the capacitive coupling principle, while the level of the pull-down control node is pulled up to the level of the preset high-level signal, the level of the intermediate sustaining node will continue to rise, thereby maintaining the level of the pull-down control node at the level of the preset high-level signal, thus improving the pull-down sustaining effect of the pull-down sustaining module connected to the pull-down control node. Attached Figure Description
[0030] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0031] Figure 1 A schematic diagram of the structure of a GOA driving unit provided for the prior art;
[0032] Figure 2 This is a schematic diagram of the structure of a GOA driving unit provided in an embodiment of this application;
[0033] Figure 3 A schematic diagram of the circuit structure of a GOA driving unit provided in an embodiment of this application;
[0034] Figure 4 A waveform diagram of each node and the access signal when a GOA driving unit is working normally, provided for an embodiment of this application;
[0035] Figure 5 This is a schematic diagram of the circuit structure of a GOA driving unit provided in another embodiment of this application. Detailed Implementation
[0036] The following embodiments are only used to illustrate the technical solutions of this application more clearly, and are therefore only examples and should not be used to limit the scope of protection of this application.
[0037] In the description of the embodiments of this application, the technical terms "comprising," "including," "having," and any variations thereof all mean "including but not limited to," unless otherwise specifically emphasized. In the description of the embodiments of this application, unless otherwise stated, the technical term "multiple" refers to two or more, and the technical terms "at least one" or "one or more" refer to one, two, or more than two. The technical terms "first," "second," etc., are only used to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary / secondary relationship of the indicated technical features. The technical term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.
[0038] This application first provides a GOA driving circuit, which may include cascaded multi-level GOA driving units. Each level of GOA driving unit can be used to drive a row of pixels on the display panel. The cascading of multiple levels of GOA driving units enables line-by-line scanning of the display panel.
[0039] To facilitate understanding, we will first explain some of the structure and working principle of the existing GOA unit.
[0040] For example, please refer to Figure 1 This is a schematic diagram of the structure of a GOA driving unit provided by existing technology. Figure 1 As shown, the inverting module in the existing GOA driving unit typically includes transistors T51, T52, T53, and T54. These four transistors form an inverter, which is used to invert the pull-up control signal at the pull-up control node Qn under the control of a preset high-level signal VGH, and output the inverted signal of the pull-up control signal to the pull-down control node Kn, so that the pull-down maintenance module maintains both the pull-up control node Qn and the output node Rn at a low level according to the inverted high-level signal.
[0041] However, due to the small channel width-to-length ratio (W / L) of transistor T51, the high level of the intermediate sustaining node Sn is not high enough, resulting in a low high level of the pull-down control node Kn (less than the preset high level signal VGH). This leads to a small current when transistors T42 and T32 in the pull-down sustaining module are turned on, reducing the pull-down sustaining effect of the pull-down sustaining module.
[0042] In view of this, embodiments of this application also provide a GOA driving unit. Please refer to... Figure 2 This is a schematic diagram of the structure of a GOA driving unit provided in an embodiment of this application. Figure 2 As shown, the GOA driver unit may include a pull-up control module 10, a pull-up module 20, a pull-down module 30, an inverting module 40, a pull-down sustaining module 50, and a reset module 60. Wherein:
[0043] The pull-up control module 10 can be connected to the pull-up control node Qn. The pull-up control module 10 can be used to receive a first input signal G(nk) and output a pull-up control signal to the pull-up control node Qn according to the first input signal G(nk). For example, the pull-up control module 10 can be used to output a high-level pull-up control signal to the pull-up control node Qn according to the high-level first input signal G(nk).
[0044] Pull-up module 20 can be connected to pull-up control node Qn. Pull-up module 20 can be used to receive scan clock signal CLK, and output gate drive signal G(n) from output node Rn according to pull-up control signal and scan clock signal CLK. For example, pull-up control module 20 can output high-level gate drive signal G(n) from output node Rn according to high-level pull-up control signal and high-level scan clock signal CLK. Gate drive signal G(n) can be used to drive a row of pixel units corresponding to the current GOA driving unit, or it can be used as an input signal for other GOA driving units.
[0045] The pull-down module 30 can be connected to the pull-up control node Qn. The pull-down module 30 can be used to receive a second input signal G(n+j) and, based on the second input signal G(n+j), to pull down the pull-up control node Qn. For example, the pull-down module 30 can pull the pull-up control node Qn down to a low level VSS based on the high-level second input signal G(n+j).
[0046] The inverting module 40 can be connected to the pull-up control node Qn and the pull-down control node Kn. The inverting module 40 can be used to receive a preset high-level signal VGH, invert the pull-up control signal according to the preset high-level signal VGH, and output the inverted pull-up control signal to the pull-down control node Kn. For example, the inverting module 40 can invert a high-level pull-up control signal into a low-level inverted signal according to the preset high-level signal VGH; or it can invert a low-level pull-up control signal into a high-level inverted signal according to the preset high-level signal VGH.
[0047] In addition, a first capacitor C1 can be connected between the intermediate sustaining node Sn and the pull-down control node Kn in the inverting module 40. The first capacitor C1 can be used to maintain the level of the high-level inverted signal at the level of the preset high-level signal VGH.
[0048] The pull-down sustaining module 50 can be connected to the pull-up control node Qn, the pull-down control node Kn, and the output node Rn. The pull-down sustaining module 50 can be used to maintain the pull-up control node Qn and the output node Rn at a low level VSS based on an inverted high signal. For example, the pull-down sustaining module 50 can maintain the pull-up control node Qn and the output node Rn at a low level VSS based on an inverted high-level signal.
[0049] The reset module 60 can be connected to the pull-up control node Qn and the output node Rn. The reset module 60 can be used to reset the pull-up control node Qn and the output node Rn according to the reset signal Reset. For example, the reset module 60 can pull down the pull-up control node Qn and the output node Rn to a low level VSS according to the high-level reset signal Reset.
[0050] Wherein, the first input signal G(nk) can be the gate drive signal output by the k-th stage GOA drive unit, and the second input signal G(n+j) can be the gate drive signal output by the j-th stage GOA drive unit, where k and j are positive integers. k and j can be determined according to the number of cycles of the scan clock signal connected to the pull-up module 20. For example, k can be 3 and j can be 4.
[0051] As can be seen from the above, by connecting a first capacitor between the intermediate sustaining node and the pull-down control node of the inverting module, when the intermediate sustaining node is at a high level, it can not only pull the pull-down control node up to the level of a preset high-level signal, but also charge the first capacitor, causing the level across the first capacitor to rise. Due to the capacitive coupling principle, while the level of the pull-down control node is pulled up to the level of the preset high-level signal, the level of the intermediate sustaining node will continue to rise, thereby maintaining the level of the pull-down control node at the level of the preset high-level signal, thus improving the pull-down sustaining effect of the pull-down sustaining module connected to the pull-down control node.
[0052] Please see Figure 3 This is a schematic diagram of the circuit structure of a GOA driving unit provided in an embodiment of this application. For ease of explanation, only the parts related to the embodiment of this application are shown, and are described in detail below:
[0053] like Figure 3 As shown, the pull-up control module 10 may include a first transistor T1. The gate and source of the first transistor T1 can be used to connect to the first input signal G(nk), and the drain of the first transistor T1 can be connected to the pull-up control node Qn.
[0054] The pull-up module 20 may include a second transistor T2 and a second capacitor C2. The gate of the second transistor T2 and the first terminal of the second capacitor C2 can be connected to the pull-up control node Qn, the source of the second transistor T2 can be used to connect to the scan clock signal CLK, and the drain of the second transistor T2 and the second terminal of the second capacitor C2 can be connected to the output node Rn. For example, the second capacitor C2 may be a bootstrap capacitor.
[0055] The pull-down module 30 may include a third transistor T3. The gate of the third transistor T3 can be used to connect to the second input signal G(n+j), the source of the third transistor T3 can be connected to the pull-up control node Qn, and the drain of the third transistor T3 can be connected to a low-level terminal. The low-level terminal is used to provide a low level VSS.
[0056] In one optional implementation, the inverter module 40 may include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a first capacitor C1. The gate and source of the fourth transistor T4 and the source of the sixth transistor T6 can be connected to a preset high-level signal VGH. The drain of the fourth transistor T4, the source of the fifth transistor T5, and the gate of the sixth transistor T6 can be connected to the first terminal of the first capacitor C1. The gate of the fifth transistor T5 and the gate of the seventh transistor T7 can be connected to the pull-up control node Qn. The drain of the sixth transistor T6, the second terminal of the first capacitor C1, and the source of the seventh transistor T7 can be connected to the pull-down control node Kn. The drain of the fifth transistor T5 and the drain of the seventh transistor T7 can be connected to a low-level terminal.
[0057] The pull-down sustaining module 50 may include an eighth transistor T8 and a ninth transistor T9. The gate of the eighth transistor T8 and the gate of the ninth transistor T9 may be connected to the pull-down control node Kn, the source of the eighth transistor T8 may be connected to the pull-up control node Qn, the source of the ninth transistor T9 may be connected to the output node Rn, and the drain of the eighth transistor T8 and the drain of the ninth transistor T9 may be connected to a low-level terminal.
[0058] The reset module 60 may include a tenth transistor T10 and an eleventh transistor T11. The source of the tenth transistor T10 may be connected to the pull-up control node Qn, and the source of the eleventh transistor T11 may be connected to the output node Rn. The gates of the tenth transistor T10 and the eleventh transistor T11 may be used to receive the reset signal Reset, and the drains of the tenth transistor T10 and the eleventh transistor T11 may be connected to a low-level terminal.
[0059] The following combination Figure 4 ,right Figure 2 and Figure 3 The working principle of the GOA driver unit in the document will be explained in detail. Please refer to [link / reference]. Figure 4 This is a waveform diagram of each node and the access signal when a GOA driving unit is working normally, provided in an embodiment of this application.
[0060] like Figure 4As shown, during stage A to B, the first input signal G(nk) is high, while the scan clock signal CLK, the second input signal G(n+j), and the reset signal Reset are all low. At this time, the first transistor T1 in the pull-up control module 10 is turned on, outputting a high-level pull-up control signal to the pull-up control node Qn, thereby pulling the pull-up control node Qn high to the first high level. Since the pull-up control node Qn is high at this time, the second transistor T2 in the pull-up module 20 is turned on, transmitting the low-level scan clock signal CLK to the output node Rn, making the output node Rn low; and at this time, the pull-up control node Qn charges the second capacitor C2, raising the level across the second capacitor C2. Since the second input signal G(n+j) is low, the third transistor T3 in the pull-down module 30 is turned off, thus putting the pull-down module 30 in the off state. In the inverting module 40, the fourth transistor T4 is normally open under the action of the preset high-level signal VGH, making the intermediate sustaining node Sn high, thereby controlling the sixth transistor T6 to conduct. However, since the pull-up control node Qn is high, the fifth transistor T5 and the seventh transistor T7 are also conducting, thus pulling down both the intermediate sustaining node Sn and the pull-down control node Kn to a low level VSS. That is, the inverting module 40 inverts the high-level pull-up control signal to a low level and outputs it to the pull-down control node Kn, while the sixth transistor T6 is immediately turned off after a brief conduction. Since the pull-down control node Kn is low, the eighth transistor T8 and the ninth transistor T9 in the pull-down sustaining module 50 are both turned off, thus putting the pull-down sustaining module 50 in the off state. Since the reset signal Reset is low, the tenth transistor T10 and the eleventh transistor T11 in the reset module 60 are both turned off, thus putting the reset module 60 in the off state.
[0061] During stages B to C, the scan clock signal CLK is high, and both the first input signal G(nk) and the second input signal G(n+j) are low. At this time, although the first transistor T1 in the pull-up control module 10 is off, the second capacitor C2 in the pull-up module 20 is charged during stages A to B. Therefore, the stored energy in the second capacitor C2 will cause the pull-up control node to be at a second high level, and will turn on the second transistor T2, thereby transmitting the high-level scan clock signal CLK to the output node Rn, causing the output node Rn to output a high-level gate drive signal G(n). Since the second input signal G(n+j) is low, the third transistor T3 in the pull-down module 30 is off, thus putting the pull-down module 30 in a closed state. The fourth transistor T4 in the inverter module 40 is normally open under the action of the preset high-level signal VGH, causing the intermediate sustaining node Sn to be high, thereby controlling the sixth transistor T6 to turn on. Simultaneously, the preset high-level signal VGH will charge the first capacitor C1. Since the pull-up control node Qn is at the second high level, both the fifth transistor T5 and the seventh transistor T7 are turned on, thus slowly pulling down the intermediate sustaining node Sn and the pull-down control node Kn to a low level VSS. At this time, the eighth transistor T8 and the ninth transistor T9 in the pull-down sustaining module 50 are turned off, thereby maintaining the pull-up control node Qn at the second high level. Since the reset signal Reset is at a low level, both the tenth transistor T10 and the eleventh transistor T11 in the reset module 60 are turned off, thereby putting the reset module 60 in the off state.
[0062] During stages C to D, the scan clock signal CLK, the first input signal G(nk), and the second input signal G(n+j) are all at low levels. At this time, the energy stored in the second capacitor C2 keeps the pull-up control node Qn at the first high level and turns on the second transistor T2, thereby transmitting the low-level scan clock signal CLK to the output node Rn, making the output node Rn low. Since the second input signal G(n+j) is low, the third transistor T3 in the pull-down module 30 is turned off, thus putting the pull-down module 30 in the off state. The fourth transistor T4 in the inverter module 40 is normally open under the action of the preset high-level signal VGH, making the intermediate sustaining node Sn high, thereby controlling the sixth transistor T6 to turn on. Simultaneously, the preset high-level signal VGH charges the first capacitor C1. Because the pull-up control node Qn is at the first high level, both the fifth transistor T5 and the seventh transistor T7 are turned on, thus slowly pulling down the intermediate sustaining node Sn and the pull-down control node Kn to the low level VSS. At this time, the eighth transistor T8 and the ninth transistor T9 in the pull-down sustaining module 50 are both turned off, thereby keeping the pull-up control node Qn at the first high level. Since the reset signal Reset is at a low level, the tenth transistor T10 and the eleventh transistor T11 in the reset module 60 are both turned off, thereby keeping the reset module 60 in the off state.
[0063] During stages D to E, the second input signal G(n+j) is high, while the first input signal G(nk), the scan clock signal CLK, and the reset signal Reset are all low. At this time, the third transistor T3 in the pull-down module 30 is turned on, pulling the pull-up control node Qn down to a low level VSS. The fourth transistor T4 in the inverter module 40 is normally open under the influence of the preset high-level signal VGH, making the intermediate sustaining node Sn high, thereby controlling the sixth transistor T6 to turn on, making the pull-down control node Kn also high. Since the pull-up control node Qn is low (VSS), the fifth transistor T5 and the seventh transistor T7 are turned off, maintaining both the intermediate sustaining node Sn and the pull-down control node Kn at a high level. However, because the channel width-to-height ratio (W / L) of the fourth transistor T4 is relatively small, in the case that the first capacitor C1 is not provided in the inverter module 40 of the existing GOA drive unit, the high level of the intermediate sustaining node Sn is low, resulting in a low high level of the pull-down control node Kn (less than the level of the preset high-level signal VGH, e.g., ...). Figure 4The waveforms of the intermediate sustain node Sn and the pull-down control node Kn are shown by dashed lines, which reduces the current when the eighth transistor T8 and the ninth transistor T9 in the pull-down sustain module 50 are turned on, thus reducing the pull-down sustaining effect of the pull-down sustain module 50. Since a first capacitor C1 is connected between the intermediate sustain node Sn and the pull-down control node Kn in this embodiment, the preset high-level signal VGH charges the first capacitor C1, raising the voltage level across C1. Because the sixth transistor T6 is in the on state, based on the capacitive coupling principle, the voltage level of the intermediate sustain node Sn continuously increases as the voltage level of the pull-down control node Kn increases, thereby increasing the voltage difference Vgs between the gate and source of the sixth transistor T6. At this time, the voltage level of the pull-down control node Kn is close to the high level of the preset high-level signal VGH (e.g., ...). Figure 4 (The solid lines in the waveforms of the intermediate sustaining node Sn and the pull-down control node Kn are shown in the diagram). Based on this, the eighth transistor T8 and the ninth transistor T9 in the pull-down sustaining module 50 are turned on, thereby stably maintaining the level of the pull-up control node Qn and the level of the output node Rn at a low level VSS, improving the pull-down sustaining effect.
[0064] During stages F to G, the reset signal Reset is high, while the first input signal G(nk), the second input signal G(n+j), and the scan clock signal CLK are all low. At this time, the tenth transistor T10 and the eleventh transistor T11 in the reset module 60 are both turned on, thereby pulling down and resetting the pull-up control node Qn and the output node Rn to a low level VSS, thus keeping the gate drive signal G(n) low.
[0065] In practical applications, because the load on the intermediate sustaining node Sn is relatively small, connecting the first capacitor C1 solely between the intermediate sustaining node Sn and the pull-down control node Kn will couple the voltage level of the intermediate sustaining node Sn to a very high level (e.g., 40 volts (V)) by the pull-down control node Kn. This results in a very high voltage difference Vds between the drain and source of the fifth transistor T5, making it prone to breakdown and causing the entire circuit to fail. To solve this technical problem, embodiments of this application also provide a GOA driving unit.
[0066] Please see Figure 5 This is a schematic diagram of the circuit structure of a GOA driving unit according to another embodiment of this application. For ease of explanation, only the parts related to the embodiment of this application are shown.
[0067] like Figure 5 As shown, with Figure 3Compared to the corresponding embodiments, the inverting module 40 in the GOA driving unit provided in this embodiment, in addition to including four transistors T4, five transistors T5, six transistors T6, seven transistors T7 and the first capacitor C1, may also include a twelfth transistor T12.
[0068] In this configuration, the gate and source of the fourth transistor T4, as well as the source of the sixth transistor T6, can be connected to a preset high-level signal VGH. The drain of the fourth transistor T4, the gate of the sixth transistor T6, the source of the twelfth transistor T12, and the gate of the twelfth transistor T12 are all connected to the first terminal of the first capacitor C1. The drain of the twelfth transistor T12 is connected to the source of the fifth transistor T5. The gate of the fifth transistor T5 and the gate of the seventh transistor T7 are all connected to the pull-up control node Qn. The drain of the sixth transistor T6, the second terminal of the first capacitor C1, and the source of the seventh transistor T7 are all connected to the pull-down control node Kn. The drain of the fifth transistor T5 and the drain of the seventh transistor T7 are connected to the low-level terminal.
[0069] It should be noted that the structure and connection relationships of other modules in the GOA driver unit provided in this embodiment are different from those of the GOA driver unit provided in this embodiment. Figure 2 The corresponding embodiments are the same; for details regarding the structure and connection relationships of other modules, please refer to [reference needed]. Figure 2 The relevant descriptions in the corresponding embodiments will not be repeated here.
[0070] Since the gate and source of the twelfth transistor T12 are both connected to the intermediate sustaining node Sn, and the drain of the twelfth transistor T12 is connected to the fifth transistor T5, the twelfth transistor T12 will divide the voltage level of the intermediate sustaining node Sn, thereby restoring the voltage level of the intermediate sustaining node Sn to the normal high level (e.g., 20V), thereby reducing the risk of the fifth transistor T5 being damaged and improving the stability of the circuit operation.
[0071] This application also provides a display device, which includes the above-described GOA driving circuit.
[0072] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units is merely an example. In practical applications, the above functions can be assigned to different functional units as needed, that is, the internal structure of the GOA driver circuit can be divided into different functional units to complete all or part of the functions described above. Furthermore, the specific names of each functional unit are only for easy differentiation and are not intended to limit the scope of protection of this application.
[0073] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, refer to the relevant descriptions of other embodiments.
[0074] It should be noted that, unless otherwise specified, all technical terms used in the embodiments of this application have the same meaning as commonly understood by those skilled in the art to which this application belongs. The technical terms used in the embodiments of this application are only used to explain specific embodiments of this application and are not intended to limit this application.
[0075] The term "embodiment" as used in the description of embodiments in this application means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0076] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0077] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A GOA driving unit, characterized in that, include: A pull-up control module, connected to a pull-up control node, is used to output a pull-up control signal to the pull-up control node based on a first input signal; A pull-up module, connected to the pull-up control node and the output node, is used to output a gate drive signal from the output node according to the pull-up control signal and the scan clock signal; A pull-down module, connected to the pull-up control node, is used to pull the pull-up control node down to a low level according to a high-level second input signal; An inverting module, connected to the pull-up control node and the pull-down control node, is used to invert the pull-up control signal according to a preset high-level signal and output the inverted signal of the pull-up control signal to the pull-down control node; a first capacitor is connected between the intermediate sustaining node in the inverting module and the pull-down control node, and the first capacitor is used to maintain the level of the high-level inverted signal at the level of the preset high-level signal; A pull-down sustaining module, connected to the pull-up control node, the pull-down control node, and the output node, is used to maintain the pull-up control node and the output node at a low level according to the high-level inverted signal; A reset module, connected to the pull-up control node and the output node, is used to pull the pull-up control node and the output node down to a low level according to a high-level reset signal.
2. The GOA driving unit according to claim 1, characterized in that, The pull-up control module includes a first transistor; The gate and source of the first transistor are used to receive the first input signal, and the drain of the first transistor is connected to the pull-up control node.
3. The GOA driving unit according to claim 1, characterized in that, The pull-up module includes a second transistor and a second capacitor; The gate of the second transistor and the first terminal of the second capacitor are both connected to the pull-up control node, the source of the second transistor is used to connect to the scan clock signal, and the drain of the second transistor and the second terminal of the second capacitor are both connected to the output node.
4. The GOA driving unit according to claim 1, characterized in that, The pull-down module includes a third transistor; The gate of the third transistor is used to receive the second input signal, the source of the third transistor is connected to the pull-up control node, and the drain of the third transistor is connected to the low-level terminal.
5. The GOA driving unit according to claim 1, characterized in that, The inverting module includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and the first capacitor; the sixth transistor is the output stage pull-up transistor in the inverting module. The gate, source, and source of the fourth transistor are used to connect to the preset high-level signal. The drain, source, and gate of the fourth transistor are connected to the first terminal of the first capacitor. The gate of the fifth transistor and the gate of the seventh transistor are connected to the pull-up control node. The drain of the sixth transistor, the second terminal of the first capacitor, and the source of the seventh transistor are connected to the pull-down control node. The drains of the fifth transistor and the seventh transistor are connected to the low-level terminal.
6. The GOA driving unit according to claim 1, characterized in that, The pull-down sustaining module includes an eighth transistor and a ninth transistor; The gate of the eighth transistor and the gate of the ninth transistor are both connected to the pull-down control node. The source of the eighth transistor is connected to the pull-up control node. The source of the ninth transistor is connected to the output node. The drains of the eighth transistor and the drains of the ninth transistor are connected to a low-level terminal.
7. The GOA driving unit according to claim 1, characterized in that, The reset module includes a tenth transistor and an eleventh transistor; The source of the tenth transistor is connected to the pull-up control node, the source of the eleventh transistor is connected to the output node, the gates of the tenth and eleventh transistors are used to receive the reset signal, and the drains of the tenth and eleventh transistors are connected to a low-level terminal.
8. The GOA driving unit according to claim 1, characterized in that, The inverting module includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, the first capacitor, and a twelfth transistor; The gate, source, and source of the fourth transistor are used to connect to the preset high-level signal. The drain, gate, source, and gate of the twelfth transistor are all connected to the first terminal of the first capacitor. The drain of the twelfth transistor is connected to the source of the fifth transistor. The gate of the fifth transistor and the gate of the seventh transistor are all connected to the pull-up control node. The drain of the sixth transistor, the second terminal of the first capacitor, and the source of the seventh transistor are all connected to the pull-down control node. The drains of the fifth transistor and the seventh transistor are connected to the low-level terminal.
9. A GOA driving circuit, characterized in that, The system includes cascaded multi-stage GOA driving units as described in any one of claims 1-8; the first input signal of each stage of the GOA driving unit is the gate driving signal output by the upper k-stage GOA driving unit, and the second input signal of each stage of the GOA driving unit is the gate driving signal output by the lower j-stage GOA driving unit; k and j are positive integers.
10. A display device, characterized in that, Includes the GOA driving circuit as described in claim 9.