A semiconductor device

Abstract

The utility model discloses a semiconductor device, wherein, the semiconductor device includes: substrate, channel layer, barrier layer, first gate structure and second gate structure, interval is located barrier layer far from the one side of substrate, first passivation layer, first passivation layer includes first opening, and first opening is located between first gate structure and second gate structure, and first opening exposes barrier layer, and the surface of the barrier layer exposed by first opening far from substrate is doped with electronegative atom, and the electronegativity of electronegative atom is greater than or equal to the electronegativity of oxygen atom, second passivation layer, located first passivation layer far from the one side of substrate and fill first opening, first electrode, located first gate structure far from the one side of first opening, second electrode, located second gate structure far from the one side of first opening. The utility model realizes the lower leakage current of gate structure at the same time, and improves the concentration and mobility of two-dimensional electron gas of device.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Technology

[0002] For existing gallium nitride (GaN) high electron mobility transistors (HEMTs), the surface of the barrier layer and the surface of the gate structure are covered by the same passivation layer. That is, the drift region of the GaN HEMT device away from the substrate is covered by the same passivation layer as the surface of the gate structure. The setting of the same passivation layer cannot simultaneously meet the requirements of high concentration, high mobility of two-dimensional electron gas and effective protection of the gate structure. Utility Model Content

[0003] This invention provides a semiconductor device to solve the problem that current passivation layer settings cannot simultaneously meet the requirements of high concentration and high mobility of two-dimensional electron gas and effective protection of the gate structure.

[0004] In a first aspect, the present invention provides a semiconductor device, wherein the semiconductor device comprises:

[0005] Substrate;

[0006] A channel layer is located on one side of the substrate;

[0007] A barrier layer is located on the side of the channel layer away from the substrate;

[0008] A first gate structure and a second gate structure are spaced apart on the side of the barrier layer away from the substrate.

[0009] A first passivation layer is located on the side of the first gate structure, the second gate structure, and the barrier layer away from the substrate; the first passivation layer includes a first sub-passivation layer and a second sub-passivation layer, the first passivation layer includes a first opening located between the first gate structure and the second gate structure, the first opening exposing the barrier layer; the side of the barrier layer exposed by the first opening away from the substrate includes an electronegative atom doped layer, the electronegativity of the electronegative atoms being greater than or equal to the electronegativity of oxygen atoms;

[0010] The second passivation layer is located on the side of the first passivation layer away from the substrate and fills the first opening. The second passivation layer includes a third sub-passivation layer and a fourth sub-passivation layer.

[0011] A first gate field plate and a second gate field plate are located on the side of the second passivation layer away from the substrate. The vertical projection of the first gate field plate onto the substrate covers the vertical projection of the first gate structure onto the substrate. The vertical projection of the second gate field plate onto the substrate covers the vertical projection of the second gate structure onto the substrate.

[0012] The first electrode is located on the side of the first gate structure away from the first opening;

[0013] The second electrode is located on the side of the second gate structure away from the first opening.

[0014] Optionally, the first passivation layer further includes a second opening and a third opening; the second opening is located on the side of the first gate structure away from the first opening, and the third opening is located on the side of the second gate structure away from the first opening; the second opening and the third opening expose the barrier layer, and the side of the barrier layer exposed by the second opening and the third opening away from the substrate includes an electronegative atom doped layer, wherein the electronegativity of the electronegative atoms is greater than or equal to the electronegativity of the oxygen atoms;

[0015] The second passivation layer fills the second opening and the third opening.

[0016] Optionally, the first sub-passivation layer is located on the side of the first gate structure, the second gate structure, and the barrier layer away from the substrate; the second sub-passivation layer is located on the side of the first sub-passivation layer away from the substrate; the third sub-passivation layer is located on the side of the first passivation layer away from the substrate, and the third sub-passivation layer fills the first opening; the fourth sub-passivation layer is located on the side of the third sub-passivation layer away from the substrate; and the thickness of the third sub-passivation layer is less than the thickness of the first sub-passivation layer.

[0017] Optionally, the thickness of the first sub-passivation layer is 5nm-100nm, and the thickness of the third sub-passivation layer is 0.5nm-5nm.

[0018] Optionally, the first sub-passivation layer includes a first aluminum nitride layer, and the third sub-passivation layer includes a second aluminum nitride layer.

[0019] Optionally, the second sub-passivation layer includes a first silicon nitride layer, a first silicon oxide layer, and / or a first silicon oxynitride layer, and the fourth sub-passivation layer includes a second silicon nitride layer, a second silicon oxide layer, and / or a second silicon oxynitride layer.

[0020] Optionally, the electronegative atom doped layer includes an oxygen atom doped layer and / or a fluorine atom doped layer.

[0021] Optionally, the cross-sectional shape of the first opening is a symmetrical shape along the center line of the semiconductor device, and the first gate field plate and the second gate field plate are symmetrical along the center line of the semiconductor device; the distance between the vertical projection of the first gate structure on the substrate and the vertical projection of the first opening on the substrate and the distance between the vertical projection of the second gate structure on the substrate and the vertical projection of the first opening on the substrate are equal; the first gate structure and the second gate structure are the same gate structure.

[0022] The distance between the vertical projection of the first electrode on the substrate and the vertical projection of the first gate structure on the substrate is the same as the distance between the vertical projection of the second electrode on the substrate and the vertical projection of the second gate structure on the substrate; both the first electrode and the second electrode are in contact with the barrier layer.

[0023] Optionally, the opening size of the second opening is the same as the opening size of the third opening; the distance between the vertical projection of the second opening on the substrate and the vertical projection of the first electrode on the substrate is equal to the distance between the vertical projection of the third opening on the substrate and the vertical projection of the second electrode on the substrate; the distance between the vertical projection of the second opening on the substrate and the vertical projection of the first gate structure on the substrate is equal to the distance between the vertical projection of the third opening on the substrate and the vertical projection of the second gate structure on the substrate.

[0024] Optionally, the vertical projection of the first gate field plate on the substrate does not overlap with the vertical projection of the first opening on the substrate, and the vertical projection of the first gate field plate on the substrate does not overlap with the vertical projection of the second opening on the substrate; or, the vertical projection of the first gate field plate on the substrate at least partially overlaps with the vertical projection of the first opening on the substrate, and the vertical projection of the first gate field plate on the substrate at least partially overlaps with the vertical projection of the second opening on the substrate.

[0025] The vertical projection of the second gate field plate onto the substrate does not overlap with the vertical projection of the first opening onto the substrate, and the vertical projection of the second gate field plate onto the substrate does not overlap with the vertical projection of the third opening onto the substrate; or, the vertical projection of the second gate field plate onto the substrate at least partially overlaps with the vertical projection of the first opening onto the substrate, and the vertical projection of the second gate field plate onto the substrate at least partially overlaps with the vertical projection of the third opening onto the substrate.

[0026] Optionally, the first passivation layer includes a fourth opening and a fifth opening, and the second passivation layer includes a sixth opening and a seventh opening;

[0027] The fourth opening is located on the side of the first gate structure away from the first opening, and the vertical projection of the sixth opening onto the substrate coincides with the vertical projection of the fourth opening onto the substrate; the first electrode is located within the fourth opening and the sixth opening;

[0028] The fifth opening is located on the side of the second gate structure away from the first opening, and the vertical projection of the seventh opening onto the substrate coincides with the vertical projection of the fifth opening onto the substrate; the second electrode is located within the fifth opening and the seventh opening.

[0029] Optionally, the first gate structure includes a first III-V semiconductor layer and a first gate; the second gate structure includes a second III-V semiconductor layer and a second gate.

[0030] The first III-V semiconductor layer is located on the side of the barrier layer away from the substrate, and the first gate is located on the side of the first III-V semiconductor layer away from the substrate; the second III-V semiconductor layer is located on the side of the barrier layer away from the substrate, and the second gate is located on the side of the second III-V semiconductor layer away from the substrate.

[0031] In this embodiment of the invention, the first passivation layer can be located on the side of the first gate structure and the second gate structure away from the substrate. The thickness of the first sub-passivation layer can be relatively thick, resulting in better electric field shielding. This makes the first passivation layer, composed of the first and second sub-passivation layers, more effective in passivating and protecting the first and second gate structures, thereby reducing leakage current in the first and second gate structures. Furthermore, the first and second sub-passivation layers cover the entire first and second gate structures, thus preventing damage to the regions of the first and second gate structures from plasma, such as oxygen or fluorine, when electronegative atoms are doped onto the surface of the barrier layer at the first opening away from the substrate to form an electronegative atom doped layer. The first passivation layer may include a first opening. When the surface of the barrier layer away from the substrate is doped with electronegative atoms to form an electronegative atom doped layer, since the electronegativity of the doped electronegative atoms is greater than or equal to that of oxygen atoms (i.e., the doped electronegative atoms have strong oxidizing properties), the surface of the barrier layer is oxidized and the interface is improved during the doping process. This improves the surface states of the barrier layer in the drift region, increases the concentration of the two-dimensional electron gas in the drift region, and thus enhances the performance of the power device. The second passivation layer is located on the side of the first passivation layer away from the substrate and fills the first opening. The second passivation layer, which is in direct contact with the barrier layer within the first opening, can effectively enhance the stress in the drift region of the GaN HEMT device, thereby increasing the concentration and mobility of the two-dimensional electron gas, reducing the on-resistance of the GaN HEMT device, and improving the dynamic performance of the GaN HEMT device. The technical solution of this utility model embodiment can achieve separate modulation of the first gate structure, the second gate structure and the device drift region through the first passivation layer and the second passivation layer. While achieving low leakage current of the first gate structure and the second gate structure, it can improve the concentration and mobility of the two-dimensional electron gas of the device, thereby effectively improving the device performance.

[0032] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this utility model, nor is it intended to limit the scope of this utility model. Other features of this utility model will become readily apparent from the following description. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0035] Figure 2 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0036] Figures 3-9 This is a schematic diagram of the structure corresponding to some steps in the method for fabricating a semiconductor device provided in this embodiment of the utility model;

[0037] Figure 10 This is a flowchart of another method for fabricating a semiconductor device provided in this embodiment of the present invention;

[0038] Figures 11-12 This is a schematic diagram of some steps in another method for fabricating a semiconductor device provided in this embodiment of the present invention.

[0039] Figure 13 This is a flowchart of another method for fabricating a semiconductor device provided in this embodiment of the present invention;

[0040] Figure 14 This is a flowchart of another method for fabricating a semiconductor device provided in this embodiment of the present invention. Detailed Implementation

[0041] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0042] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0043] Figure 1This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this utility model, as shown below. Figure 1 As shown, the semiconductor device includes: a substrate 1, a channel layer 2 located on one side of the substrate 1, and a barrier layer 3 located on the side of the channel layer 2 away from the substrate 1. A first gate structure 4 and a second gate structure 5 are spaced apart and located on the side of the barrier layer 3 away from the substrate 1. A first passivation layer 6 includes a first sub-passivation layer 61 and a second sub-passivation layer 62. The first sub-passivation layer 61 is located on the side of the first gate structure 4, the second gate structure 5, and the barrier layer 3 away from the substrate 1, and the second sub-passivation layer 62 is located on the side of the first sub-passivation layer 61 away from the substrate 1. The first passivation layer 6 includes a first opening 63 located between the first gate structure 4 and the second gate structure 5, exposing the barrier layer 3. The surface of the barrier layer 3 exposed by the first opening 63 away from the substrate 1 is doped with electronegative atoms, the electronegativity of which is greater than or equal to that of oxygen atoms. The second passivation layer 7 includes a third sub-passivation layer 71 and a fourth sub-passivation layer 72. The third sub-passivation layer 71 is located on the side of the first passivation layer 6 away from the substrate 1 and fills the first opening 63. The fourth sub-passivation layer 72 is located on the side of the third sub-passivation layer 71 away from the substrate 1. The first electrode 81 is located on the side of the first gate structure 4 away from the first opening 63. The second electrode 82 is located on the side of the second gate structure 5 away from the first opening 63.

[0044] Specifically, substrate 1 can be a Si substrate, a sapphire substrate, or a GaN substrate. Channel layer 2 can be intrinsic GaN, and barrier layer 3 can be AlGaN. First gate structure 4 can be located on the side of barrier layer 3 away from substrate 1, and second gate structure 5 can also be located on the side of barrier layer 3 away from substrate 1. First gate structure 4 and second gate structure 5 are spaced apart, and can be a completely symmetrical structure along the centerline of the GaN HEMT device, i.e., first gate structure 4 and second gate structure 5 can be symmetrically spaced along the centerline of the GaN HEMT device. First gate structure 4 can include a first doped III-V semiconductor layer 41 and a first gate 42. The first doped III-V semiconductor layer 41 can be located on the side of barrier layer 3 away from substrate 1, and the first gate 42 can be located on the side of the first doped III-V semiconductor layer 41 away from substrate 1. The second gate structure 5 may include a second-doped III-V semiconductor layer 51 and a second gate 52. The second-doped III-V semiconductor layer 51 may be located on the side of the barrier layer 3 away from the substrate 1, and the second gate 52 may be located on the side of the second-doped III-V semiconductor layer 51 away from the substrate 1. Both the first-doped III-V semiconductor layer 41 and the second-doped III-V semiconductor layer 51 may include a P-GaN layer, and both the first gate 42 and the second gate 52 may include a titanium nitride metal layer.

[0045] The first passivation layer 6 may include a first sub-passivation layer 61 and a second sub-passivation layer 62. The first sub-passivation layer 61 may be located on the side of the first gate structure 4 and the second gate structure 5 away from the substrate 1. The first sub-passivation layer 61 may also be located on the side of the barrier layer 3 away from the substrate 1. The second sub-passivation layer 62 may be located on the side of the first sub-passivation layer 61 away from the substrate 1. The first passivation layer 6 may completely surround the first gate structure 4 and the second gate structure 5. The first passivation layer 6 is mainly used for passivation and protection of the first gate structure 4 and the second gate structure 5. The thickness of the first sub-passivation layer 61 can be relatively thick, resulting in better electric field shielding. This enhances the passivation protection effect of the first passivation layer 6, composed of the first sub-passivation layer 61 and the second sub-passivation layer 62, on the first gate structure 4 and the second gate structure 5, thereby reducing leakage current in both structures. Furthermore, the first and second sub-passivation layers 61 and 62 cover the entire first gate structure 4 and the entire second gate structure 5. This prevents damage to the regions of the first gate structure 4 and the second gate structure 5 from plasma, such as oxygen or fluorine, when electronegative atoms are doped onto the surface of the barrier layer 3 away from the substrate 1 at the first opening 63 to form an electronegative atom doped layer. The opening size of the first opening 63 can be set according to actual conditions. A certain distance can be set between the edge of the first opening 63 near the first gate structure 4 and the first gate structure 4, and a certain distance can also be set between the edge of the first opening 63 near the second gate structure 5 and the second gate structure 5. The first passivation layer 6 between the edge of the first opening 63 near the first gate structure 4 and the first gate structure 4 can completely surround the first gate structure 4, effectively passivating and protecting the first gate structure 4. Similarly, the first passivation layer 6 between the edge of the first opening 63 near the second gate structure 5 and the second gate structure 5 can completely surround the second gate structure 5, effectively passivating and protecting the second gate structure 5.

[0046] Experiments revealed that when electronegative atoms are doped onto the surface of the barrier layer 3 exposed by the first opening 63, away from the substrate 1, to form an electronegative atom doped layer, the electronegativity of the doped electronegative atoms is greater than or equal to that of oxygen atoms, meaning these doped electronegative atoms have strong oxidizing properties. During the doping process of these electronegative atoms on the surface of the barrier layer 3 to form the electronegative atom doped layer, the surface is oxidized and the interface is improved. This improves the surface states of the barrier layer 3 in the drift region, increases the concentration of two-dimensional electron gas in the drift region, and thus enhances the performance of the power device. The larger the opening size of the first opening 63, the better the effect on improving the concentration and mobility of the two-dimensional electron gas in the drift region.

[0047] The second passivation layer 7 may include a third sub-passivation layer 71 and a fourth sub-passivation layer 72. The third sub-passivation layer 71 may be located on the side of the second sub-passivation layer 62 away from the substrate 1, and the third sub-passivation layer 71 may fill the first opening 63, covering the barrier layer 3 exposed by the first opening 63. The fourth sub-passivation layer 72 may be located on the side of the third sub-passivation layer 71 away from the substrate 1. The thickness of the third sub-passivation layer 71 may be less than the thickness of the first sub-passivation layer 61. The second passivation layer 7, which is in direct contact with the barrier layer 3 within the first opening 63, can effectively enhance the stress in the drift region of the GaN HEMT device, thereby increasing the concentration and mobility of the two-dimensional electron gas in the GaN HEMT device, reducing the on-resistance of the GaN HEMT device, and improving the dynamic performance of the GaNHEMT device. The larger the opening size of the first opening 63, the larger the contact area between the second passivation layer 7 and the barrier layer 3, and the higher the concentration and mobility of the two-dimensional electron gas in the GaN HEMT device can be.

[0048] The GaN HEMT device provided in this embodiment can have a completely symmetrical structure. The first electrode 81 can be used as either the source or the drain, and the second electrode 82 can be used as either the drain or the source.

[0049] In this embodiment of the present invention, the first passivation layer 6 can be located on the side of the first gate structure 4 and the second gate structure 5 away from the substrate 1. The thickness of the first sub-passivation layer 61 can be relatively thick, resulting in better electric field shielding capability. This makes the first passivation layer 6, composed of the first sub-passivation layer 61 and the second sub-passivation layer 62, provide better passivation protection for the first gate structure 4 and the second gate structure 5, thereby reducing leakage current in the first gate structure 4 and the second gate structure 5. Furthermore, the first sub-passivation layer 61 and the second sub-passivation layer 62 cover the entire first gate structure 4 and the entire second gate structure 5. This avoids damage to the region of the first gate structure 4 and the second gate structure 5 by plasma such as oxygen or fluorine gas when electronegative atoms are doped onto the surface of the barrier layer 3 at the first opening 63 away from the substrate 1 to form an electronegative atom doped layer. The first passivation layer 6 may include a first opening 63. When the surface of the barrier layer 3 exposed by the first opening 63 away from the substrate 1 is doped with electronegative atoms to form an electronegative atom doped layer, since the electronegativity of the doped electronegative atoms is greater than or equal to that of oxygen atoms, i.e., the doped electronegative atoms have strong oxidizing properties, the surface of the barrier layer 3 is oxidized and the interface is improved during the doping process of the electronegative atoms. This can improve the surface states of the barrier layer 3 in the drift region, increase the concentration of two-dimensional electron gas in the drift region, and thus improve the performance of the power device. The second passivation layer 7 is located on the side of the first passivation layer 6 away from the substrate 1 and fills the first opening 63. This allows the second passivation layer 6, which is in direct contact with the barrier layer 3 within the first opening 63, to effectively enhance the stress in the drift region of the GaN HEMT device, thereby increasing the concentration and mobility of the two-dimensional electron gas in the GaN HEMT device, reducing the on-resistance of the GaN HEMT device, and improving the dynamic performance of the GaN HEMT device. The technical solution of this utility model embodiment can achieve separate modulation of the first gate structure 4, the second gate structure 5 and the device drift region through the first passivation layer 6 and the second passivation layer 7. While achieving low leakage current of the first gate structure 4 and the second gate structure 5, it can improve the concentration and mobility of the two-dimensional electron gas of the device, thereby effectively improving the device performance.

[0050] Optionally, based on the above embodiments, refer to... Figure 1 The first passivation layer 6 further includes a second opening 64 and a third opening 65. The second opening 64 is located on the side of the first gate structure 4 away from the first opening 63, and the third opening 65 is located on the side of the second gate structure 5 away from the first opening 63. The second opening 64 and the third opening 65 expose the barrier layer 3. The surface of the barrier layer 3 exposed by the second opening 64 and the third opening 65 away from the substrate 1 is doped with electronegative atoms, the electronegativity of which is greater than or equal to that of oxygen atoms. The second passivation layer 7 fills the second opening 64 and the third opening 65.

[0051] Specifically, a certain distance can be set between the edge of the second opening 64 near the first gate structure 4 and the first gate structure 4 to ensure that the first passivation layer 6 between the edge of the second opening 64 near the first gate structure 4 and the first gate structure 4 can completely surround the first gate structure 4, effectively passivating and protecting the first gate structure 4. The edge of the second opening 64 away from the first gate structure 4 can be located between the first gate structure 4 and the first electrode 81. The edge of the second opening 64 away from the first gate structure 4 can also extend to the area of ​​the first electrode 81, and can also extend to the area of ​​the first electrode 81 away from the first gate structure 4.

[0052] A certain distance can be provided between the edge of the third opening 65 near the second gate structure 5 and the second gate structure 5 to ensure that the first passivation layer 6 between the edge of the third opening 65 near the second gate structure 5 and the second gate structure 5 can completely surround the second gate structure 5, effectively passivating and protecting the second gate structure 5. The edge of the third opening 65 away from the second gate structure 5 can be located between the second gate structure 5 and the second electrode 82. The edge of the third opening 65 away from the second gate structure 5 can also extend to the area of ​​the second electrode 82, and can also extend to the area of ​​the second electrode 82 away from the second gate structure 5.

[0053] When the surface of the barrier layer 3 exposed by the second opening 64 and the third opening 65, away from the substrate 1, is doped with electronegative atoms to form an electronegative atom doped layer, the electronegativity of the doped electronegative atoms is greater than or equal to that of oxygen atoms, meaning that these doped electronegative atoms have strong oxidizing properties. During the doping process of these electronegative atoms on the surface of the barrier layer 3, oxidation and interface improvement are performed, which can improve the surface states of the barrier layer 3 in the drift region, increase the concentration of two-dimensional electron gas in the drift region, and thus improve the performance of the power device. The larger the opening size of the second opening 64 and the third opening 65, the better the effect on improving the concentration and mobility of two-dimensional electron gas in the drift region.

[0054] The third sub-passivation layer 71 can be located on the side of the second sub-passivation layer 62 away from the substrate 1, and the third sub-passivation layer 71 can fill the first opening 63, the second opening 64, and the third opening 65, covering the barrier layer 3 exposed by the first opening 63, the second opening 64, and the third opening 65. The fourth sub-passivation layer 72 can be located on the side of the third sub-passivation layer 71 away from the substrate 1. The thickness of the third sub-passivation layer 71 can be less than the thickness of the first sub-passivation layer 61. The second passivation layer 7, which is in direct contact with the barrier layer 3 in the first opening 63, the second opening 64, and the third opening 65, can effectively enhance the stress in the drift region of the GaN HEMT device, thereby increasing the concentration and mobility of the two-dimensional electron gas in the GaN HEMT device, reducing the on-resistance of the GaN HEMT device, and improving the dynamic performance of the GaN HEMT device. The larger the opening size of the first opening 63, the second opening 64 and the third opening 65, the larger the contact area between the second passivation layer 7 and the barrier layer 3 will be, and the concentration and mobility of the two-dimensional electron gas of the GaN HEMT device can be further improved.

[0055] Optionally, based on the above embodiments, refer to... Figure 1 The thickness of the third sub-passivation layer 71 is less than the thickness of the first sub-passivation layer 61.

[0056] Specifically, the thickness of the first sub-passivation layer 61 can be relatively thick, resulting in better electric field shielding. This makes the first passivation layer 6, composed of the first sub-passivation layer 61 and the second sub-passivation layer 62, more effective in passivating and protecting the first gate structure 4 and the second gate structure 5, thereby reducing leakage current in the first gate structure 4 and the second gate structure 5. Furthermore, the first sub-passivation layer 61 and the second sub-passivation layer 62 cover the entire first gate structure 4 and the entire second gate structure 5. This avoids damage to the regions of the first gate structure 4 and the second gate structure 5 caused by plasma, such as oxygen or fluorine, when electronegative atoms are doped onto the surface of the barrier layer 3 away from the substrate 1 at the first opening 63, the second opening 64, and the third opening 65 to form an electronegative atom doped layer. The thickness of the third sub-passivation layer 71 can be less than the thickness of the first sub-passivation layer 61. The second passivation layer 7, which is in direct contact with the barrier layer 3 in the first opening 63, the second opening 64 and the third opening 65, can effectively enhance the stress in the drift region of the GaN HEMT device, thereby increasing the concentration and mobility of the two-dimensional electron gas in the GaN HEMT device, reducing the on-resistance of the GaN HEMT device and improving the dynamic performance of the GaN HEMT device.

[0057] In this embodiment of the invention, the thickness and other parameters of the first sub-passivation layer 61 and the third sub-passivation layer 71 are different, which is mainly achieved by adjusting the process temperature, gas ratio and pretreatment of the first sub-passivation layer 61 and the third sub-passivation layer 71.

[0058] Optionally, based on the above embodiments, refer to... Figure 1 The first sub-passivation layer 61 includes a first aluminum nitride layer, and the second sub-passivation layer 71 includes a second aluminum nitride layer.

[0059] Specifically, the materials of the first sub-passivation layer 61 and the third sub-passivation layer 71 can both be aluminum nitride. In some embodiments of this utility model, the materials of the first passivation layer 61 and the second passivation layer 71 can also be aluminum oxide, etc.

[0060] Optionally, based on the above embodiments, refer to... Figure 1 The materials of the second sub-passivation layer 62 and the fourth sub-passivation layer 72 can be set to at least one of silicon nitride, silicon oxide and silicon oxynitride.

[0061] Optionally, based on the above embodiments, refer to... Figure 1 Electronegative atoms include at least one of oxygen atoms and fluorine atoms.

[0062] Specifically, in this embodiment of the GaN HEMT device, after forming the first gate structure 4 and the second gate structure 5, a first passivation layer 6 is formed on the side of the first gate structure 4 and the second gate structure 5 away from the substrate 1 and on the side of the barrier layer 3 away from the substrate 1. Then, the drift region of the GaN HEMT device is selectively opened through photolithography and etching processes, forming the first opening 63, the second opening 64, and the third opening 65. Oxygen and / or fluorine gas are then introduced into the surface of the barrier layer 3 of the exposed drift region through the first opening 63, the second opening 64, and the third opening 65 to perform interface enhancement treatment. That is, the side of the barrier layer 3 exposed by the first opening 63, the second opening 64, and the third opening 65 away from the substrate 1 is surface-doped with electronegative atoms to form an electronegative atom doped layer. Since the electronegativity of electronegative atoms is relatively strong, it can improve the surface states of the barrier layer 3, increase the concentration and mobility of the two-dimensional electron gas in the drift region, and thus improve the performance of the device.

[0063] Optionally, based on the above embodiments, refer to... Figure 1The cross-sectional shape of the first opening 63 is symmetrical along the centerline of the semiconductor device. The distance between the vertical projection of the first gate structure 4 onto the substrate 1 and the vertical projection of the first opening 63 onto the substrate 1, and the distance between the vertical projection of the second gate structure 5 onto the substrate 1 and the vertical projection of the first opening 63 onto the substrate 1, are equal. The first gate structure 4 and the second gate structure 5 are identical gate structures. The distance between the vertical projection of the first electrode 81 onto the substrate 1 and the vertical projection of the first gate structure 4 onto the substrate 1, and the distance between the vertical projection of the second electrode 82 onto the substrate 1 and the vertical projection of the second gate structure 5 onto the substrate 1, are equal. Both the first electrode 81 and the second electrode 82 are in contact with the barrier layer.

[0064] Specifically, the cross-sectional shape of the first opening 63 is symmetrical along the centerline of the semiconductor device. The first gate structure 4 and the second gate structure 5 can be symmetrically spaced along the centerline of the GaN HEMT device. The first electrode 81 and the second electrode 82 can also be symmetrically arranged along the centerline of the GaN HEMT device. This allows the GaN HEMT device to have a completely symmetrical structure, where the first electrode 81 can serve as either the source or the drain, and the second electrode 82 can serve as either the drain or the source.

[0065] Optionally, based on the above embodiments, refer to... Figure 1 The opening size of the second opening 64 is the same as the opening size of the third opening 65. The distance between the vertical projection of the second opening 64 onto the substrate 1 and the vertical projection of the first electrode 81 onto the substrate 1 is equal to the distance between the vertical projection of the third opening 65 onto the substrate 1 and the vertical projection of the second electrode 82 onto the substrate 1. The distance between the vertical projection of the second opening 64 onto the substrate 1 and the vertical projection of the first gate structure 4 onto the substrate 1 is equal to the distance between the vertical projection of the third opening 65 onto the substrate 1 and the vertical projection of the second gate structure 5 onto the substrate 1.

[0066] Specifically, when the first passivation layer 6, in addition to the first opening 63, also has a second opening 64 and a third opening 65, the cross-sectional pattern of the first opening 63 is symmetrical along the centerline of the semiconductor device. The first gate structure 4 and the second gate structure 5 can be symmetrically spaced along the centerline of the GaN HEMT device. The second opening 64 and the third opening 65 can also be symmetrically arranged along the centerline of the GaN HEMT device. The first electrode 81 and the second electrode 82 can also be symmetrically arranged along the centerline of the GaN HEMT device. This allows the GaN HEMT device to have a completely symmetrical structure.

[0067] The first passivation layer 6 may also have a fourth opening 66 and a fifth opening 67, and the second passivation layer 7 may also have a sixth opening 73 and a seventh opening 74. The fourth opening 66 may be located on the side of the second opening 64 away from the first gate structure 4, and the vertical projection of the sixth opening 73 onto the substrate 1 may coincide with the vertical projection of the fourth opening 66 onto the substrate 1. The fifth opening 67 may be located on the side of the third opening 65 away from the second gate structure 5, and the vertical projection of the seventh opening 74 onto the substrate 1 may coincide with the vertical projection of the fifth opening 67 onto the substrate 1. The first electrode 81 is located within the fourth opening 66 and the sixth opening 73 and is in contact with the barrier layer 3, and the second electrode 82 is located within the fifth opening 67 and the seventh opening 74 and is in contact with the barrier layer 3.

[0068] Optionally, based on the above embodiments, refer to... Figure 1 The thickness of the first sub-passivation layer 61 is 5nm-100nm, and the thickness of the third sub-passivation layer 71 is 0.5nm-5nm.

[0069] Specifically, the thickness of the third sub-passivation layer 71 can be less than the thickness of the first sub-passivation layer 61. For example, the thickness of the first sub-passivation layer 61 can be 5nm-100nm, and the thickness of the third sub-passivation layer 71 can be 0.5nm-5nm. By forming the first sub-passivation layer 61 and the third sub-passivation layer 71 separately and setting the thicknesses of the first sub-passivation layer 61 and the third sub-passivation layer 71 to be different, the first passivation layer 6 can effectively passivate and protect the first gate structure 4 and the second gate structure 5. The second passivation layer 7, which is in direct contact with the barrier layer 3 in the first opening 63, the second opening 64, and the third opening 65, can effectively enhance the stress in the drift region of the GaN HEMT device, thereby improving the concentration and mobility of the two-dimensional electron gas in the GaN HEMT device.

[0070] Optionally, based on the above embodiments, refer to... Figure 1The semiconductor device may further include a first gate field plate 91 and a second gate field plate 92. Both the first gate field plate 91 and the second gate field plate 92 may be located on the side of the fourth sub-passivation layer 72 away from the substrate 1. The centerline of the first gate field plate 91 may coincide with the centerline of the first gate structure 4. The vertical projection of the first gate field plate 91 onto the substrate 1 may cover the vertical projection of the first gate structure 4 onto the substrate 1. The vertical projection of the first gate field plate 91 onto the substrate 1 may not overlap with the vertical projections of the first opening 63 and the second opening 64 onto the substrate 1. The first gate field plate 91 may also extend along the direction of the first gate structure 4 pointing to the first opening 63, such that the vertical projection of the first gate field plate 91 onto the substrate 1 may at least partially overlap with the vertical projection of the first opening 63 onto the substrate 1. The first gate field plate 91 may also extend along the direction of the first gate structure 4 pointing to the second opening 64, such that the vertical projection of the first gate field plate 91 onto the substrate 1 may at least partially overlap with the vertical projection of the second opening 64 onto the substrate 1.

[0071] The centerline of the second gate field plate 92 can coincide with the centerline of the second gate structure 5, and the vertical projection of the second gate field plate 92 onto the substrate 1 can cover the vertical projection of the second gate structure 5 onto the substrate 1. The vertical projection of the second gate field plate 92 onto the substrate 1 can not overlap with the vertical projections of the first opening 63 and the third opening 65 onto the substrate 1. Alternatively, the second gate field plate 92 can extend along the direction of the second gate structure 4 pointing to the first opening 63, such that the vertical projection of the second gate field plate 92 onto the substrate 1 can at least partially overlap with the vertical projection of the first opening 63 onto the substrate 1. The second gate field plate 92 can also extend along the direction of the second gate structure 5 pointing to the third opening 65, such that the vertical projection of the second gate field plate 92 onto the substrate 1 can at least partially overlap with the vertical projection of the third opening 65 onto the substrate 1.

[0072] The first gate field plate 91 and the second gate field plate 92 can both be made of metallic materials. The first gate field plate 91 and the second gate field plate 92 can be used for electric field modulation to avoid electric field concentration between the first gate structure 4 and the first electrode 81 or the second gate structure 5 and the second electrode 82, thereby improving the breakdown voltage of the device.

[0073] Figure 2 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention. Figures 3-9 This is a schematic diagram of the structure corresponding to some steps in the method for fabricating a semiconductor device provided in this embodiment of the utility model, as shown below. Figure 2 As shown, the preparation method includes:

[0074] S100: Provides a substrate.

[0075] Specifically, such as Figure 3As shown, a substrate 1 is first provided, which can be a Si substrate, a sapphire substrate or a GaN substrate.

[0076] S110: A channel layer and a barrier layer are formed sequentially on one side of the substrate.

[0077] Specifically, such as Figure 4 As shown, a channel layer 2 is first formed on one side of the substrate 1, and a barrier layer 3 is formed on the side of the channel layer 2 away from the substrate 1. The channel layer 2 can be made of intrinsic GaN, and the barrier layer 3 can be made of AlGaN material.

[0078] S120: A first gate structure and a second gate structure are formed at intervals on the side of the barrier layer away from the substrate.

[0079] Specifically, such as Figure 5 As shown, a first gate structure 4 and a second gate structure 5 are formed at intervals on the side of the barrier layer 3 away from the substrate 1. The first gate structure 4 and the second gate structure 5 can be a completely symmetrical structure along the centerline of the GaN HEMT device, that is, the first gate structure 4 and the second gate structure 5 can be symmetrically spaced along the centerline of the GaN HEMT device. The first gate structure 4 may include a first doped III-V semiconductor layer 41 and a first gate 42. The first doped III-V semiconductor layer 41 may be located on the side of the barrier layer 3 away from the substrate 1, and the first gate 42 may be located on the side of the first doped III-V semiconductor layer 41 away from the substrate 1. The second gate structure 5 may include a second doped III-V semiconductor layer 51 and a second gate 52. The second doped III-V semiconductor layer 51 may be located on the side of the barrier layer 3 away from the substrate 1, and the second gate 52 may be located on the side of the second doped III-V semiconductor layer 51 away from the substrate 1. Both the first doped III-V semiconductor layer 41 and the second doped III-V semiconductor layer 51 may include a P-GaN layer, and both the first gate 42 and the second gate 52 may include a titanium nitride metal layer.

[0080] For example, a doped III-V semiconductor layer can be formed on the side of the barrier layer 3 away from the substrate 1, and a gate can be formed on the side of the doped III-V semiconductor layer away from the substrate 1. Then, the first gate structure 4 and the second gate structure 5 can be formed by photolithography and etching processes.

[0081] S130: A first passivation layer is formed on the side of the first gate structure, the second gate structure, and the barrier layer away from the substrate. The first passivation layer includes a first sub-passivation layer and a second sub-passivation layer.

[0082] Specifically, such as Figure 6As shown, a first passivation layer 6 is formed on the side of the first gate structure 4, the second gate structure 5, and the barrier layer 3 away from the substrate 1. The first passivation layer 6 can be formed on the entire surface of the first gate structure 4, the second gate structure 5, and the barrier layer 3 away from the substrate 1.

[0083] S140: Etch the first sub-passivation layer and the second sub-passivation layer between the first gate structure and the second gate structure to form a first opening, the first opening exposing the barrier layer.

[0084] Specifically, such as Figure 7 As shown, using a photomask, the drift region of the GaNHEMT device is selectively opened through photolithography and etching processes to form the first opening 63. A certain distance can be set between the first opening 63 and the edge of the first gate structure 4, and also between the first opening 63 and the edge of the second gate structure 5, ensuring that the first passivation layer 6 completely surrounds the first gate structure 4 and the second gate structure 5. The first passivation layer 6 is mainly used for passivation protection of the first gate structure 4 and the second gate structure 5. The thickness of the first sub-passivation layer 61 can be relatively thick, resulting in stronger electric field shielding. This makes the first passivation layer 6, composed of the first sub-passivation layer 61 and the second sub-passivation layer 62, provide better passivation protection for the first gate structure 4 and the second gate structure 5, thereby reducing leakage current in the first gate structure 4 and the second gate structure 5.

[0085] S150: Electronegative atoms are doped onto the surface of the barrier layer exposed at the first opening away from the substrate through a plasma surface treatment process. The electronegativity of the electronegative atoms is greater than or equal to that of oxygen atoms.

[0086] Specifically, such as Figure 7 As shown, when electronegative atoms are doped onto the surface of the barrier layer 3 exposed at the first opening 63 away from the substrate 1 to form an electronegative atom doped layer, the specific process involves placing the surface of the barrier layer 3 exposed at the first opening 63 away from the substrate 1 in a plasma atmosphere of oxygen and / or fluorine. In this process, because the entire device is placed in a plasma atmosphere, the function of the second sub-passivation layer 62 is to isolate the first sub-passivation layer 61, the first gate structure 4, and the second gate structure 5 from the plasma atmosphere, thereby preventing them from being damaged by the plasma. In other words, without the second sub-passivation layer 62, the surface of the first sub-passivation layer 61 would be exposed to the plasma atmosphere, failing to achieve the effect of reducing gate leakage current. The second sub-passivation layer 62 is used to protect the first sub-passivation layer 61, the first gate structure 4, and the second gate structure, specifically, to prevent adverse effects when electronegative atoms are doped onto the surface of the barrier layer 3 exposed at the first opening 63 away from the substrate 1.

[0087] During the process of doping the surface of the barrier layer 3 with the electronegative atom to form an electronegative atom doped layer, its surface is oxidized and the interface is improved. This can improve the surface states of the barrier layer 3 in the drift region, increase the concentration of the two-dimensional electron gas in the drift region, and thus improve the performance of the power device. The larger the opening size of the first opening 63, the better the effect on improving the concentration and mobility of the two-dimensional electron gas in the drift region.

[0088] S160: A second passivation layer is formed on the side of the first passivation layer away from the substrate and within the first opening. The second passivation layer includes a third sub-passivation layer and a fourth sub-passivation layer.

[0089] Specifically, such as Figure 8 As shown, a second passivation layer 7 is formed on the side of the first passivation layer 6 away from the substrate 1, within the first opening 63. The thickness of the third sub-passivation layer 71 can be less than the thickness of the first sub-passivation layer 61. The second passivation layer 7, which is in direct contact with the barrier layer 3 within the first opening 63, can effectively enhance the stress in the drift region of the GaN HEMT device, thereby increasing the concentration and mobility of the two-dimensional electron gas in the GaN HEMT device, reducing the on-resistance of the GaN HEMT device, and improving the dynamic performance of the GaN HEMT device. The larger the opening size of the first opening 63, the larger the contact area between the second passivation layer 7 and the barrier layer 3, and the concentration and mobility of the two-dimensional electron gas in the GaN HEMT device can be further improved.

[0090] S170: A first electrode is formed on the side of the first gate structure away from the first opening.

[0091] Specifically, such as Figure 9 As shown, the first passivation layer 6 may also have a fourth opening 66, and the second passivation layer 7 may also have a sixth opening 73. The fourth opening 66 may be located on the side of the first gate structure 4 away from the first opening 63, and the vertical projection of the sixth opening 73 onto the substrate 1 may coincide with the vertical projection of the fourth opening 66 onto the substrate 1. The first electrode 81 is located within the fourth opening 66 and the sixth opening 73 and is in contact with the barrier layer 3.

[0092] S180: A second electrode is formed on the side of the second gate structure away from the first opening.

[0093] Specifically, such as Figure 9 As shown, the first passivation layer 6 may also have a fifth opening 67, and the second passivation layer 7 may also have a seventh opening 74. The fifth opening 67 may be located on the side of the second gate structure 5 away from the first opening 63, and the vertical projection of the seventh opening 74 onto the substrate 1 may coincide with the vertical projection of the fifth opening 67 onto the substrate 1. The second electrode 82 is located within the fifth opening 67 and the seventh opening 74 and is in contact with the barrier layer 3.

[0094] Optionally, based on the above embodiments, Figure 10 This is a flowchart of another method for fabricating a semiconductor device provided in this embodiment of the present invention. Figures 11-12 This is a schematic diagram of some steps in a method for fabricating another semiconductor device provided by this utility model embodiment, as shown below. Figure 10 As shown, the preparation method includes:

[0095] S200: Provides a substrate.

[0096] S210: A channel layer and a barrier layer are formed sequentially on one side of the substrate.

[0097] S220: A first gate structure and a second gate structure are formed at intervals on the side of the barrier layer away from the substrate.

[0098] S230: A first passivation layer is formed on the side of the first gate structure, the second gate structure, and the barrier layer away from the substrate. The first passivation layer includes a first sub-passivation layer and a second sub-passivation layer.

[0099] S240: Etch the first sub-passivation layer and the second sub-passivation layer between the first gate structure and the second gate structure to form a first opening, the first opening exposing the barrier layer.

[0100] S250: Etching the first sub-passivation layer and the second sub-passivation layer on the side of the first gate structure away from the first opening forms a second opening, and the second opening exposes the barrier layer.

[0101] Specifically, such as Figure 11 As shown, the first sub-passivation layer 61 and the second sub-passivation layer 62 on the side of the first gate structure 4 away from the first opening 63 are etched to form the second opening 64. A certain distance can be set between the edge of the second opening 64 near the first gate structure 4 and the first gate structure 4 to ensure that the first passivation layer 6 between the edge of the second opening 64 near the first gate structure 4 and the first gate structure 4 can completely surround the first gate structure 4, effectively passivating and protecting the first gate structure 4. The edge of the second opening 64 away from the first gate structure 4 can be located between the first gate structure 4 and the first electrode 81. The edge of the second opening 64 away from the first gate structure 4 can continue to extend, reaching the area of ​​the first electrode 81 and the area of ​​the first electrode 81 away from the first gate structure 4.

[0102] S260: The first sub-passivation layer and the second sub-passivation layer on the side of the second gate structure away from the first opening are etched to form a third opening, and the third opening exposes the barrier layer.

[0103] Specifically, such as Figure 11The first sub-passivation layer 61 and the second sub-passivation layer 62 on the side of the second gate structure 5 away from the first opening 63 are etched to form a third opening 65. A certain distance can be set between the edge of the third opening 65 near the second gate structure 5 and the second gate structure 5 to ensure that the first passivation layer 6 between the edge of the third opening 65 near the second gate structure 5 and the second gate structure 5 can completely surround the second gate structure 5, effectively passivating and protecting the second gate structure 5. The edge of the third opening 65 away from the second gate structure 5 can be located between the second gate structure 5 and the second electrode 82. The edge of the third opening 65 away from the second gate structure 5 can continue to extend, reaching the region of the second electrode 82 and the region of the second electrode 82 away from the second gate structure 5.

[0104] S270: Electronegative atoms are doped onto the surface of the barrier layer exposed at the first opening away from the substrate through a plasma surface treatment process. The electronegativity of the electronegative atoms is greater than or equal to that of oxygen atoms.

[0105] S280: Electronegative atoms are doped onto the surface of the barrier layer exposed at the second opening away from the substrate through a plasma surface treatment process. The electronegativity of the electronegative atoms is greater than or equal to that of oxygen atoms.

[0106] Specifically, such as Figure 11 As shown, when electronegative atoms are doped onto the surface of the barrier layer 3 exposed at the second opening 64 away from the substrate 1 to form an electronegative atom doped layer using a plasma surface treatment process, the specific process involves placing the surface of the barrier layer 3 exposed at the second opening 64 away from the substrate 1 in a plasma atmosphere of oxygen and / or fluorine. In this process, because the entire device is placed in a plasma atmosphere, the function of the second sub-passivation layer 62 is to isolate the first sub-passivation layer 61, the first gate structure 4, and the second gate structure 5 from the plasma atmosphere, thereby preventing them from being damaged by the plasma. In other words, without the second sub-passivation layer 62, the surface of the first sub-passivation layer 61 would be exposed to the plasma atmosphere, failing to achieve the effect of reducing gate leakage current. The second sub-passivation layer 62 is used to protect the first sub-passivation layer 61, the first gate structure 4, and the second gate structure 5, specifically, to prevent adverse effects when electronegative atoms are doped onto the surface of the barrier layer 3 exposed at the second opening 64 away from the substrate 1.

[0107] During the process of doping the surface of the barrier layer 3 with the electronegative atom to form an electronegative atom doped layer, its surface is oxidized and the interface is improved. This can improve the surface states of the barrier layer 3 in the drift region, increase the concentration of the two-dimensional electron gas in the drift region, and thus improve the performance of the power device. The larger the opening size of the second opening 64, the better the effect on improving the concentration and mobility of the two-dimensional electron gas in the drift region.

[0108] S290: Electronegative atoms are doped on the surface of the barrier layer exposed at the third opening away from the substrate through a plasma surface treatment process. The electronegativity of the electronegative atoms is greater than or equal to that of oxygen atoms.

[0109] Specifically, such as Figure 11 As shown, when electronegative atoms are doped onto the surface of the barrier layer 3 exposed at the third opening 65 away from the substrate 1 to form an electronegative atom doped layer, the specific process involves placing the surface of the barrier layer 3 exposed at the third opening 65 away from the substrate 1 in a plasma atmosphere of oxygen and / or fluorine. In this process, because the entire device is placed in a plasma atmosphere, the function of the second sub-passivation layer 62 is to isolate the first sub-passivation layer 61, the first gate structure 4, and the second gate structure 5 from the plasma atmosphere, thereby preventing them from being damaged by the plasma. In other words, without the second sub-passivation layer 62, the surface of the first sub-passivation layer 61 would be exposed to the plasma atmosphere, failing to achieve the effect of reducing gate leakage current. The second sub-passivation layer 62 is used to protect the first sub-passivation layer 61, the first gate structure 4, and the second gate structure 5, specifically, to prevent adverse effects when electronegative atoms are doped onto the surface of the barrier layer 3 exposed at the third opening 65 away from the substrate 1.

[0110] During the process of doping the surface of the barrier layer 3 with the electronegative atom to form an electronegative atom doped layer, its surface is oxidized and the interface is improved. This can improve the surface states of the barrier layer 3 in the drift region, increase the concentration of the two-dimensional electron gas in the drift region, and thus improve the performance of the power device. The larger the opening size of the third opening 65, the better the effect on improving the concentration and mobility of the two-dimensional electron gas in the drift region.

[0111] S291: A second passivation layer is formed on the side of the first passivation layer away from the substrate and within the first opening, the second opening, and the third opening. The second passivation layer includes a third sub-passivation layer and a fourth sub-passivation layer.

[0112] Specifically, such as Figure 12 As shown, a second passivation layer 7 is formed on the side of the first passivation layer 6 away from the substrate 1 and within the first opening 63, the second opening 64, and the third opening 65. The thickness of the third sub-passivation layer 71 can be less than the thickness of the first sub-passivation layer 61. The second passivation layer 7, which is in direct contact with the barrier layer 3 within the first opening 63, the second opening 64, and the third opening 65, can effectively enhance the stress in the drift region of the GaN HEMT device, thereby increasing the concentration and mobility of the two-dimensional electron gas in the GaN HEMT device, reducing the on-resistance of the GaN HEMT device, and improving the dynamic performance of the GaN HEMT device.

[0113] S292: A first electrode is formed on the side of the first gate structure away from the first opening.

[0114] S293: A second electrode is formed on the side of the second gate structure away from the first opening.

[0115] Optionally, based on the above embodiments, Figure 13 This is a flowchart of another method for fabricating a semiconductor device provided in this embodiment of the present invention, such as... Figure 13 As shown, the preparation method includes:

[0116] S300: Provides a substrate.

[0117] S310: A channel layer and a barrier layer are formed sequentially on one side of the substrate.

[0118] S320: A first gate structure and a second gate structure are formed at intervals on the side of the barrier layer away from the substrate.

[0119] S330: A first sub-passivation layer is formed on the entire surface of the first gate structure, the second gate structure, and the side of the barrier layer away from the substrate.

[0120] Specifically, such as Figure 6 As shown, a first sub-passivation layer 61 is formed on the entire surface of the first gate structure 4, the second gate structure 5 on the side away from the substrate 1 and the barrier layer 3 on the side away from the substrate 1. For example, the material of the first sub-passivation layer 61 can be aluminum nitride or aluminum oxide, etc.

[0121] S340: A second sub-passivation layer is formed on the side of the first sub-passivation layer away from the substrate.

[0122] Specifically, such as Figure 6 As shown, a second sub-passivation layer 62 is formed on the side of the first sub-passivation layer 61 away from the substrate 1. For example, the material of the second sub-passivation layer 62 can be silicon nitride or silicon oxide, etc.

[0123] S350: Etch the first sub-passivation layer and the second sub-passivation layer between the first gate structure and the second gate structure to form a first opening, the first opening exposing the barrier layer.

[0124] S360: Electronegative atoms are doped onto the surface of the barrier layer exposed at the first opening away from the substrate through a plasma surface treatment process. The electronegativity of the electronegative atoms is greater than or equal to that of oxygen atoms.

[0125] S370: A third sub-passivation layer is formed on the side of the first passivation layer away from the substrate and within the first opening.

[0126] Specifically, such as Figure 8As shown, a third sub-passivation layer 71 is formed on the side of the second sub-passivation layer 62 away from the substrate 1, and the third sub-passivation layer 71 is formed within the first opening 63. For example, the material of the third sub-passivation layer 71 may include aluminum nitride or aluminum oxide, etc.

[0127] S380: A fourth sub-passivation layer is formed on the side of the third sub-passivation layer away from the substrate.

[0128] Specifically, such as Figure 8 As shown, a fourth sub-passivation layer 72 is formed on the side of the third sub-passivation layer 71 away from the substrate 1. For example, the material of the fourth sub-passivation layer 72 may include silicon nitride or silicon oxide, etc.

[0129] S390: A first electrode is formed on the side of the first gate structure away from the first opening.

[0130] S391: A second electrode is formed on the side of the second gate structure away from the first opening.

[0131] Optionally, based on the above embodiments, Figure 14 This is a flowchart of another method for fabricating a semiconductor device provided in this embodiment of the present invention, such as... Figure 14 As shown, the preparation method includes:

[0132] S400: Provides a substrate.

[0133] S410: A channel layer and a barrier layer are formed sequentially on one side of the substrate.

[0134] S420: A first gate structure and a second gate structure are formed at intervals on the side of the barrier layer away from the substrate.

[0135] S430: A first passivation layer is formed on the side of the first gate structure, the second gate structure, and the barrier layer away from the substrate. The first passivation layer includes a first sub-passivation layer and a second sub-passivation layer.

[0136] S440: Etch a first sub-passivation layer and a second sub-passivation layer between the first gate structure and the second gate structure to form a first opening, the first opening exposing the barrier layer.

[0137] S450: Electronegative atoms are doped onto the surface of the barrier layer exposed at the first opening away from the substrate through a plasma surface treatment process. The electronegativity of the electronegative atoms is greater than or equal to that of oxygen atoms.

[0138] S460: A second passivation layer is formed on the side of the first passivation layer away from the substrate and within the first opening. The second passivation layer includes a third sub-passivation layer and a fourth sub-passivation layer.

[0139] S470: Etch a second passivation layer on the side of the first gate structure away from the first opening to form a sixth opening.

[0140] Specifically, such as Figure 1 As shown, a sixth opening 73 is formed on the second passivation layer 7 on the side of the first gate structure 4 away from the first opening 63 by photolithography and etching processes.

[0141] S480: The first passivation layer corresponding to the sixth opening is etched to form the fourth opening; the vertical projection of the fourth opening onto the substrate coincides with the vertical projection of the sixth opening onto the substrate.

[0142] Specifically, such as Figure 1 As shown, a fourth opening 66 is formed on the first passivation layer 6 in the region corresponding to the sixth opening 73 through photolithography and etching processes.

[0143] S490: The first electrode is formed in the fourth and sixth openings.

[0144] Specifically, such as Figure 1 As shown, a first electrode 81 is formed in the fourth opening 66 and the sixth opening 73. For example, the first electrode 81 can be a metal electrode.

[0145] S491: Etch the second passivation layer on the side of the second gate structure away from the first opening to form the seventh opening.

[0146] Specifically, such as Figure 1 As shown, a seventh opening 74 is formed on the second passivation layer 7 on the side of the second gate structure 5 away from the first opening 63 by photolithography and etching processes.

[0147] S492: The first passivation layer corresponding to the seventh opening is etched to form the fifth opening; the vertical projection of the fifth opening onto the substrate coincides with the vertical projection of the seventh opening onto the substrate.

[0148] Specifically, such as Figure 1 As shown, a fifth opening 67 is formed on the first passivation layer 6 in the region corresponding to the seventh opening 74 through photolithography and etching processes.

[0149] S493: A second electrode is formed in the fifth and seventh openings.

[0150] Specifically, such as Figure 1 As shown, a second electrode 82 is formed in the fifth opening 67 and the seventh opening 74. For example, the second electrode 82 can be a metal electrode.

[0151] It should be understood that the various forms of the process shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this utility model can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this utility model can be achieved, and this is not limited herein.

[0152] The specific embodiments described above do not constitute a limitation on the scope of protection of this utility model. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model should be included within the scope of protection of this utility model.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A channel layer is located on one side of the substrate; A barrier layer is located on the side of the channel layer away from the substrate; A first gate structure and a second gate structure are spaced apart on the side of the barrier layer away from the substrate. A first passivation layer is located on the side of the first gate structure, the second gate structure, and the barrier layer away from the substrate; the first passivation layer includes a first sub-passivation layer and a second sub-passivation layer, the first passivation layer includes a first opening, the first opening is located between the first gate structure and the second gate structure, and the first opening exposes the barrier layer; The side of the barrier layer exposed by the first opening away from the substrate includes an electronegative atom doping layer, wherein the electronegativity of the electronegative atoms is greater than or equal to that of the oxygen atoms; The second passivation layer is located on the side of the first passivation layer away from the substrate and fills the first opening. The second passivation layer includes a third sub-passivation layer and a fourth sub-passivation layer. A first gate field plate and a second gate field plate are located on the side of the second passivation layer away from the substrate. The vertical projection of the first gate field plate onto the substrate covers the vertical projection of the first gate structure onto the substrate. The vertical projection of the second gate field plate onto the substrate covers the vertical projection of the second gate structure onto the substrate. The first electrode is located on the side of the first gate structure away from the first opening; The second electrode is located on the side of the second gate structure away from the first opening.

2. The semiconductor device according to claim 1, characterized in that, The first passivation layer further includes a second opening and a third opening; the second opening is located on the side of the first gate structure away from the first opening, and the third opening is located on the side of the second gate structure away from the first opening; the second opening and the third opening expose the barrier layer, and the side of the barrier layer exposed by the second opening and the third opening away from the substrate includes an electronegative atom doping layer, wherein the electronegativity of the electronegative atoms is greater than or equal to the electronegativity of the oxygen atoms; The second passivation layer fills the second opening and the third opening.

3. The semiconductor device according to claim 1, characterized in that, The first sub-passivation layer is located on the side of the first gate structure, the second gate structure, and the barrier layer away from the substrate; the second sub-passivation layer is located on the side of the first sub-passivation layer away from the substrate; the third sub-passivation layer is located on the side of the first passivation layer away from the substrate, and the third sub-passivation layer fills the first opening; the fourth sub-passivation layer is located on the side of the third sub-passivation layer away from the substrate; the thickness of the third sub-passivation layer is less than the thickness of the first sub-passivation layer.

4. The semiconductor device according to claim 3, characterized in that, The thickness of the first sub-passivation layer is 5nm-100nm, and the thickness of the third sub-passivation layer is 0.5nm-5nm.

5. The semiconductor device according to claim 1, characterized in that, The first sub-passivation layer includes a first aluminum nitride layer, and the third sub-passivation layer includes a second aluminum nitride layer.

6. The semiconductor device according to claim 1, characterized in that, The second sub-passivation layer includes a first silicon nitride layer, a first silicon oxide layer, and / or a first silicon oxynitride layer, and the fourth sub-passivation layer includes a second silicon nitride layer, a second silicon oxide layer, and / or a second silicon oxynitride layer.

7. The semiconductor device according to claim 1 or 2, characterized in that, The electronegative atom doped layer includes an oxygen atom doped layer and / or a fluorine atom doped layer.

8. The semiconductor device according to claim 1, characterized in that, The cross-sectional shape of the first opening is a symmetrical shape along the center line of the semiconductor device, and the first gate field plate and the second gate field plate are symmetrical along the center line of the semiconductor device; the distance between the vertical projection of the first gate structure on the substrate and the vertical projection of the first opening on the substrate and the distance between the vertical projection of the second gate structure on the substrate and the vertical projection of the first opening on the substrate are equal. The first gate structure and the second gate structure are the same gate structure; The distance between the vertical projection of the first electrode on the substrate and the vertical projection of the first gate structure on the substrate is the same as the distance between the vertical projection of the second electrode on the substrate and the vertical projection of the second gate structure on the substrate; both the first electrode and the second electrode are in contact with the barrier layer.

9. The semiconductor device according to claim 2, characterized in that, The opening size of the second opening is the same as the opening size of the third opening; the distance between the vertical projection of the second opening on the substrate and the vertical projection of the first electrode on the substrate is equal to the distance between the vertical projection of the third opening on the substrate and the vertical projection of the second electrode on the substrate; the distance between the vertical projection of the second opening on the substrate and the vertical projection of the first gate structure on the substrate is equal to the distance between the vertical projection of the third opening on the substrate and the vertical projection of the second gate structure on the substrate.

10. The semiconductor device according to claim 2, characterized in that, The vertical projection of the first gate field plate onto the substrate does not overlap with the vertical projection of the first opening onto the substrate, and the vertical projection of the first gate field plate onto the substrate does not overlap with the vertical projection of the second opening onto the substrate; or, the vertical projection of the first gate field plate onto the substrate at least partially overlaps with the vertical projection of the first opening onto the substrate, and the vertical projection of the first gate field plate onto the substrate at least partially overlaps with the vertical projection of the second opening onto the substrate. The vertical projection of the second gate field plate onto the substrate does not overlap with the vertical projection of the first opening onto the substrate, and the vertical projection of the second gate field plate onto the substrate does not overlap with the vertical projection of the third opening onto the substrate; or, the vertical projection of the second gate field plate onto the substrate at least partially overlaps with the vertical projection of the first opening onto the substrate, and the vertical projection of the second gate field plate onto the substrate at least partially overlaps with the vertical projection of the third opening onto the substrate.

11. The semiconductor device according to claim 1, characterized in that, The first passivation layer includes a fourth opening and a fifth opening, and the second passivation layer includes a sixth opening and a seventh opening; The fourth opening is located on the side of the first gate structure away from the first opening, and the vertical projection of the sixth opening on the substrate coincides with the vertical projection of the fourth opening on the substrate. The first electrode is located within the fourth opening and the sixth opening; The fifth opening is located on the side of the second gate structure away from the first opening, and the vertical projection of the seventh opening on the substrate coincides with the vertical projection of the fifth opening on the substrate. The second electrode is located within the fifth opening and the seventh opening.

12. The semiconductor device according to claim 1, characterized in that, The first gate structure includes a first III-V semiconductor layer and a first gate; the second gate structure includes a second III-V semiconductor layer and a second gate. The first III-V semiconductor layer is located on the side of the barrier layer away from the substrate, and the first gate is located on the side of the first III-V semiconductor layer away from the substrate; the second III-V semiconductor layer is located on the side of the barrier layer away from the substrate, and the second gate is located on the side of the second III-V semiconductor layer away from the substrate.

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