A silicon carbide vdmos device potential balancing termination structure
By constructing a P+ doped region and a potential transfer metal layer in a silicon carbide VDMOS device, combined with an insulating dielectric region, the breakdown risk caused by electric field concentration is resolved, the device's withstand voltage capability is improved, and the process is simplified.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- GLOBAL POWER TECH CO LTD
- Filing Date
- 2025-04-24
- Publication Date
- 2026-05-29
AI Technical Summary
Traditional silicon carbide VDMOS devices have electric field concentration at the edges, resulting in a high risk of breakdown and requiring multiple field limiting rings to achieve withstand voltage, which is difficult to achieve in the manufacturing process.
A P+ doped region is constructed next to the P+ well region of the device. The electric field is uniformly distributed through a high resistivity conductor layer and a potential transfer metal layer. The electric field intensity is further distributed by a low dielectric constant insulating medium, thereby improving the withstand voltage capability of the terminal structure.
This technology improves the withstand voltage without increasing the width of the terminal structure, reduces the risk of breakdown, and simplifies the manufacturing process.
Smart Images
Figure CN224306196U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a potential balance termination structure for a silicon carbide VDMOS device. Background Technology
[0002] Silicon carbide VDMOS is a typical example of silicon carbide power devices, widely used in electric vehicles, aerospace, and power conversion. Based on the device structure design, the edges of repeating cells experience electric field concentration due to the lateral distribution of the electric field, leading to breakdown at the device edges. Traditional cells use field-limiting ring structures with the same doping concentration to suppress this electric field concentration. However, because the doping concentration and spacing of the field-limiting rings are equal, the electric field strength gradually decreases, and there are still differences in the electric field distribution. The risk of breakdown remains high near the P+ well region. Furthermore, a large number of field-limiting rings are needed to achieve the breakdown voltage at the device terminals, sacrificing area for voltage withstand capability, and the manufacturing process is difficult. Utility Model Content
[0003] The technical problem to be solved by this utility model is to provide a potential balance termination structure for silicon carbide VDMOS devices, which improves the withstand voltage capability of the average unit width termination, that is, while ensuring the withstand voltage capability of the termination, the width of the termination structure is saved.
[0004] In a first aspect, this utility model provides a potential-balanced termination structure for a silicon carbide VDMOS device, comprising:
[0005] silicon carbide substrate,
[0006] A drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate, and the drift layer having a P+ well region, a P+ doped region, at least three insulating dielectric regions and a stop ring contact region;
[0007] An insulating layer is provided, which is connected to the upper side of the P+ doped region, the upper side of the drift layer, and the upper side of the insulating dielectric region, respectively; the insulating layer is provided with at least two through holes;
[0008] At least two potential-transferring metal layers are disposed within the via, and the lower side of the potential-transferring metal layers is connected to the upper side of the drift layer.
[0009] A stop ring metal layer, the lower side of which is connected to the stop ring contact area;
[0010] A source metal layer, the lower side of which is connected to the P+ well region and the P+ doped region.
[0011] The advantages of this utility model are:
[0012] I. This utility model constructs a P+ doped region next to the P+ well region of the device to diffuse the electric field of the main junction toward the cutoff ring, thereby avoiding the concentration of the electric field at the main junction. A high resistivity conductor layer is constructed between the source metal layer and the cutoff ring metal layer 5 for connection, thereby achieving a uniform potential distribution between the source metal layer and the cutoff ring metal layer. The potential of the high resistivity conductor layer is transferred to the drift layer at equal intervals through the potential transfer metal layer, thereby achieving a uniform lateral transfer of potential in the drift layer.
[0013] II. This utility model constructs an insulating dielectric region next to the potential transfer metal layer. By using a low dielectric constant insulating dielectric, the electric field strength of the insulating dielectric region is increased, and the high potential from the main junction is gradually distributed towards the cutoff ring metal layer, thereby achieving an approximately uniform distribution of the electric field strength in the lateral direction and improving the withstand voltage of the terminal structure. Attached Figure Description
[0014] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0015] Figure 1 This is a schematic diagram of a potential balance termination structure for a silicon carbide VDMOS device according to the present invention.
[0016] Figure 2 A cross-sectional view of the process of a potential balance termination structure for a silicon carbide VDMOS device according to this utility model. Figure 1 .
[0017] Figure 3 A cross-sectional view of the process of a potential balance termination structure for a silicon carbide VDMOS device according to this utility model. Figure 2 .
[0018] Figure 4 A cross-sectional view of the process of a potential balance termination structure for a silicon carbide VDMOS device according to this utility model. Figure 3 .
[0019] Figure 5 A cross-sectional view of the process of a potential balance termination structure for a silicon carbide VDMOS device according to this utility model. Figure 4 .
[0020] Figure 6 A cross-sectional view of the process of a potential balance termination structure for a silicon carbide VDMOS device according to this utility model. Figure 5 .
[0021] Figure 7 A cross-sectional view of the process of a potential balance termination structure for a silicon carbide VDMOS device according to this utility model. Figure 6 .
[0022] Figure 8 A cross-sectional view of the process of a potential balance termination structure for a silicon carbide VDMOS device according to this utility model. Figure 7 .
[0023] Figure 9 A cross-sectional view of the process of a potential balance termination structure for a silicon carbide VDMOS device according to this utility model. Figure 8 .
[0024] Figure 10 A cross-sectional view of the process of a potential balance termination structure for a silicon carbide VDMOS device according to this utility model. Figure 9 .
[0025] Figure 11 A cross-sectional view of the process of a potential balance termination structure for a silicon carbide VDMOS device according to this utility model. Figure 10 . Detailed Implementation
[0026] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0028] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.
[0029] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.
[0030] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0031] like Figure 1 As shown, this application embodiment provides a potential balance termination structure for a silicon carbide VDMOS device, including:
[0032] Silicon carbide substrate 1,
[0033] Drift layer 2, the lower side of which is connected to the upper side of the silicon carbide substrate 1, and the drift layer 2 is provided with a P+ well region 21, a P+ doped region 22, at least three insulating dielectric regions 23 and a stop ring contact region 24.
[0034] An insulating layer 3 is connected to the upper side of the P+ doped region 22, the upper side of the drift layer 2, and the upper side of the insulating dielectric region 23, respectively; the insulating layer 3 is provided with at least two through holes 31;
[0035] At least two potential-transferring metal layers 4 are disposed within the perforation 31, and the lower side of the potential-transferring metal layer 4 is connected to the upper side of the drift layer 2.
[0036] A stop ring metal layer 5, the lower side of which is connected to the stop ring contact area 24;
[0037] Source metal layer 6, the lower side of which is connected to the P+ well region 21 and the P+ doped region 22;
[0038] Drain metal layer 8, which is connected to the lower side of silicon carbide substrate 1.
[0039] In this embodiment, preferably, it further includes a high resistivity conductor layer 7, the lower side of which is connected to the insulating layer 3 and the potential transfer metal layer 4.
[0040] In this embodiment, preferably, the doping concentration of the P+ doped region 22 is less than the doping concentration of the P+ well region 21.
[0041] In this embodiment, preferably, the thickness of the P+ doped region 22 is greater than the thickness of the P+ well region 21.
[0042] In this embodiment, preferably, the thickness of the insulating dielectric region 23 is greater than the thickness of the P+ well region 21.
[0043] In this embodiment, preferably, the width of the insulating dielectric region 23 is equal to the distance between the leftmost insulating dielectric region 23 and the P+ doped region 22, and the width of the insulating dielectric region 23 is equal to the distance between two adjacent insulating dielectric regions 23.
[0044] like Figures 1 to 11 As shown, the method for preparing the above-mentioned terminal structure includes the following steps:
[0045] Step 1: Epitaxial growth is performed on silicon carbide substrate 1 to form drift layer 2;
[0046] Step 2: Form a barrier layer 9 on the drift layer 2, etch the barrier layer 9 to form a via, and implant ions to form a P+ doped region 22;
[0047] Step 3: Remove the barrier layer 9, reform the barrier layer 9, etch the barrier layer 9 to form a via, and implant ions to form the P+ well region 21 and the stop ring contact region 24, respectively.
[0048] Step 4: Remove the barrier layer 9, reform the barrier layer 9, etch the barrier layer 9 to form a via, etch the drift layer 2 to form at least three trenches 25, and deposit to form an insulating dielectric region 23.
[0049] Step 5: Remove the barrier layer 9, reform the barrier layer 9, etch the barrier layer 9 to form a via, and deposit to form the insulating layer 3;
[0050] Step 6: Remove the barrier layer 9, reform the barrier layer 9, etch the barrier layer 9 to form a via, etch the insulating layer 3 to form at least two through holes 31, and deposit metal to form a potential transfer metal layer 4.
[0051] Step 7: Remove the barrier layer 9, reform the barrier layer 9, etch the barrier layer 9 to form vias, and deposit to form a high resistivity conductor layer 7;
[0052] Step 8: Remove the barrier layer 9, reform the barrier layer 9, etch the barrier layer 9 to form a via, and deposit to form the source metal layer 6 and the stop ring metal layer 5.
[0053] In another embodiment of this invention, the termination structure is applied to the termination of a planar gate silicon carbide VDMOS device. Since this is a termination structure design, the device cell structure will not be described further. Instead, a single-sided termination structure will be used as an example. The doping concentration of the N-type silicon carbide substrate 1 is 2-8e18cm⁻¹. -3 The doping concentration of the N-type drift layer 2 is 5-9e16cm. -3 The doping concentration of P+ doped region 22 is 1-5e18cm. -3 The doping concentration of P+ well region 21 is 5-8e18cm. -3 The doping concentration of the stop ring contact region 24 is 5-8e18cm. -3 The insulating layer 3 can be made of silicon dioxide, the insulating dielectric region 23 can be made of silicon dioxide or an insulating material with a dielectric constant less than that of silicon dioxide, the high resistivity conductor layer 7 is made of SIPOS material or low-doped polysilicon, the source metal layer 6, the stop ring metal layer 5 and the potential transfer metal layer 4 are made of one or more metals such as Al, Cu and Ni; the doping concentration of the N-type silicon carbide substrate 1, the N-type drift layer 2 and the P+ well region 21 is based on the traditional design structure of planar gate silicon carbide VDMOS devices, which extends the electric field of the device laterally towards the stop ring metal layer 5, reduces the electric field strength and improves the reliability of the device;
[0054] In the terminal structure, the width d1 of the P+ doped region 22 is 5 μm, the maximum depth of the P+ well region 21 is 600 nm, and the depth of the P+ doped region 22 is 1.5 μm. The overlap width w1 between the P+ well region 21 and the P+ doped region 22 is 200 nm to prevent separation of the two regions due to process errors, which would affect the device's terminal breakdown voltage characteristics. This is because the electric field concentration is most severe at the main junction, and the risk of breakdown is highest thereafter. The P+ doped region 22 is needed to laterally extend the electric field strength of the main junction. The width w of the insulating dielectric region 23 is 2 μm, and its thickness is 800 μm. The distance w from the P+ doped region 22 to the nearest insulating dielectric region 23 is 2 μm. Potential transfer... The metal transfer layer 4 is distributed between the insulating dielectric regions 23, and its width is equal to the distance between two adjacent insulating dielectric regions 23, which is 2 μm. The width w of the insulating dielectric region 23 is 2 μm. The lateral voltage divider adopts a standard unit structure. This is because a relatively uniform lateral electric field distribution can be achieved through a high resistivity material and a potential transfer metal structure after the main junction. The thickness of the insulating layer 3 is 800 nm, which is a compromise design considering the fabrication process speed and withstand voltage capability. The number of voltage divider standard units can be increased or decreased according to different withstand voltage requirements. Increasing the number of voltage divider standard units can improve the withstand voltage. The thickness of the high resistivity conductor layer 7 is 100 nm, which is to improve the voltage divider effect.
[0055] By constructing a P+ doped region 22 next to the P+ well region 21 of the device, the electric field of the main junction is diffused towards the cutoff ring, avoiding the concentration of the electric field at the main junction. A high resistivity conductor layer 7 is constructed between the source metal layer 6 and the cutoff ring metal layer 5 to connect them, thereby achieving a uniform potential distribution between the source metal layer 6 and the cutoff ring metal layer 5. The potential of the high resistivity conductor layer 7 is transferred to the N-type drift layer 2 at equal intervals through the potential transfer metal layer 4, thereby achieving a lateral uniform transfer of potential in the N-type drift layer 2.
[0056] An insulating dielectric region 23 is constructed next to the potential transfer metal layer 4. The electric field strength of the insulating dielectric region 23 is increased by the low dielectric constant insulating dielectric, and the high potential from the main junction is gradually distributed to the direction of the cutoff ring metal layer 5, so as to achieve an approximately uniform distribution of the electric field strength in the lateral direction and improve the withstand voltage of the terminal structure.
[0057] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.
Claims
1. A potential-balanced termination structure for a silicon carbide VDMOS device, characterized in that: include: silicon carbide substrate, A drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate, and the drift layer having a P+ well region, a P+ doped region, at least three insulating dielectric regions and a stop ring contact region; An insulating layer is provided, which is connected to the upper side of the P+ doped region, the upper side of the drift layer, and the upper side of the insulating dielectric region, respectively; the insulating layer is provided with at least two through holes; At least two potential-transferring metal layers are disposed within the via, and the lower side of the potential-transferring metal layers is connected to the upper side of the drift layer. A stop ring metal layer, the lower side of which is connected to the stop ring contact area; A source metal layer, the lower side of which is connected to the P+ well region and the P+ doped region.
2. The silicon carbide VDMOS device potential balance termination structure as described in claim 1, characterized in that: It also includes a high resistivity conductor layer, the lower side of which is connected to the insulating layer and the potential-transferring metal layer.
3. The silicon carbide VDMOS device potential balance termination structure as described in claim 1, characterized in that: The doping concentration of the P+ doped region is less than that of the P+ well region.
4. The potential balance termination structure of a silicon carbide VDMOS device as described in claim 1, characterized in that: The thickness of the P+ doped region is greater than the thickness of the P+ well region.
5. The potential balance termination structure of a silicon carbide VDMOS device as described in claim 1, characterized in that: The thickness of the insulating dielectric region is greater than the thickness of the P+ well region.
6. The potential balance termination structure of a silicon carbide VDMOS device as described in claim 1, characterized in that: The width of the insulating medium region is equal to the distance between the leftmost insulating medium region and the P+ doped region, and the width of the insulating medium region is equal to the distance between two adjacent insulating medium regions.