Silicon carbide vdmos insulation high uis characteristic terminal

Abstract

The utility model provides a kind of silicon carbide VDMOS insulation high UIS characteristic terminal, comprising: silicon carbide substrate;Drift layer, the drift layer is located on the upside of the silicon carbide substrate, P+ trap region, P type area, insulating medium area and P+ area are equipped on the drift layer;The lower part of the insulating medium area is located in the P type area;The right side of the P+ trap region is connected to the left side of the insulating medium area, and the lower side of the P+ trap region is respectively connected to the drift layer and P type area;The left side of the P+ area is connected to the right side of the insulating medium area, and the lower side of the P+ area is respectively connected to the drift layer and P type area;Insulating layer, the lower side of the insulating layer is connected to the upside of insulating medium area and the upside of P+ area;Source metal layer, the source metal layer is connected to the upside of P+ trap region and the upside of insulating layer, improves the UIS performance of terminal.

Description

Technical Field

[0001] This utility model relates to a silicon carbide VDMOS insulated terminal with high UIS characteristics. Background Technology

[0002] Silicon carbide VDMOS is a typical example of silicon carbide power devices, widely used in electric vehicles, aerospace, and power conversion. Based on the device structure design, the edges of repeating cells experience electric field concentration due to the lateral distribution of the electric field, leading to breakdown at the device edges. Traditional cells use field-limiting ring structures with the same doping concentration to suppress this electric field concentration. However, because the doping concentration and spacing of the field-limiting rings are equal, the electric field strength gradually decreases, and there are still differences in the electric field distribution. The risk of breakdown remains high near the P+ well region. Furthermore, since the device operates under unclamped inductive load conditions, there is a situation where the drain experiences high voltage after the device is turned off, i.e., the UIS characteristic of the device. The termination structure has a weakness in the UIS characteristic of the device. Utility Model Content

[0003] The technical problem to be solved by this utility model is to provide a silicon carbide VDMOS insulated terminal with high UIS characteristics, thereby improving the UIS performance of the terminal.

[0004] In a first aspect, this utility model provides a silicon carbide VDMOS insulating high UIS characteristic terminal, characterized in that it includes:

[0005] silicon carbide substrate;

[0006] A drift layer is disposed on the upper side of the silicon carbide substrate. The drift layer has a P+ well region, a P-type region, an insulating dielectric region, and a P+ region. The lower part of the insulating dielectric region is disposed within the P-type region. The right side of the P+ well region is connected to the left side of the insulating dielectric region, and the lower side of the P+ well region is connected to the drift layer and the P-type region, respectively. The left side of the P+ region is connected to the right side of the insulating dielectric region, and the lower side of the P+ region is connected to the drift layer and the P-type region, respectively.

[0007] An insulating layer, the lower side of which is connected to the upper side of the insulating dielectric region and the upper side of the P+ region;

[0008] A source metal layer is connected to the upper side of the P+ well region and the upper side of the insulating layer.

[0009] The advantages of this utility model are:

[0010] I. This utility model provides an insulating dielectric region wrapped by a P-type region on the terminal structure next to the P+ well region of the device, thereby cutting off the edge region of the P+ well region and avoiding the electric field concentration on the side of the P+ well region near the terminal, which would lead to a decrease in the withstand voltage. There is a P-type region below the P+ well region near the terminal that is connected to it, which concentrates and buffers the electric field below it, thereby reducing the electric field strength and improving the terminal withstand voltage of the device.

[0011] Second, this utility model extends the electric field of the insulating dielectric region and the P-type region into the device drift layer, so that the terminal electric field distribution extends into the device body, avoiding the breakdown effect on the terminal structure of the device.

[0012] Third, the P-type region and P+ region outside the insulating dielectric region of this utility model can ensure that when the drain of the device is subjected to voltage, the electric field is first distributed laterally and then longitudinally, thereby improving the withstand voltage at the terminal edge.

[0013] IV. The insulating dielectric structure of this utility model includes an insulating dielectric region and an insulating layer. Due to the greater breakdown field strength of the insulating dielectric structure, the withstand voltage capability of the device terminal is stronger. The insulating dielectric structure and the transverse and longitudinal withstand voltage structure on the outside of the terminal can improve the withstand voltage capability of the device, thereby improving the UIS characteristics of the device. Attached Figure Description

[0014] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0015] Figure 1 This is a schematic diagram of a silicon carbide VDMOS insulated high UIS characteristic terminal according to the present invention.

[0016] Figure 2 This is a process cross-section of a silicon carbide VDMOS insulating high UIS characteristic terminal according to the present invention. Figure 1 .

[0017] Figure 3 This is a process cross-section of a silicon carbide VDMOS insulating high UIS characteristic terminal according to the present invention. Figure 2 .

[0018] Figure 4 This is a process cross-section of a silicon carbide VDMOS insulating high UIS characteristic terminal according to the present invention. Figure 3 .

[0019] Figure 5 This is a process cross-section of a silicon carbide VDMOS insulating high UIS characteristic terminal according to the present invention. Figure 4 .

[0020] Figure 6 This is a process cross-section of a silicon carbide VDMOS insulating high UIS characteristic terminal according to the present invention. Figure 5.

[0021] Figure 7 This is a process cross-section of a silicon carbide VDMOS insulating high UIS characteristic terminal according to the present invention. Figure 6 .

[0022] Figure 8 This is a process cross-section of a silicon carbide VDMOS insulating high UIS characteristic terminal according to the present invention. Figure 7 .

[0023] Figure 9 This is a process cross-section of a silicon carbide VDMOS insulating high UIS characteristic terminal according to the present invention. Figure 8 . Detailed Implementation

[0024] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0026] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0027] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.

[0028] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0029] like Figure 1 As shown, this application embodiment provides a silicon carbide VDMOS insulated high UIS characteristic terminal, including:

[0030] Silicon carbide substrate 1;

[0031] A drift layer 2 is disposed on the upper side of the silicon carbide substrate 1. The drift layer 2 has a P+ well region 21, a P-type region 22, an insulating dielectric region 23, and a P+ region 24. The lower part of the insulating dielectric region 23 is disposed within the P-type region 22. The right side of the P+ well region 21 is connected to the left side of the insulating dielectric region 23, and the lower side of the P+ well region 21 is connected to the drift layer 2 and the P-type region 22, respectively. The left side of the P+ region 24 is connected to the right side of the insulating dielectric region 23, and the lower side of the P+ region 24 is connected to the drift layer 2 and the P-type region 22, respectively.

[0032] Insulating layer 3, the lower side of which is connected to the upper side of insulating medium region 23 and the upper side of P+ region 24;

[0033] Source metal layer 4, which is connected to the upper side of P+ well region 21 and the upper side of insulating layer 3;

[0034] Drain metal layer 5, which is connected to the lower side of silicon carbide substrate 1.

[0035] In this embodiment, preferably, the thickness w1 of the P-type region 22 located to the left of the insulating medium region 23 is less than the thickness w2 of the P-type region 22 located to the right of the insulating medium region 23.

[0036] In this embodiment, preferably, the doping concentration of the P-type region 22 is less than the doping concentration of the P+ well region 21.

[0037] In this embodiment, preferably, the doping concentration of the P-type region 22 is less than the doping concentration of the P+ region 24.

[0038] In this embodiment, preferably, the thickness w2 of the P-type region 22 located to the right of the insulating dielectric region 23 is equal to the thickness w3 of the drift layer 2 located to the right of the P-type region 22.

[0039] like Figures 1 to 9 As shown, the fabrication method of the silicon carbide VDMOS insulating high UIS characteristic terminal includes the following steps:

[0040] Step 1: Epitaxial growth is performed on silicon carbide substrate 1 to form drift layer 2;

[0041] Step 2: Form a barrier layer 6 above the drift layer 2, etch the barrier layer 6 to form a via, and implant ions to form a P-type region 22;

[0042] Step 3: Remove the barrier layer 6, reform the barrier layer 6, etch the barrier layer 6 to form a via, and implant ions to form a P+ well region 21;

[0043] Step 4: Remove the barrier layer 6, reform the barrier layer 6, etch the barrier layer 6 to form a via, and implant ions to form the P+ region 24.

[0044] Step 5: Remove the barrier layer 6, reform the barrier layer 6, etch the barrier layer 6 to form a via, etch the P+ well region 21 and the P-type region 22 to form a trench 25, and deposit the insulating medium to form the insulating medium region 23.

[0045] Step 6: Remove barrier layer 6, reform barrier layer 6, etch barrier layer 6 to form vias, and deposit insulating layer 3.

[0046] Step 7: Remove barrier layer 6, reform barrier layer 6, etch barrier layer 6 to form vias, deposit metal to form source metal layer 4, and remove barrier layer 6.

[0047] In another embodiment of this invention, the doping concentration of the N-type silicon carbide substrate 1 is 2-8e18cm. -3 The doping concentration of the N-type drift layer 2 is 5-9e16cm.-3 The doping concentration of P-type region 22 is 0.8-5e17cm. -3 The doping concentration of P+ well region 21 is 5-8e18cm. -3 The doping concentration of P+ region 24 is 1-5e18cm. -3 The insulating layer 3 can be made of silicon dioxide, the insulating dielectric region 23 can be made of SiN or diamond, and the source metal layer 4 can be made of one or an alloy of Al, Cu, and Ni.

[0048] The doping concentration of the N-type silicon carbide substrate 1, N-type drift layer 2, and P+ well region 21 is considered in the traditional design structure of planar gate silicon carbide VDMOS devices. The doping concentration of the P-type region 22 is to achieve the diffusion of the electric field distribution of the P+ well region 21 downward after the main electric field is laterally distributed in the insulating dielectric region 23, thereby reducing the electric field strength and improving the reliability of the device.

[0049] In the cell structure of the device, the width d0 of the P+ well region 21 is 3μm. In the termination structure, the insulating dielectric region 23 etches a portion of the P+ well region 21, and the width w0 of this portion is 500nm. The width w1 of the P-type region 22 near the P+ well region 21 is 500nm. The width d1 of the insulating dielectric region 23 is 5μm. The width w2 of the P-type region 22 near the P+ region 24 is 1μm. The width w2+w3 of the P+ region 24 is 2μm. The width w3 of the N-type drift layer 2 to the right of the P-type region 22 is 1μm. The thickness of the insulating dielectric region 23 is 5-10μm and is adjusted according to the device termination withstand voltage design. The thickness of the P-type region 22 at the bottom of the insulating dielectric region 23 is 500nm.

[0050] In this embodiment, an insulating dielectric region 23 wrapped by a P-type region 22 is provided on the terminal structure next to the P+ well region 21 of the device to cut off the edge region of the P+ well region 21, thereby avoiding the electric field concentration on the side of the P+ well region 21 near the terminal, which would lead to a decrease in the withstand voltage. A P-type region 22 is connected to the P+ well region 21 near the terminal, which concentrates and buffers the electric field below it, thereby reducing the electric field strength and improving the terminal withstand voltage of the device.

[0051] In this embodiment, the electric field of the insulating dielectric region 23 and the P-type region 22 extends into the device drift layer 2, so that the terminal electric field distribution extends into the device body, avoiding the breakdown effect on the terminal structure of the device.

[0052] In this embodiment, the P-type region 22 and P+ region 24 outside the insulating dielectric region 23 can ensure that when the device drain is subjected to voltage, the electric field is first distributed laterally and then longitudinally, thereby improving the withstand voltage at the terminal edge.

[0053] The insulating dielectric structure of this embodiment includes an insulating dielectric region 23 and an insulating layer 3. Since the breakdown field strength of the insulating dielectric structure is greater, the withstand voltage capability of the device terminal is stronger. The insulating dielectric structure and the withstand voltage structure combined with the transverse and longitudinal structure on the outside of the terminal can improve the withstand voltage capability of the device, thereby improving the UIS characteristics of the device.

[0054] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A silicon carbide VDMOS insulating high UIS characteristic terminal, characterized in that: include: silicon carbide substrate; A drift layer is disposed on the upper side of the silicon carbide substrate. The drift layer has a P+ well region, a P-type region, an insulating dielectric region, and a P+ region. The lower part of the insulating dielectric region is disposed within the P-type region. The right side of the P+ well region is connected to the left side of the insulating dielectric region, and the lower side of the P+ well region is connected to the drift layer and the P-type region, respectively. The left side of the P+ region is connected to the right side of the insulating dielectric region, and the lower side of the P+ region is connected to the drift layer and the P-type region, respectively. An insulating layer, the lower side of which is connected to the upper side of the insulating dielectric region and the upper side of the P+ region; A source metal layer is connected to the upper side of the P+ well region and the upper side of the insulating layer.

2. The silicon carbide VDMOS insulating high UIS characteristic terminal as described in claim 1, characterized in that: The thickness of the P-type region located to the left of the insulating medium region is less than the thickness of the P-type region located to the right of the insulating medium region.

3. A silicon carbide VDMOS insulating high UIS characteristic terminal as described in claim 1, characterized in that: The doping concentration of the P-type region is less than that of the P+ well region.

4. A silicon carbide VDMOS insulated high UIS characteristic terminal as described in claim 1, characterized in that: The doping concentration of the P-type region is less than that of the P+ region.

5. A silicon carbide VDMOS insulated high UIS characteristic terminal as described in claim 1, characterized in that: The thickness of the P-type region located to the right of the insulating dielectric region is equal to the thickness of the drift layer located to the right of the P-type region.

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