Indium sheet heat dissipation packaging structure
By creating grooves on the substrate surface and sealing passive components with bottom filler adhesive, the short circuit problem caused by indium wafer splashing is solved, improving the reliability and production efficiency of packaged products.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- JIANGSU SILICON INTEGRITY SEMICON TECH CO LTD
- Filing Date
- 2025-07-30
- Publication Date
- 2026-05-29
Smart Images

Figure CN224306317U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor packaging technology, and more specifically to an indium sheet heat dissipation packaging structure. Background Technology
[0002] With technological advancements, semiconductor package sizes are increasingly approaching miniaturization, and ball array packaging (BGA) is gradually becoming the packaging choice for high-end processor chips. The significantly increased processing speed of high-end processors leads to a corresponding increase in internal heat generation. Therefore, chip packages urgently need solutions to their thermal conductivity and dissipation problems. Traditional thermal grease materials are no longer sufficient to meet the heat dissipation requirements of high-end packaged products, while metallic thermal interface materials such as indium foil are widely used in high-end packaged products due to their excellent thermal conductivity.
[0003] However, using indium sheets as a heat-conducting material also faces many challenges.
[0004] In FCBGA packaging structures, chips are becoming increasingly powerful, generating significant heat during operation. This heat needs to be quickly dissipated through a heat sink. Traditional indium wafers melt during reflow heating, and the flux used to mount the indium wafers evaporates and overflows. Some of the molten indium spills onto the substrate along with the flux. Since passive components such as capacitors and resistors are mounted on the substrate, this spilled indium can cause short circuits in these components, affecting the normal operation of the packaged product and even rendering it unusable.
[0005] Currently, the mainstream solutions include two approaches: one is to first encapsulate and protect the passive components with coating adhesive (a type of adhesive used for coating, bonding, and sealing), but this approach may develop cracks after multiple reflows, leading to indium intrusion and short circuits; the other is to add a ring-shaped metal cover on top of the passive components, but this approach significantly increases manufacturing costs and makes the process more complex. Neither of these solutions can completely solve the problem of indium splashing, and they still affect the reliability and production efficiency of packaged products.
[0006] Therefore, a new technical solution is urgently needed to effectively prevent molten indium metal from splashing onto passive components and causing short circuits, thereby improving the reliability of packaged products. Summary of the Invention
[0007] To address the aforementioned issues, this invention provides an indium sheet heat dissipation packaging structure that is simple in structure, easy to implement, and can effectively prevent molten indium metal from splashing onto passive components, thereby improving the reliability and lifespan of the packaged product.
[0008] According to one aspect of this utility model, an indium-based heat dissipation packaging structure is provided, comprising a substrate, a chip, passive components, and a heat sink. The chip is disposed on a first surface of the substrate and electrically connected to the internal circuitry of the substrate. The heat sink is mounted on the first surface of the substrate and covers the chip, with a thermal interface material between the heat sink and the chip. At least one groove is provided on the first surface of the substrate, and a pad is provided within the groove, which is electrically connected to the internal circuitry of the substrate. The passive components are partially or completely embedded in the groove and electrically connected to the pads. The connection between the bottom of the chip and the first surface of the substrate is filled with underfill adhesive, which completely covers the passive components and the groove.
[0009] Preferably, the groove is located close to the chip, which can reduce the amount of underfill used, reduce the process difficulty, and improve the coverage and wrapping effect of the underfill adhesive.
[0010] Preferably, the pads are set at the bottom of the groove. This structure has the simplest process, and the pads at the bottom of the groove are prepared during the process of setting the internal circuit of the substrate.
[0011] Preferably, the groove width is 1.3-1.6 times the width of the passive component, and the passive component is located in the middle of the groove.
[0012] Preferably, the groove is rectangular, which is simple to prepare.
[0013] Preferably, when the passive component is fully embedded in the groove, the depth of the groove is 0.5-0.8 times the thickness of the passive component, maintaining a certain distance from the chip, which makes it less likely to short circuit.
[0014] Preferably, the passive components include one or more of capacitors, resistors, and inductors.
[0015] Preferably, solder balls are provided on the second surface of the substrate for electrical connection with external circuitry.
[0016] Compared with the prior art, the beneficial effects of this utility model are:
[0017] The indium sheet heat dissipation packaging structure provided by this utility model is simple in structure, easy to implement, reduces manufacturing costs, and improves production efficiency.
[0018] This invention enables the embedding or partial embedding of passive components by setting grooves on the first surface of the substrate. Through bottom filling, the high fluidity of the filler adhesive is used to cover the passive components and the bottom of the chip together, forming a complete closed space. This effectively avoids the problem of indium sheets splashing onto passive components when they melt during reflow heating, and prevents product scrap due to short circuit of indium metal in passive components, thereby improving product reliability. Attached Figure Description
[0019] Figure 1 This is a schematic diagram of the indium sheet heat dissipation packaging structure in Embodiment 1 of this utility model;
[0020] Figure 2 This is a schematic diagram of the substrate structure in Example 1;
[0021] Figure 3 This is a schematic diagram of the structure in Example 1 in which a chip and passive components are disposed on the first surface of the substrate;
[0022] Figure 4 In order to be in Figure 3 A structural diagram of the bottom filler adhesive is provided in the image.
[0023] Figure 5 This is a schematic diagram of the indium sheet heat dissipation packaging structure in Example 2.
[0024] Reference numerals: substrate 1, first surface 101, second surface 102, internal circuit 2, solder joint 3, groove 4, pad 5, passive component 6, chip 7, bottom filler 8, indium sheet 9, heat sink 10, solder ball 11. Detailed Implementation
[0025] The present invention will be further described below with reference to specific embodiments.
[0026] Example 1
[0027] like Figure 1 As shown, in an indium sheet heat dissipation packaging structure disclosed in this embodiment, the passive component 6 is completely embedded in the groove 4.
[0028] Specifically, the indium sheet heat dissipation packaging structure includes a substrate 1, a chip 7, a passive component 6, and a heat dissipation cover 10. The chip 7 is disposed on the first surface 101 of the substrate 1 and is electrically connected to the internal circuit 2 of the substrate 1. The heat dissipation cover 10 is installed on the first surface 101 of the substrate 1 and covers the chip 7. A thermal interface material is provided between the heat dissipation cover 10 and the chip 7.
[0029] like Figure 2 As shown, substrate 1 has a first surface 101, a second surface 102, and internal circuitry 2. Solder joints 3 are provided on the first surface 101. Later, chip 7 is flip-chip mounted on the first surface 101 of substrate 1 and electrically connected to the internal circuitry 2 through the solder joints 3. At least one groove 4 is provided on the first surface 101 of substrate 1, and a pad 5 is provided in the groove 4. The pad 5 is electrically connected to the internal circuitry 2 of substrate 1.
[0030] The grooves 4 are distributed around the solder joints 3 to accommodate the passive components 6. Specifically, the grooves 4 are located close to the chip 7, which reduces the amount of underfill adhesive 8 used, simplifies the manufacturing process, and improves the coverage and encapsulation effect of the underfill adhesive 8. The grooves 4 are rectangular, which simplifies the fabrication process.
[0031] The width of the groove 4 is 1.3-1.6 times the width of the passive component 6, and the depth of the groove 4 is 0.5-0.8 times the thickness of the passive component 6. It maintains a certain distance from the chip 7, making it less likely to short circuit.
[0032] like Figure 3 As shown, the passive component 6 is fully embedded in the groove 4, and the chip 7 is flip-chipped onto the first surface 101 of the substrate 1 using flux. The passive component 6, the chip 7 and the substrate 1 are soldered together by the reflow process, so as to realize the electrical connection between the passive component 6, the chip 7 and the internal circuit 2 of the substrate 1.
[0033] Passive component 6 is positioned in the middle of groove 4. Pad 5 is positioned at the bottom of groove 4. This structure has the simplest manufacturing process, and the pad 5 at the bottom of groove 4 is prepared during the process of setting the internal circuit 2 of substrate 1.
[0034] like Figure 4 As shown, a bottom filler 8 is provided at the connection between the bottom of the chip 7 and the first surface 101 of the substrate 1. The bottom filler 8 fills the bottom of the chip 7, the substrate 1 and the groove 4 through capillary action. That is, the bottom filler 8 completely covers the passive component 6 and the groove 4. After the bottom filler 8 is cured, the passive component 6 will no longer be affected by the surrounding environment.
[0035] Next, an indium sheet 9 is mounted on the top surface of chip 7. Flux is applied to both sides of the indium sheet 9 to remove the oxide layer on its surface and increase the adhesion between the indium sheet 9 and the upper and lower interfaces. A heat sink 10 is then attached to the substrate 1 using adhesive, covering chip 7. Solder balls 11 are disposed on the second surface 102 of substrate 1 for electrical connection with external circuitry, forming a structure as shown below. Figure 1 The packaging structure is shown. The heat generated by the chip 7 during operation will be conducted through the indium sheet 9 to the heat sink 10, and finally conducted to the external environment, achieving the purpose of rapid cooling of the chip 7.
[0036] During the curing process of the adhesive, the indium sheet 9 will enter a molten state. When the flux evaporates due to heat, the gas will carry out some of the metallic indium. After the metallic indium splashes out, it may fall onto the surface of the bottom filler 8. The passive component 6 will not be affected because it is encased inside the filler.
[0037] Passive components 6 include one or more of capacitors, resistors, and inductors.
[0038] In this embodiment, by setting a groove 4 on the first surface 101 of the substrate 1, the passive component 6 is embedded or partially embedded. Through the bottom filling operation, the high fluidity of the filling adhesive is used to cover and wrap the bottom of the passive component 6 and the chip 7 together, forming a complete closed space. This effectively avoids the problem of the traditional indium sheet 9 splashing onto the passive component 6 when it melts during reflow heating, and prevents the passive component 6 from being scrapped due to short circuit of indium metal, thus improving the reliability of the product.
[0039] The indium sheet heat dissipation packaging structure provided by this utility model is simple in structure, easy to implement, reduces manufacturing costs, and improves production efficiency.
[0040] Example 2
[0041] The only difference between this embodiment and Embodiment 1 is that in the indium sheet heat dissipation packaging structure disclosed in this embodiment, the passive component 6 is partially embedded in the groove 4.
[0042] like Figure 5 As shown, when the groove 4 is fabricated on the first surface 101 of the substrate 1, the depth of the groove 4 is less than the thickness of the passive component 6. The passive component 6 is partially embedded in the groove 4 and electrically connected to the pad 5 at the bottom of the groove 4. Through a bottom filling operation, the high fluidity of the filler adhesive is used to cover and encapsulate the passive component 6 and the bottom of the chip 7 together, forming a complete closed space. These structures are consistent with those in Embodiment 1 and will not be described again here.
[0043] The indium sheet heat dissipation packaging structure disclosed in this embodiment can also effectively avoid the problem of the traditional indium sheet 9 splashing onto the passive component 6 when it melts during reflow heating, preventing the passive component 6 from being scrapped due to short circuit of indium metal, and improving the reliability of the product.
[0044] The above descriptions are merely some embodiments of this utility model. It should be noted that those skilled in the art can make other modifications and improvements without departing from the inventive concept of this utility model, and these all fall within the protection scope of this utility model.
Claims
1. An indium-based heat dissipation packaging structure, comprising a substrate, a chip, passive components, and a heat sink, wherein the chip is disposed on a first surface of the substrate and electrically connected to internal circuitry of the substrate; the heat sink is mounted on the first surface of the substrate and covers the chip, and a thermal interface material is provided between the heat sink and the chip, characterized in that... At least one groove is provided on the first surface of the substrate, and a pad is provided in the groove. The pad is electrically connected to the internal circuitry of the substrate. The passive component is partially or completely embedded in the groove and electrically connected to the pad. The connection between the bottom of the chip and the first surface of the substrate is filled with underfill adhesive, which completely covers the passive component and the groove.
2. The indium sheet heat dissipation packaging structure according to claim 1, characterized in that, The groove is located near the chip.
3. The indium sheet heat dissipation packaging structure according to claim 2, characterized in that, The solder pads are located at the bottom of the groove.
4. The indium sheet heat dissipation packaging structure according to claim 3, characterized in that, The width of the groove is 1.3-1.6 times the width of the passive component, and the passive component is located in the middle of the groove.
5. The indium sheet heat dissipation packaging structure according to claim 4, characterized in that, The groove is rectangular.
6. The indium sheet heat dissipation packaging structure according to claim 5, characterized in that, When the passive component is fully embedded in the groove, the depth of the groove is 0.5-0.8 times the thickness of the passive component.
7. The indium sheet heat dissipation packaging structure according to claim 6, characterized in that, The passive components include one or more of capacitors, resistors, and inductors.
8. The indium sheet heat dissipation packaging structure according to claim 7, characterized in that, Solder balls are disposed on the second surface of the substrate for electrical connection with external circuitry.