High-efficiency low-ripple FPGA power supply circuit based on mine card driving control system

CN224319252UActive Publication Date: 2026-06-02JIANGSU NENGYAN ELECTRIC CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
JIANGSU NENGYAN ELECTRIC CO LTD
Filing Date
2025-04-11
Publication Date
2026-06-02

AI Technical Summary

Technical Problem

Existing FPGA power modules are prone to voltage crosstalk in mining applications, resulting in high output ripple that affects AD sampling accuracy and signal processing stability, and they cannot effectively suppress microsecond-level high voltage surges.

Method used

The system employs an isolated dual-power supply design, with the core power supply circuit and the I/O power supply circuit providing 1.2V and 3.3V power respectively. A two-stage LC filter is added to the core power supply circuit, and transient voltage suppression diodes are installed in the I/O power supply circuit to prevent high-voltage surge impact.

Benefits of technology

This achieves independent voltage power supply, reduces circuit ripple, improves anti-interference capability, prevents high voltage surge impact, and ensures the stability of the FPGA power module and the accuracy of signal processing.

✦ Generated by Eureka AI based on patent content.

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Abstract

The utility model discloses a kind of high-efficiency low ripple FPGA power supply circuit based on mine card drive control system, including power supply, core power supply circuit, first power supply indicating circuit, IO power supply circuit and second power supply indicating circuit, one end of power supply is electrically connected with the direct current bus of mine card drive control system, the other end is electrically connected with the input end of core power supply circuit and first power supply indicating circuit, the output end of core power supply circuit is electrically connected with the input end of first power supply indicating circuit, the input end of IO power supply circuit is electrically connected with power supply, the output end of IO power supply circuit is electrically connected with the input end of second power supply indicating circuit.The utility model can solve the technical problem that existing existing FPGA power module is prone to voltage cross interference, and due to the higher output ripple, leading to the technical problem that its AD sampling accuracy and signal processing stability are affected, and the technical problem that microsecond level high voltage surge cannot be effectively suppressed.
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