A three-phase rectifier bridge topology with power factor compensation

By adding diodes to each phase branch of the three-phase rectifier bridge, a redundant conduction path of 12 diodes is constructed, which solves the problem of low power factor in traditional three-phase rectifier bridges and achieves the extension of current conduction time and power factor compensation.

CN224319263UActive Publication Date: 2026-06-02葛铮
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
葛铮
Filing Date
2025-04-24
Publication Date
2026-06-02

AI Technical Summary

Technical Problem

Traditional three-phase rectifier bridges have low power factors. Existing technologies, such as active power factor correction circuits or complex passive compensation networks, suffer from problems such as complex circuit structure, high cost, and low reliability.

Method used

Two diodes are added to each phase branch of the three-phase rectifier bridge to form a diode group with a specific connection relationship, resulting in a 12-diode structure. This increases the redundant conduction path and extends the current conduction time.

Benefits of technology

Power factor compensation was achieved, and the current conduction time was extended from 2-3ms to 6-9ms, thus improving the power factor compensation effect of the rectifier bridge.

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Abstract

The utility model relates to the field of power electronics technology, and particularly relates to a three-phase rectifier bridge topology structure with power factor compensation, which includes input terminals, output terminals and a diode group; the diode group includes diodes D7, D1, D4, D10, D11, D5, D2, D8, D9, D3, D6 and D12; the anode of D7 is connected to the cathode of D1; the anode of diode D1 is connected to the cathode of D4; the anode of diode D4 is connected to the cathode of D10; the anode of diode D11 is connected to the anode of D10, and the cathode is connected to the anode of D5; the anode of diode D2 is connected to the cathode of D5, and the cathode is connected to the anode of D8; the cathode of diode D9 is connected to the cathode of D8, and the anode is connected to the cathode of; the cathode of diode D6 is connected to the anode of D3, and the anode is connected to the cathode of D12. In the three-phase rectifier bridge of the utility model, 2 diodes are added to each phase, with a total of 12 diodes. When the single-phase input is conducted, the conduction time is extended from 2-3T / ms to 6-9T / ms, realizing the compensation of the power factor.
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Description

Technical Field

[0001] This utility model relates to the field of power electronics technology, specifically to a three-phase rectifier bridge topology with power factor compensation. Background Technology

[0002] Three-phase rectifier bridges, as core components of power conversion, are widely used in industrial control, power electronic equipment, and other fields. Traditional three-phase rectifier bridges typically employ a bridge structure with six diodes, resulting in a short current conduction time and a low power factor. To improve power factor (PFC), existing technologies often use active power factor correction circuits or complex passive compensation networks, but these suffer from drawbacks such as complex circuit structures, high costs, and low reliability. Therefore, to address the insufficient power factor of traditional three-phase rectifier bridges, an improved scheme that achieves efficient PFC compensation through topology optimization is urgently needed. Utility Model Content

[0003] The purpose of this invention is to overcome the above-mentioned problems and provide a three-phase rectifier bridge topology with power factor compensation.

[0004] To achieve the above objectives, the present invention adopts the following technical solution:

[0005] A three-phase rectifier bridge topology with power factor compensation includes input terminals, output terminals, and a diode group. The diode group includes diodes D7, D1, D4, D10, D11, D5, D2, D8, D9, D3, D6, and D12. The anode of diode D7 is connected to the cathode of diode D1. The anode of diode D1 is connected to the cathode of diode D4. The anode of diode D4 is connected to the cathode of diode D10. The anode of diode D11 is connected to the anode of diode D10, and its cathode is connected to the anode of diode D5. The anode of diode D2 is connected to the cathode of diode D5, and its cathode is connected to the anode of diode D8. The cathode of diode D9 is connected to the cathode of diode D8, and its anode is connected to the cathode of diode D3. The cathode of diode D6 is connected to the anode of diode D3, and its anode is connected to the cathode of diode D12.

[0006] Further, the input terminals include terminals A, A1, A2, B, B1, B2, C, C1, and C2; terminal A is connected to the anode of diode D1 and the cathode of diode D4; terminal A1 is connected to the anode of diode D7 and the cathode of diode D1; terminal A2 is connected to the anode of diode D4 and the cathode of diode D10; terminal B is connected to the anode of diode D2 and the cathode of diode D5; terminal B1 is connected to the anode of diode D8 and the cathode of diode D2; terminal B2 is connected to the anode of diode D5 and the cathode of diode D11; terminal C is connected to the anode of diode D3 and the cathode of diode D6; terminal C1 is connected to the anode of diode D9 and the cathode of diode D3; and terminal C2 is connected to the anode of diode D6 and the cathode of diode D12.

[0007] Furthermore, the output terminal includes terminal H and terminal M; terminal H is connected to the cathodes of diodes D7, D8 and D9 respectively; terminal M is connected to the anodes of diodes D10, D11 and D12 respectively.

[0008] Furthermore, diodes D7, D1, D4, D10, D11, D5, D2, D8, D9, D3, D6, and D12 all have their positive terminals facing downwards.

[0009] The advantages of this utility model are:

[0010] This invention increases the total number of diodes from 6 to 12 by adding two diodes to each phase branch of a three-phase rectifier bridge, and by adding lead terminals and constructing diode groups with specific connection relationships. Under single-phase input conditions, the added diodes create redundant conduction paths, extending the current conduction time from 2-3 T / ms to 6-9 T / ms, thereby achieving power factor compensation. Attached Figure Description

[0011] Figure 1 This is a circuit diagram of a three-phase rectifier bridge topology with power factor compensation in Example 1.

[0012] Figure 2 This is a circuit connection diagram of a three-phase rectifier bridge topology with power factor compensation in Example 1. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. The components of the embodiments of this utility model described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0014] The present invention will be described in detail below through specific embodiments to enable a better understanding of the present invention. However, the following embodiments do not limit the scope of protection of the present invention.

[0015] Example 1

[0016] like Figure 2 As shown, a three-phase rectifier bridge topology with power factor compensation includes input terminals, output terminals, a capacitor bank, and a diode bank. The diode bank includes diodes D7, D1, D4, D10, D11, D5, D2, D8, D9, D3, D6, and D12. The anode of diode D7 is connected to the cathode of diode D1. The anode of diode D1 is connected to the cathode of diode D4. The anode of diode D4 is connected to the cathode of diode D10. The anode of diode D11 is connected to the anode of diode D10, and its cathode is connected to the anode of diode D5. The anode of diode D2 is connected to the cathode of diode D5, and its cathode is connected to the anode of diode D8. The cathode of diode D9 is connected to the cathode of diode D8, and its anode is connected to the cathode of diode D3. The cathode of diode D6 is connected to the anode of diode D3, and its anode is connected to the cathode of diode D12.

[0017] Further, the input terminals include terminals A, A1, A2, B, B1, B2, C, C1, and C2; terminal A is connected to the anode of diode D1 and the cathode of diode D4; terminal A1 is connected to the anode of diode D7 and the cathode of diode D1; terminal A2 is connected to the anode of diode D4 and the cathode of diode D10; terminal B is connected to the anode of diode D2 and the cathode of diode D5; terminal B1 is connected to the anode of diode D8 and the cathode of diode D2; terminal B2 is connected to the anode of diode D5 and the cathode of diode D11; terminal C is connected to the anode of diode D3 and the cathode of diode D6; terminal C1 is connected to the anode of diode D9 and the cathode of diode D3; and terminal C2 is connected to the anode of diode D6 and the cathode of diode D12.

[0018] Furthermore, the capacitor bank includes capacitors CC1, CC2, CC3, CC4, CC5, CC6, and CC7. One end of capacitor CC1 is connected to terminal A1, and the other end is connected to capacitor CC4, both of which are connected to terminal C. The other end of capacitor CC4 is connected to terminal A2. One end of capacitor CC2 is connected to terminal B1, and the other end is connected to terminal A and capacitor CC5. The other end of capacitor CC5 is connected to terminal B2. One end of capacitor CC3 is connected to terminal C1, and the other end is connected to terminal B and capacitor CC6. The other end of capacitor CC6 is connected to terminal C2. The positive terminal of capacitor CC7 is connected to terminal H, and the negative terminal is connected to terminal M. Both ends are connected in parallel with a resistor R1 with a resistance of 10K.

[0019] Furthermore, the output terminal includes terminal H and terminal M; terminal H is connected to the cathodes of diodes D7, D8 and D9 respectively; terminal M is connected to the anodes of diodes D10, D11 and D12 respectively.

[0020] Furthermore, diodes D7, D1, D4, D10, D11, D5, D2, D8, D9, D3, D6, and D12 all have their positive terminals facing downwards.

[0021] Assuming terminal C is open, a sinusoidal alternating current UAB is applied through terminals A and B. When terminal A is positive and terminal B is negative, diodes D1, D7, D5, and D11 conduct, charging capacitor CC7. Since diodes D1 and D7 are connected in parallel with capacitor CC2 and diode D8, the charging voltage of capacitor CC2 is no greater than the charge of a PN junction. Capacitor CC5 is charged through diode D5, reaching the voltage of UAB. When terminal A is negative and terminal B is positive, capacitor CC2 is charged through diode D2, reaching the voltage of UBA. Simultaneously, capacitor CC5 and UBA are superimposed, and the negative terminal discharges through the positive terminal of diode D11 and through diodes D1 and D7, discharging capacitor CC7 until the reverse voltage reaches the voltage of a PN junction. This increases the conduction time of the rectifier bridge.

[0022] Assuming terminal A is open, a sinusoidal alternating current UBC is supplied through terminals B and C. When terminal B is positive and terminal C is negative, diodes D2, D8, D6, and D12 conduct, charging capacitor CC7. Simultaneously, capacitor CC6 is charged through diode D6, with a charge value of UBC. When terminal B is negative and terminal C is positive, diodes D5, D11, D3, and D9 conduct, charging capacitor CC7. Simultaneously, the energy stored in capacitor CC6 is added to UBC, and this energy is transferred from capacitor CC6 to capacitor CC7 through diode D12. Capacitor CC3 charges capacitor CC7 through diode D3, with a charge value of UCB.

[0023] Assuming terminal B is open, a sinusoidal alternating current UCA is supplied through terminals C and A. When terminal C is positive and terminal A is negative, diodes D3, D9, D4, and D10 conduct, charging capacitor CC7. Simultaneously, capacitor CC4 is charged through diode D4, with a charge value of UCA. When terminal C is negative and terminal A is positive, diodes D1, D7, D6, and D12 conduct, charging capacitor CC7. Simultaneously, the energy stored in capacitor CC4 is added to UCA, and through diode D1, the energy stored in capacitor CC1 is transferred to capacitor CC7. Capacitor CC4 then charges capacitor CC7 through diode D4, with a charge value of UAC. This cycle repeats continuously, constituting the working cycle of this three-phase rectifier bridge.

[0024] This shows that the circuit increases the current conduction time, extending it from 2-3ms to 6-9ms, thus achieving PFC compensation. The circuit is completely symmetrical.

[0025] The specific embodiments of this utility model have been described in detail above, but they are merely examples, and this utility model is not equivalent to the specific embodiments described above. For those skilled in the art, any equivalent modifications and substitutions to this utility model are also within the scope of this utility model. Therefore, all equivalent changes and modifications made without departing from the spirit and scope of this utility model should be covered within the scope of this utility model.

Claims

1. A three-phase rectifier bridge topology with power factor compensation, characterized in that: It includes input terminals, output terminals, capacitor banks, and diode banks; the diode banks include diodes D7, D1, D4, D10, D11, D5, D2, D8, D9, D3, D6, and D12; the anode of diode D7 is connected to the cathode of diode D1; the anode of diode D1 is connected to the cathode of diode D4; the anode of diode D4 is connected to the cathode of diode D10; the anode of diode D11 is connected to the anode of diode D10, and its cathode is connected to the anode of diode D5; the anode of diode D2 is connected to the cathode of diode D5, and its cathode is connected to the anode of diode D8; the cathode of diode D9 is connected to the cathode of diode D8, and its anode is connected to the cathode of diode D3; the cathode of diode D6 is connected to the anode of diode D3, and its anode is connected to the cathode of diode D12. The capacitor bank includes capacitors CC1, CC2, CC3, CC4, CC5, CC6, and CC7. One end of capacitor CC1 is connected to terminal A1, and the other end is connected to capacitor CC4, both of which are connected to terminal C. The other end of capacitor CC4 is connected to terminal A2. One end of capacitor CC2 is connected to terminal B1, and the other end is connected to terminal A and capacitor CC5. The other end of capacitor CC5 is connected to terminal B2. One end of capacitor CC3 is connected to terminal C1, and the other end is connected to terminal B and capacitor CC6. The other end of capacitor CC6 is connected to terminal C2. The positive terminal of capacitor CC7 is connected to terminal H, and the negative terminal is connected to terminal M.

2. The three-phase rectifier bridge topology with power factor compensation according to claim 1, characterized in that: The input terminals include terminals A, A1, A2, B, B1, B2, C, C1, and C2. Terminal A is connected to the anode of diode D1 and the cathode of diode D4. Terminal A1 is connected to the anode of diode D7 and the cathode of diode D1. Terminal A2 is connected to the anode of diode D4 and the cathode of diode D10. Terminal B is connected to the anode of diode D2 and the cathode of diode D5. Terminal B1 is connected to the anode of diode D8 and the cathode of diode D2. Terminal B2 is connected to the anode of diode D5 and the cathode of diode D11. Terminal C is connected to the anode of diode D3 and the cathode of diode D6. Terminal C1 is connected to the anode of diode D9 and the cathode of diode D3. Terminal C2 is connected to the anode of diode D6 and the cathode of diode D12.

3. A three-phase rectifier bridge topology with power factor compensation according to claim 2, characterized in that: The output terminals include terminal H and terminal M; terminal H is connected to the cathodes of diodes D7, D8 and D9 respectively; terminal M is connected to the anodes of diodes D10, D11 and D12 respectively.

4. A three-phase rectifier bridge topology with power factor compensation according to claim 3, characterized in that: Diodes D7, D1, D4, D10, D11, D5, D2, D8, D9, D3, D6, and D12 all have their positive terminals facing downwards.