A heterogeneous industrial data acquisition gateway
By combining x86 and ARM heterogeneous processor architectures with independent power supply and clock adjustment modules, the balance between performance and power consumption of a single processor architecture is solved, improving the efficiency of industrial data acquisition and processing and adapting to the diverse data needs of complex industrial environments.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- BENXI IRON & STEEL (GROUP) INFORMATION AUTOMATION CO LTD
- Filing Date
- 2025-06-27
- Publication Date
- 2026-06-02
AI Technical Summary
Existing industrial data acquisition gateways use a single processor architecture, which makes it difficult to balance high-performance computing with low power consumption requirements. Furthermore, the lack of targeted design for power supply and clock control affects data acquisition efficiency and equipment stability, making it difficult to adapt to complex and ever-changing industrial environments.
It adopts a heterogeneous processor architecture of X86 and ARM, and is equipped with an independent power controller and clock adjustment module to achieve dynamic energy efficiency control. The X86 processor handles high-complexity data, while the ARM processor handles low-power tasks, flexibly scheduling processor resources.
It achieves energy efficiency balance under different data computation complexities and task types, improves data acquisition and processing efficiency, and adapts to the diverse data acquisition and transmission needs of complex industrial environments.
Smart Images
Figure CN224319374U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of industrial data acquisition technology, and in particular to a heterogeneous industrial data acquisition gateway. Background Technology
[0002] In industrial IoT scenarios, data acquisition gateways need to adapt to diverse device protocols and process different types of data, placing high demands on computing power and power consumption control. Existing industrial data acquisition gateways mostly adopt a single processor architecture, which suffers from inflexible allocation of computing resources and difficulty in balancing high-performance computing with low power consumption requirements. Furthermore, the lack of targeted design for power supply and clock regulation makes it impossible to dynamically optimize energy efficiency based on processor load, resulting in impacts on data acquisition efficiency and device stability, making it difficult to adapt to complex and ever-changing industrial environments. Utility Model Content
[0003] In view of the above-mentioned shortcomings and deficiencies of the prior art, this utility model provides a heterogeneous industrial data acquisition gateway, which adopts an X86 and ARM heterogeneous processor architecture, and is equipped with an independent power controller and clock adjustment module to realize dynamic energy efficiency control.
[0004] To achieve the above objectives, the main technical solutions adopted by this utility model include:
[0005] A heterogeneous industrial data acquisition gateway includes an interconnected x86 processor and an ARM processor. The x86 processor and the ARM processor are connected to a power controller, which is connected to a programmable power supply module and a clock adjustment module. The x86 processor and the ARM processor are respectively connected to a memory module and a storage module. The gateway also includes a protocol conversion module and an Ethernet module, which are connected to the x86 processor and the ARM processor via a system bus.
[0006] Furthermore, the power controller includes a battery management chip TPS65023RSBR. The DCD1_EN pin of the battery management chip is connected to the x86 processor, the DCD3_EN pin is connected to the ARM processor, and the VDCDC1 pin and VDCDC3 pin are connected to the programmable power module and the clock adjustment module, respectively.
[0007] Furthermore, the protocol conversion module is model EBT3001.
[0008] Furthermore, the programmable power module is model AP-D583A.
[0009] Furthermore, the clock adjustment module is model SYN2407K.
[0010] The beneficial effects of this utility model are as follows: This utility model provides a heterogeneous industrial data acquisition gateway that integrates X86 and ARM heterogeneous processor architectures, coupled with an independent power controller and clock adjustment module, to achieve dynamic energy efficiency control. It can flexibly schedule the high-performance computing of X86 and the low-power advantages of ARM based on data computation complexity and task type, solving the problem of difficulty in balancing performance and power consumption with a single architecture, and adapting to a wider range of industrial data acquisition scenarios. This utility model can achieve dynamic power and clock control, improve the efficiency of industrial data acquisition and processing, optimize energy efficiency ratio, and adapt to diverse data acquisition and transmission needs in complex industrial environments. Attached Figure Description
[0011] Figure 1 This is a schematic diagram of the heterogeneous industrial data acquisition gateway structure of this utility model;
[0012] Figure 2 This is a schematic diagram of the power controller circuit.
[0013] In the diagram: 1 is the x86 processor, 2 is the ARM processor, 3 is the power controller, 4 is the programmable power supply module, 5 is the clock adjustment module, 6 is the memory module, 7 is the storage module, 8 is the protocol conversion module, 9 is the system bus, and 10 is the Ethernet module. Detailed Implementation
[0014] To better explain and facilitate understanding of this utility model, the present utility model will be described in detail below with reference to the accompanying drawings and specific embodiments.
[0015] This utility model provides a heterogeneous industrial data acquisition gateway, such as Figure 1 As shown, the system includes an interconnected x86 processor 1 and an ARM processor 2, which communicate via an internal bus. The x86 processor 1 handles high-complexity data processing tasks, while the ARM processor 2 handles low-power data processing tasks. They communicate via the internal bus to collaboratively complete the data acquisition task. Industrial-grade x86 processors (Intel Atom) and ARM processors (ARM Cortex-A53) are selected and integrated using standard connectors to ensure electrical connection stability.
[0016] The x86 processor 1 and ARM processor 2 are connected to a power controller 3, which in turn is connected to a programmable power module 4 and a clock adjustment module 5. The power controller 3, connected to the programmable power module 4 and clock adjustment module 5, dynamically allocates power and regulates the clock frequency based on the load of the x86 processor 1 and ARM processor 2. The power controller 3 adjusts the power allocation of the programmable power module 4 and the frequency of the clock adjustment module 5 by detecting the control signals from the x86 processor 1 and ARM processor 2. The programmable power module 4 can be an AP-D583A model. The clock adjustment module 5 can be a SYN2407K model. The power controller 3 can use a battery management chip such as TPS65023RSBR. Figure 2 As shown, the DC-DC1_EN pin of the battery management chip is connected to the x86 processor 1, the DC-DC3_EN pin is connected to the ARM processor 2, and the VDCDC1 and VDCDC3 pins are connected to the programmable power module 4 and the clock adjustment module 5, respectively. The power controller 3 distributes power through the programmable power module 4 based on the control signals from the x86 processor 1 and the ARM processor 2; the clock adjustment module 5 receives instructions from the power controller 3 and synchronously adjusts the processor clock frequency to achieve energy efficiency and performance matching.
[0017] Both the x86 processor 1 and the ARM processor 2 are connected to the memory module 6 and the storage module 7, respectively. The memory module 6 provides data caching for the x86 processor 1 and the ARM processor 2; the storage module 7 is used for persistent storage of acquired data; it also includes a protocol conversion module 8 and an Ethernet module 10, which are connected to the x86 processor 1 and the ARM processor 2 via the system bus 9. The system bus 9 connects all modules, ensuring data interaction; the protocol conversion module 8 adapts to various equipment protocols in the industrial field; the Ethernet module 10 enables data transmission to the industrial cloud platform or host computer. Specifically, the memory module 6 is configured with high-speed DDR4 memory, and the storage module 7 uses an industrial-grade solid-state drive to ensure reliable data storage; the protocol conversion module 8 supports protocols such as MODBUS, and more specifically, the protocol conversion module 8 can be an EBT3001 protocol conversion module. The Ethernet module 10 can be a high-speed industrial Ethernet chip, enabling efficient data transmission between modules via the PCIe system bus.
[0018] The work process is as follows:
[0019] The x86 processor 1 and ARM processor 2 run programs at different functional levels, while memory module 6 and storage module 7 provide the necessary resources. Protocol conversion module 8 transmits field data to the two processors via system bus 9. Data is automatically selected based on the protocol, and each processor determines whether the data should be processed by x86 processor 1 or ARM processor 2. After processing, the data is sent via Ethernet module 10. When the system is in an idle or low-power operating state as planned, the power controller 3 controls the programmable power supply module 4 and clock adjustment module 5 to regulate the overall power consumption of the system.
[0020] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Any modifications, alterations, substitutions, and variations made by those skilled in the art to the above embodiments are within the scope of the present invention.
Claims
1. A heterogeneous industrial data collection gateway, characterized by: It includes an X86 processor (1) and an ARM processor (2) that are interconnected. The X86 processor (1) and the ARM processor (2) are connected to a power controller (3). The power controller (3) is connected to a programmable power supply module (4) and a clock adjustment module (5). The X86 processor (1) and the ARM processor (2) are respectively connected to a memory module (6) and a storage module (7). It also includes a protocol conversion module (8) and an Ethernet module (10). The protocol conversion module (8) and the Ethernet module (10) are connected to the X86 processor (1) and the ARM processor (2) through a system bus (9).
2. The heterogeneous industrial data acquisition gateway of claim 1, wherein: The power controller (3) includes a battery management chip TPS65023RSBR. The DCD1_EN pin of the battery management chip is connected to the X86 processor (1), the DCD3_EN pin is connected to the ARM processor (2), and the VDCDC1 pin and VDCDC3 pin are connected to the programmable power module (4) and the clock adjustment module (5), respectively.
3. The heterogeneous industrial data acquisition gateway of claim 1, wherein: The protocol conversion module (8) is model EBT3001.
4. The heterogeneous industrial data acquisition gateway of claim 1, wherein: The programmable power module (4) is model AP-D583A.
5. The heterogeneous industrial data acquisition gateway of claim 1, wherein: The clock adjustment module (5) is model SYN2407K.