A back contact solar cell
By setting a modified layer with the same doping type outside the first carrier collection layer, the problem of requiring two laser treatments in the prior art is solved, thereby improving the performance and simplifying the process of back contact solar cells.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- JA SOLAR TECH YANGZHOU
- Filing Date
- 2025-04-10
- Publication Date
- 2026-06-02
AI Technical Summary
In the current back-contact solar cell fabrication process, two laser treatments are required to remove part of the area, which affects the passivation performance of the first carrier collection layer and leads to a decrease in cell performance.
A modification layer with the same doping type is set outside the first carrier collection layer to avoid removing the second carrier collection layer, and the longitudinal current conduction is achieved through the modification layer.
It simplifies the manufacturing process, improves the performance of solar cells, and avoids damage to the cells caused by a second laser process.
Smart Images
Figure CN224319804U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of solar cell manufacturing technology, and in particular to a back contact battery. Background Technology
[0002] In existing back-contact solar cell fabrication processes, two laser treatments are typically required. The first treatment removes a portion of the first carrier collection layer, which is fabricated across the entire surface, to open the P-region. The second treatment removes excess second carrier collection layer from the N-region surface after the second carrier collection layer has been fabricated across the entire surface. This results in a back-contact solar cell structure where the N-region consists only of the first carrier collection layer and the P-region consists only of the second carrier collection layer. Due to limitations in existing back-contact solar cell structures, the first carrier collection layer cannot directly contact the second carrier collection layer. Therefore, it is necessary to remove the second carrier collection layer outside the first carrier layer. This means that the laser process cannot avoid affecting the passivation performance of the tunneling oxide layer and other films in the first carrier collection layer, thus impacting the overall performance of the solar cell. Utility Model Content
[0003] In view of this, this utility model provides a back-contact solar cell, which is a novel solar cell structure. By providing a modified layer with the same doping type as the first carrier collection layer outside the first carrier collection layer, it is unnecessary to remove the second doped layer outside the first carrier collection layer after fabricating the second carrier collection layer containing the second doped layer, thus avoiding the second laser process required in the prior art. This not only enables the conduction of longitudinal current in the first region through the modified layer but also improves the performance of the solar cell.
[0004] To solve the above-mentioned technical problems, this utility model provides the following technical solution:
[0005] In a first aspect, the present invention provides a back-contact solar cell, comprising: a silicon substrate, wherein a first region, a second region, and a spacer region are disposed on a first main surface of the silicon substrate, the spacer region being located between the first region and the second region; a first carrier collection layer, a modification layer, and a second doped layer are stacked from the inside to the outside in the first region; wherein the first carrier collection layer and the modification layer respectively extend to the spacer region; the first carrier collection layer and the modification layer have the same doping type, and the doping type is opposite to that of the second doped layer; a second carrier collection layer is disposed in the second region; wherein the second carrier collection layer extends to the spacer region and covers the first carrier collection layer, and the second carrier collection layer includes the second doped layer.
[0006] Optionally, the interval region includes a first interval region adjacent to the first region, a second interval region adjacent to the second region, and a third interval region located between the first interval region and the second interval region; wherein,
[0007] The first carrier collection layer extends to the third interval region, the second carrier collection layer extends to the second interval region, and extends to the third interval region and covers the first carrier collection layer;
[0008] The modified layer extends to the first interval region and abuts against the second carrier collection layer that extends to the third interval region; or, the modified layer extends to the third interval region but does not extend to the second interval region.
[0009] Optionally, the first carrier collection layer includes a tunneling oxide layer and a first doped layer doped with a first dopant element stacked together; or, the first carrier collection layer includes a first intrinsic silicon thin film layer and a first doped layer doped with a first dopant element stacked together.
[0010] Optionally, the second carrier collection layer further includes a second intrinsic silicon-containing thin film layer disposed inside the second doped layer;
[0011] The modified layer and the second intrinsic silicon-containing thin film layer are located in the same layer;
[0012] And / or, the thickness of the modified layer is equal to that of the second intrinsic silicon-containing thin film layer;
[0013] And / or, the side of the modified layer near the silicon substrate is located on the same plane as the side of the second intrinsic silicon-containing thin film layer near the silicon substrate.
[0014] Optionally, the back contact solar cell further includes a first conductive thin film layer disposed outside the second doped layer in the first region, and a second conductive thin film layer disposed outside the second carrier collection layer in the second region;
[0015] The first conductive film layer does not extend into the first spacing region, and the second conductive film layer does not extend into the second spacing region.
[0016] Optionally, the first conductive thin film layer and the second conductive thin film layer are prepared simultaneously; and / or, the work function of the first conductive thin film layer and the second conductive thin film layer is adapted to the second dopant element; the work function of the first conductive thin film layer and the second conductive thin film layer is 3.1 eV to 6.5 eV.
[0017] Optionally, the back-contact solar cell further includes: a passivation layer and an anti-reflection layer sequentially disposed from the inside to the outside on the second main surface of the silicon substrate; and / or, metal electrodes disposed in the first region and the second region respectively.
[0018] And / or, the first region of the silicon substrate has a polished surface structure, and the second main surface and the second region have a textured surface structure;
[0019] And / or, the doping type of the silicon substrate is the same as the doping type of the first carrier collection layer; and the silicon substrate is an n-type silicon substrate.
[0020] Optionally, the thickness of the second intrinsic silicon-containing thin film layer is 1 nm to 50 nm; and / or, the thickness of the second doped layer is 1 nm to 50 nm.
[0021] Optionally, the thickness of the first doped layer is 30 nm to 300 nm; and / or, the thickness of the tunneling oxide layer is 0.5 nm to 3 nm; and / or, the thickness of the first intrinsic silicon-containing thin film layer is 0.5 nm to 10 nm.
[0022] The first aspect of the above-mentioned utility model has the following advantages or beneficial effects: it provides a novel solar cell structure. By setting a modified layer with the same doping type as the first carrier collection layer outside the first carrier collection layer, it is no longer necessary to remove the second doped layer outside the first carrier collection layer after preparing the second carrier collection layer containing the second doped layer, thus avoiding the second laser process in the prior art. This not only enables the conduction of longitudinal current in the first region through the modified layer but also improves the performance of the solar cell. Attached Figure Description
[0023] The accompanying drawings are provided to better understand this utility model and do not constitute an undue limitation thereof. Wherein:
[0024] Figure 1 This is a cross-sectional structural diagram of a back-contact solar cell according to an embodiment of the present utility model;
[0025] Figure 2 This is a schematic diagram of the main process of a method for preparing a back-contact solar cell according to an embodiment of the present invention;
[0026] Figure 3 This is a detailed flowchart of step S201 according to an embodiment of the present utility model;
[0027] Figure 4 This is a schematic diagram of the cross-sectional structure of the silicon substrate obtained after step S301 according to the embodiment of this utility model;
[0028] Figure 5 This is a schematic diagram of the cross-sectional structure of the silicon substrate obtained after step S302 in the embodiment of this utility model;
[0029] Figure 6 This is a schematic diagram of the cross-sectional structure of the silicon substrate obtained according to an optional embodiment in step S302 of the present invention;
[0030] Figure 7 This is a schematic diagram of the cross-sectional structure of the silicon substrate obtained after step S303 according to the embodiment of this utility model;
[0031] Figure 8 This is a schematic flowchart of step S202 according to an embodiment of the present utility model;
[0032] Figure 9 This is a schematic diagram of the cross-sectional structure of the silicon substrate obtained after step S801 according to the embodiment of this utility model;
[0033] Figure 10 This is a schematic diagram of the cross-sectional structure of the silicon substrate obtained after step S802 in the embodiment of this utility model;
[0034] Figure 11 This is a schematic diagram of the cross-sectional structure of the silicon substrate obtained after step S803 according to the embodiment of this utility model;
[0035] Figure 12 This is a schematic diagram of the cross-sectional structure of the silicon substrate after a conductive thin film layer is prepared on the outside of the second doped layer according to an embodiment of the present invention;
[0036] Figure 13 This is a schematic diagram of the cross-sectional structure of the silicon substrate after the conductive thin film layer in the spacer region has been removed by etching process according to an embodiment of the present invention.
[0037] The attached figures are labeled as follows:
[0038] 1-Silicon substrate; 11-First region; 12-Second region; 13-Spacer region; 131-First spacer region; 132-Second spacer region; 133-Third spacer region; 2-First carrier collection layer; 3-Modified layer; 4-Second doped layer; 5-First conductive thin film layer; 6-Second carrier collection layer; 7-Second conductive thin film layer; 8-Second intrinsic silicon-containing thin film layer; 9-Passivation layer; 10-Antireflection layer;
[0039] 100 - Metal electrode; 200 - Dielectric layer; 300 - Conductive thin film layer. Detailed Implementation
[0040] A solar cell is a thin-film photovoltaic semiconductor that directly generates electricity using sunlight. Also known as a "solar chip" or "photovoltaic cell," it can instantly output voltage and generate current when a circuit is established, provided it receives sufficient illumination. In physics, this is called photovoltaic (PV). To facilitate and clearly describe the fabrication method and the solar cell of this invention, exemplary embodiments of this invention are described below with reference to the accompanying drawings. These embodiments include various details to aid understanding and should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this invention. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.
[0041] Figure 1 A cross-sectional structural schematic diagram of a back-contact solar cell provided in an embodiment of the present invention is shown, as follows: Figure 1 As shown, the back-contact solar cell provided by this utility model includes: a silicon substrate 1, wherein a first region 11, a second region 12 and a spacer region 13 are disposed on a first main surface of the silicon substrate 1, the spacer region 13 being located between the first region 11 and the second region 12; a first carrier collection layer 2, a modified layer 3 and a second doped layer 4 are stacked from the inside to the outside in the first region 11; wherein the first carrier collection layer 2 and the modified layer 3 extend to the spacer region 13 respectively; the first carrier collection layer 2 and the modified layer 3 have the same doping type and the opposite doping type to the second doped layer 4; a second carrier collection layer 6 is stacked from the inside to the outside in the second region 12; wherein the second carrier collection layer 6 extends to the spacer region 13 and covers the first carrier collection layer 2, and the second carrier collection layer 6 includes the second doped layer 4.
[0042] It should be noted that although the doping types of modified layer 3 and the second doped layer 4 are opposite, since both modified layer 3 and the second doped layer 4 are independently fabricated and in contact, the interface between these two layers may have problems such as impurities and lattice mismatch. The interface between these two layers has a large defect density and recombination centers, which hinders carrier diffusion and is detrimental to carrier mobility. Therefore, an effective pn junction cannot be formed between the two independent layers, i.e., between modified layer 3 and the second doped layer 4. However, this does not affect carrier conduction.
[0043] For example, the silicon substrate 1, the first carrier collection layer 2, and the second doped layer 4 in this embodiment of the present invention can all be of different doping types. Specifically, this includes the following various cases:
[0044] Scenario 1: When the silicon substrate 1 is an n-type silicon substrate, the first dopant element can be phosphorus, and the second dopant element can be boron. A phosphorus-doped (n-type) first carrier collection layer 2 and a modification layer 3 are sequentially disposed on the first main surface of the silicon substrate 1 in the first region 11, and a boron-doped (p-type) second doped layer 4 is disposed outside the modification layer 3. It should be noted that although the n-type modification layer 3 and the p-type second doped layer 4 are in close contact, the lack of a pn junction between the modification layer 3 and the second doped layer 4 does not affect the current flow from the modification layer 3 to the second doped layer 4.
[0045] Case 2: When the silicon substrate 1 is an n-type silicon substrate, the first doping element can also be boron and the second doping element can be phosphorus. The first region 11 has a boron-doped (p-type) first carrier collection layer 2 and a modification layer 3 sequentially disposed on the first main surface of the silicon substrate 1, and a phosphorus-doped (n-type) second doping layer 4 disposed on the outside of the modification layer 3.
[0046] Case 3: When the silicon substrate 1 is a p-type silicon substrate, the first doping element can be phosphorus and the second doping element can be boron. The first region 11 has a phosphorus-doped (n-type) first carrier collection layer 2 and a modification layer 3 sequentially disposed on the first main surface of the silicon substrate 1, and a boron-doped (p-type) second doping layer 4 disposed outside the modification layer 3.
[0047] Case 4: When the silicon substrate 1 is a p-type silicon substrate, the first doping element can also be boron and the second doping element can be phosphorus. The first region 11 has a boron-doped (p-type) first carrier collection layer 2 and a modification layer 3 sequentially disposed on the first main surface of the silicon substrate 1, and a phosphorus-doped (n-type) second doping layer 4 disposed on the outside of the modification layer 3.
[0048] In response to the various situations described above, in one optional embodiment, this invention selects the same type of silicon substrate as the doping type of the first carrier collection layer 2; and the silicon substrate is an n-type silicon substrate. This is because the minority carrier lifetime of a p-type silicon substrate is generally lower than that of an n-type silicon substrate, meaning the lifetime of non-equilibrium minority carriers is lower, which affects the overall photoelectric conversion efficiency of the back-contact solar cell. Therefore, this invention selects an n-type silicon substrate instead of a p-type silicon substrate. Furthermore, through multiple tests on the performance of the back-contact solar cell, it was found that performing boron doping first (i.e., setting the first carrier collection layer to p-type) results in worse overall passivation performance compared to performing phosphorus doping first (i.e., setting the first carrier collection layer to n-type). Therefore, this invention selects to set the first carrier collection layer 2 to n-type, the same type as the silicon substrate.
[0049] like Figure 1As shown, to illustrate the extension positions of the first carrier collection layer 2, the modified layer 3, and the second carrier collection layer 6, the present invention further divides the spacer region 13. Specifically, in an optional embodiment, the spacer region 13 includes a first spacer region 131 adjacent to the first region 11, a second spacer region 132 adjacent to the second region 12, and a third spacer region 133 located between the first spacer region 131 and the second spacer region 132. It is understood that... Figure 1 The specific width divisions of the first interval region 131, the second interval region 132, and the third interval region 133 can be adjusted according to the actual situation.
[0050] In a further optional embodiment, the spacer region 13 includes: a first spacer region 131 adjacent to the first region 11, a second spacer region 132 adjacent to the second region 12, and a third spacer region 133 located between the first spacer region 131 and the second spacer region 132; wherein, the first carrier collection layer 2 extends to the third spacer region 133, the second carrier collection layer 6 extends to the second spacer region 132, and extends to the third spacer region 133 and covers the first carrier collection layer 2; the modified layer 3 extends to the first spacer region 131 and abuts against the second carrier collection layer 6 extending to the third spacer region 133. Alternatively, the modified layer 3 extends to the third spacer region 133, and the modified layer 3 does not extend to the second spacer region 132. Since the modified layer 3 is obtained by laser treatment of the second intrinsic silicon-containing thin film layer in the second carrier collection layer 6, in order to avoid damage to the second carrier collection layer 6 in the second region 12 by the laser, there needs to be a gap between the laser-modified area and the second region 12. For example, the modified layer 3 is not set at the position corresponding to the second gap region 132. In this way, the performance of the second carrier collection layer 6 corresponding to the second region 12 is ensured, thereby ensuring the performance of the back contact solar cell. In addition, in order to ensure that the second carrier collection layer 6 does not conduct with the conductive thin film layer outside the first region 11, the modified layer 3 cannot be only disposed in the first region 11, but needs to extend to the spacer region 13 to ensure that there is no longitudinal current conduction between the second carrier collection layer 6 and the conductive thin film layer outside the first region 11. As for the first carrier collection layer 2, since the back contact solar cell mainly collects and transmits carriers through the carrier collection layer, the first carrier collection layer 2 and the second carrier collection layer 4 are preferably in contact to ensure that the carrier collection layer covers the back surface of the silicon substrate 1. Therefore, in this embodiment of the present invention, the first carrier collection layer 2 is extended to the third spacer region 133 in the spacer region 13, and in contact with the second carrier collection layer 6 extended to the second spacer region 132.
[0051] The specific structure of the first carrier collecting layer 2 can be one of two different stacked structures. In one optional embodiment, the first carrier collecting layer 2 includes a stacked tunneling oxide layer and a first doped layer doped with a first dopant element; in another optional embodiment, the first carrier collecting layer 2 includes a stacked first intrinsic silicon-containing thin film layer and a first doped layer doped with a first dopant element. The process conditions for preparing the tunneling oxide layer and the first intrinsic silicon-containing thin film layer are different; one is a low-temperature preparation process, and the other is a high-temperature preparation process. In actual preparation, either the tunneling oxide layer or the first intrinsic silicon-containing thin film can be selected according to the actual process requirements.
[0052] Regarding the thickness of the first carrier collection layer 2, in one optional embodiment, the thickness of the first doped layer is 30nm to 300nm, such as 30nm, 50nm, 100nm, 200nm, 250nm, 300nm, etc., the thickness of the tunneling oxide layer is 0.5nm to 3nm, such as 0.5nm, 1nm, 2nm, 3nm, and the thickness of the first intrinsic silicon-containing thin film layer is 0.5nm to 10nm, such as 0.5nm, 2.5nm, 5nm, 8nm, 10nm, etc.
[0053] The structure of the second carrier collecting layer 6 further includes a second intrinsic silicon-containing thin film layer 8 disposed inside the second doped layer 4. That is, the second carrier collecting layer 6 is composed of a second intrinsic silicon-containing thin film layer 8 and a second doped layer 4 stacked together. In a further optional embodiment, the modification layer 3 is obtained by laser modification of the second intrinsic silicon-containing thin film layer 8 extending to the spacer region 13 and the first region 11, followed by doping with a first doping element. In other words, this embodiment of the invention, based on the preparation of the first carrier collecting layer 2, prepares a full-surface second intrinsic silicon-containing thin film layer 8 on the first main surface of the silicon substrate 1, and transforms the second intrinsic silicon-containing thin film layer 8 into a phosphorus-doped silicon-containing thin film layer (i.e., modification layer 3) by laser modification and phosphorus doping of the second intrinsic silicon-containing thin film layer 8 extending to the spacer region 13 and the first region 11. This transforms the PN junction between the first carrier collecting layer 2 and the second doped layer 6 into a composite junction, enabling current transmission.
[0054] Specifically, the material of the second intrinsic silicon-containing thin film layer 8 and / or the second doped layer 4 can be one or more of microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide and silicon carbide, and the thickness can be set to 1nm to 50nm, such as 1nm, 10nm, 15nm, 20nm, 30nm, 40nm, 45nm, 50nm, etc.
[0055] The modified layer 3 and the second intrinsic silicon-containing thin film layer 8 are located in the same layer; and / or, the modified layer 3 and the second intrinsic silicon-containing thin film layer 8 have the same thickness; and / or, the side of the modified layer 3 closest to the silicon substrate 1 and the side of the second intrinsic silicon-containing thin film layer 8 closest to the silicon substrate 1 are located on the same plane. Since the modified layer 3 is obtained by doping modification of the second intrinsic silicon-containing thin film layer 8, the two are the same layer, have the same thickness, and are located on the same horizontal plane.
[0056] In one optional embodiment, the laser modification process can use ultraviolet, green, or red light as the laser wavelength, with a pulse width of at least one or more of nanosecond, picosecond, and femtosecond, and a power of 1–100 W. Compared to laser etching, the laser modification process has very low energy and has less impact on the passivation performance of the first carrier collection layer 2. Laser modification can significantly improve the overall performance of the solar cell.
[0057] In an optional embodiment, the back-contact solar cell further includes a first conductive thin film layer 5 disposed outside the second doped layer 4 in the first region 11, and a second conductive thin film layer 7 disposed outside the second carrier collection layer 4 in the second region 12; the first conductive thin film layer 5 does not extend to the first spacer region 131, and the second conductive thin film layer 7 does not extend to the second spacer region 132. This is because a pn junction will be formed between the first carrier collection layer 2 and the second carrier collection layer 6 (excluding the portion of the second carrier collection layer 6 excluding the modified layer 3) in the spacer region 13. If the first conductive thin film layer 5 or the second conductive thin film layer 7 is disposed in this region, leakage current will occur. Therefore, it is necessary to disconnect the first conductive thin film layer 5 and the second conductive thin film layer 7 in the spacer region 13.
[0058] It should be noted that, since the second carrier collection layer 6 includes a second intrinsic silicon-containing thin film layer 8 and a second doped layer 4, a pin or nip junction can easily form between it and the first doped layer of the first carrier collection layer 2, which can easily lead to leakage or short circuit problems. However, the modified layer 3 alone does not form a heterojunction or a pn junction with the second doped layer 4, as explained above, and will not be repeated here.
[0059] In a further optional embodiment, the first conductive thin film layer 5 and the second conductive thin film layer 7 are prepared simultaneously, that is, the first conductive thin film layer 5 and the second conductive thin film layer 7 are made of the same material. Specifically, the first conductive thin film layer 5 and / or the second conductive thin film layer 7 can be metal oxides or metal nitrides doped with one or more doping elements, wherein the metal oxide can be at least one of indium oxide, tin oxide, zinc oxide, cadmium oxide, and titanium nitride, the metal nitride can be titanium nitride, and the doping element can be at least one of indium, tin, calcium, aluminum, cadmium, zinc, cerium, and fluorine.
[0060] It should be noted that in existing back-contact solar cell structures, the work functions of the conductive thin film layers used are different due to the different doping types of the carrier collection layers in the first region 11 and the second region 12. The work function, also known as the work function or work function of energy transfer, refers to the minimum energy required to move an electron from the interior of a solid to its surface. Specifically, the p-type carrier collection layer requires a relatively high work function, while the n-type carrier collection layer requires a lower work function. Therefore, conductive thin film layers with different work functions need to be matched according to different types of dopants. However, preparing two conductive thin film layers with different work functions separately would make the fabrication process very cumbersome. To simplify the fabrication process and improve efficiency as much as possible, existing technologies usually choose a relatively moderate work function to prepare the conductive thin film layer, that is, a value greater than that required for the n-type carrier collection layer but less than that required for the p-type carrier collection layer. However, this approach undoubtedly prevents both the first region 11 and the second region 12 from achieving optimal conductivity. In this embodiment of the invention, since both the first region 11 and the second region 12 are in contact with the conductive thin film layer, they are p-type doped layers (i.e., the second doped layer 4). Therefore, only the work function corresponding to the p-type doped layer needs to be selected to achieve the optimal conductivity. That is, in this embodiment of the invention, the work function of the first conductive thin film layer 5 and the second conductive thin film layer 7 is adapted to the second doping element, which eliminates the need for complex fabrication processes while ensuring the conductivity of the first region 11 and the second region 12. In a further optional embodiment, the work function of the first conductive thin film layer 5 and the second conductive thin film layer 7 is 3.1 eV to 6.5 eV, for example, 3.1 eV, 3.5 eV, 4.3 eV, 4.9 eV, 5.5 eV, 6.0 eV, 6.5 eV, etc.
[0061] In one alternative embodiment, such as Figure 1As shown, the back-contact solar cell provided by this utility model further includes a passivation layer 9 and an anti-reflection layer 10 sequentially disposed from the inside to the outside on the second main surface of the silicon substrate 1. The passivation layer 9 can be made of an intrinsic silicon-containing thin film, a stacked structure composed of an intrinsic silicon-containing thin film and an n-type doped silicon-containing thin film, or an aluminum oxide layer. In a preferred embodiment, the thickness of the intrinsic silicon-containing thin film is 1 nm to 15 nm, for example, 1 nm, 5 nm, 8 nm, 10 nm, 12 nm, or 15 nm, and the thickness of the n-type doped silicon-containing thin film is 0 nm to 15 nm, for example, 0 nm, 5 nm, 8 nm, 10 nm, 12 nm, or 15 nm. It can be understood that when the thickness of the n-type doped silicon-containing thin film is 0 nm, the passivation layer 9 is composed only of the intrinsic silicon-containing thin film. In one optional embodiment, the antireflection layer 10 can be at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, silicon oxynitride, aluminum oxynitride, magnesium fluoride, lithium fluoride, ITO, and zinc oxide, and the thickness of the antireflection layer 10 can be 40nm to 200nm, such as 40nm, 80nm, 100nm, 150nm, 200nm, etc.
[0062] In another optional embodiment, the first region 11 of the silicon substrate 1 has a polished surface structure, and the second main surface and the second region 12 have a textured surface structure.
[0063] In summary, the back-contact solar cell provided by this embodiment of the invention, by providing a modified layer 3 with the same doping type as the first carrier collection layer 2 outside the first carrier collection layer 2, eliminates the need to remove the second doped layer 4 outside the first carrier collection layer 2 after the second carrier collection layer 6 containing the second doped layer 4 is prepared, thus avoiding the second laser process required in the prior art. This not only enables the conduction of longitudinal current in the first region 11 through the modified layer 3, but also improves the performance of the solar cell.
[0064] In one embodiment of this utility model, such as Figure 2 As shown, this embodiment provides a method for fabricating a back-contact solar cell, which may include the following steps:
[0065] Step S201: A first carrier collection layer 2 is prepared in a first region 11 on the first main surface of the silicon substrate 1 and a partial spacing region 13 near the first region 11.
[0066] In step S202, a second carrier collection layer 6 is prepared in the second region 12 of the first main surface and a portion of the spacer region 13 near the second region 12, and a modified layer 3 and a second doped layer 4 are simultaneously formed in the first region 11; the modified layer 3 covers the first carrier collection layer 2, and the second doped layer 4 covers the modified layer 3; wherein the doping type of the first carrier collection layer 2 and the modified layer 3 is the same, and the doping type of the second doped layer 4 is opposite.
[0067] Following step S202, the preparation method further includes:
[0068] In step S203, a conductive thin film layer is prepared on the outside of the second doped layer 4, and the conductive thin film layer of the spacer region 13 is removed by etching process to obtain the first conductive thin film layer 5 corresponding to the first region and the second conductive thin film layer 7 corresponding to the second region.
[0069] Among them, such as Figure 1 As shown, the partial spacing region 13 in step S201 refers to the first spacing region 131 and the third spacing region 133 near the first region 11, while the partial spacing region 13 in step S202 refers to the second spacing region 132 and the third spacing region 133 near the second region 12. It can be understood that the spacing region 13 is to ensure that the first region 11 and the second region 12 are not electrically connected, that is, to ensure that there is no short circuit between the positive and negative electrodes of the back-contact solar cell. Therefore, it is sufficient to ensure that there is no electrical connection between the first carrier collection layer 2 and the second carrier collection layer 6. As for whether the first carrier collection layer 2 extends to the first spacing region 131 and the third spacing region 133 or only extends to the first spacing region 131, it can be selected according to the actual situation.
[0070] In an optional embodiment, the process of preparing the first carrier collection layer 2 only in the first region 11 and part of the spacer region 13 in step S201 can be as follows: Figure 3 As shown, it includes:
[0071] Step S301: Prepare a first carrier collection layer 2 doped with a first doping element on the first main surface of the silicon substrate 1;
[0072] Step S302: Use laser technology to remove the dielectric layer 200 and the first carrier collection layer 2 corresponding to the second region 12 on the silicon substrate;
[0073] Step S303: Remove the remaining dielectric layer 200 in the first region 11.
[0074] For example, the silicon substrate cross-sectional structure obtained after step S301 is as follows: Figure 4 As shown, the cross-sectional structure of the silicon substrate obtained after step S302 is as follows. Figure 5As shown, the cross-sectional structure of the silicon substrate obtained after step S303 is as follows: Figure 7 As shown. (Through) Figure 4 and Figure 5 As can be seen, this embodiment of the invention first prepares the first carrier collection layer 2 on the entire surface, and then removes a portion of it using a laser process, thereby retaining the first region 11 and a portion of the intermediate region 13 of the first carrier collection layer 2. The dielectric layer 200 can be one or more of silicon oxide, silicon nitride, or silicon oxynitride.
[0075] The laser removal process in step S302 can include two different implementation methods, as follows:
[0076] (1) In an optional embodiment, the dielectric layer 200 corresponding to the second region 12 and the first carrier collection layer 2 can be directly etched using a laser process, i.e., from... Figure 4 Directly obtain Figure 5 The cross-sectional structure is shown. In this embodiment, due to the large energy of laser etching, it will undoubtedly cause greater damage to the second region 12 of the silicon substrate 1. Therefore, after etching, it is necessary to perform alkaline texturing on both the first and second main surfaces of the silicon substrate 1 to eliminate laser damage. It is understood that since the dielectric layer 200 does not react with the alkaline solution, the alkaline texturing process in step S302 will not affect the structure of the first region 11.
[0077] (2) In another optional embodiment, in order to minimize the damage to the silicon substrate 1 caused by the laser energy, only the dielectric layer 200 corresponding to the second region 12 and part of the first carrier collection layer 2 are removed using a laser process to obtain... Figure 6 The cross-sectional structure of the silicon substrate is shown. Compared to directly removing the entire dielectric layer 200 and the first carrier collection layer 2, this method significantly reduces damage to the silicon substrate 1 caused by the laser process because it does not directly scan the silicon substrate 1 and leaves a portion of the first carrier collection layer 2 for absorbing laser energy. Figure 6 The obtained silicon substrate cross-sectional structure can also be obtained by using an alkaline solution texturing process to remove the remaining first carrier collection layer 2 in the second region 12. Figure 5 The silicon substrate structure shown.
[0078] In addition, the process of removing the remaining medium layer 200 in step S303 can be achieved by cleaning with an acid solution, such as hydrofluoric acid.
[0079] As can be seen, through the above steps S301 to S303, a silicon substrate cross-sectional structure with only the first region 11 and part of the spacer region 13 retained is obtained, and the second region 12 and the second main surface of the silicon substrate 1 are both textured, which is more conducive to the subsequent fabrication of the structure.
[0080] The specific process of step S202 is described in detail below, such as... Figure 8 As shown, the process of step S202 includes:
[0081] Step S801: Prepare a second intrinsic silicon-containing thin film layer 8 on the first main surface;
[0082] Step S802: Laser modification is performed on the regions in the second intrinsic silicon-containing thin film layer 8 that correspond to the first region 11 and part of the spacer region 13, so that the first doped element in the first carrier collection layer 2 diffuses into the corresponding second intrinsic silicon-containing thin film layer 8 to obtain the modified layer 3.
[0083] Step S803: A second doped layer 4 is prepared on the first main surface, covering the second intrinsic silicon-containing thin film layer 8 and the modified layer 3.
[0084] In step S801, while preparing the second intrinsic silicon-containing thin film layer 8, a passivation layer 9 and an antireflection layer 10 can be sequentially prepared on the second main surface of the silicon substrate 1, resulting in the following: Figure 9 The silicon substrate cross-sectional structure shown includes a second intrinsic silicon-containing thin film layer 8 and a passivation layer 9, both of which can be composed of one or more of microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide, and silicon carbide, and therefore can be fabricated simultaneously. Furthermore, depending on the passivation effect, a doped silicon-containing thin film layer can also be stacked in the passivation layer 9. This invention does not specifically limit this, and the choice can be made according to the actual process.
[0085] from Figure 9 It can be seen that after step S801, what is actually obtained is a silicon substrate structure in which the entire first main surface is provided with a second intrinsic silicon-containing thin film layer 8. By modifying part of the second intrinsic silicon-containing thin film layer 8 in step S802, the following can be obtained: Figure 10 The diagram shows a cross-sectional structure of a silicon substrate. To distinguish between the modified and unmodified portions, [the diagram is shown in the original text]. Figure 10 The modified layer 3 and the second intrinsic silicon-containing thin film layer 8 are marked with different colors.
[0086] In an optional embodiment, the laser modification in step S802 is actually as follows: a laser is used to irradiate the regions in the second intrinsic silicon-containing thin film layer 8 corresponding to the first region 11 and part of the spacer region 13, so that the first dopant element in the first carrier collection layer 2 located inside the second intrinsic silicon-containing thin film layer 8 diffuses to the second intrinsic silicon-containing thin film layer 8, resulting in a modified layer 3 in the first region 11 and extending to part of the spacer region 13. In other words, this embodiment of the invention provides energy to the first dopant element in the first carrier collection layer 2 using a laser, enabling the first dopant element to diffuse to the second intrinsic silicon-containing thin film layer 8, thereby obtaining the modified layer 3. Specifically, the laser wavelength selected for the laser modification process can be ultraviolet, green, or red light; the pulse width can be at least one of nanoseconds, picoseconds, or femtoseconds, or a combination thereof; and the power can be 1W to 100W, such as 1W, 20W, 50W, 80W, or 100W. Compared to laser etching, laser modification has much lower energy and has less impact on the passivation performance of the first carrier collection layer 2. Therefore, laser modification can significantly improve the overall performance of solar cells.
[0087] Finally, by preparing a second doped layer 4 across the entire surface of the first main surface, the desired result can be obtained. Figure 11 The schematic diagram of the cross-sectional structure of the silicon substrate shown shows that the second carrier collection layer 6 of the second region 12 has been formed, and the fabrication of the main structures of the first region 11 and the second region 12 of the silicon substrate 1 has been completed.
[0088] The process of preparing the first conductive thin film layer 5 and the second conductive thin film layer 7 in step S203 can be described as follows: Figure 12 and Figure 13 As shown, where, Figure 12 A schematic diagram of the cross-sectional structure of the silicon substrate after a conductive thin film layer is formed outside the second doped layer 4 is shown. Figure 13 A schematic cross-sectional view of the silicon substrate after the conductive thin film layer in the spacer region 13 is removed by an etching process is shown. Since the side of the first main surface in contact with the conductive thin film layer is a full-layer p-type second doped layer 4, the work function of the prepared conductive thin film layer can be set to be relatively high to match the p-type second doped layer 4, for example, 3.1-6.5 eV, such as 3.1 eV, 3.5 eV, 4.3 eV, 4.9 eV, 5.5 eV, 6.0 eV, 6.5 eV, etc.
[0089] In one optional embodiment, the etching paste selected in the etching process can be an etching paste containing acidic components, which can react with oxides (such as indium tin oxide, zinc oxide, tin oxide, etc.) in the conductive thin film layer, thereby achieving the effect of partially etching the conductive thin film layer 300.
[0090] In a further optional embodiment, after step S303, the process may further include: fabricating metal electrodes 100 in the first region 11 and the second region 12 of the silicon substrate 1, respectively. The metal electrodes 100 may be one or more of a silver electrode, a silver alloy electrode, a copper electrode, a copper alloy electrode, or a nickel / copper / silver multilayer electrode.
[0091] In summary, the back-contact solar cell fabrication method provided by this embodiment eliminates the need to remove the second doped layer 4 outside the first carrier collection layer 2 after fabricating the second carrier collection layer 6 containing the second doped layer 4, thus avoiding the second laser process required in the prior art. This not only enables longitudinal current conduction in the first region 11 through the modified layer 3, but also simplifies the fabrication process, reduces damage to the tunneling oxide layer and other layers of the first carrier collection layer 2 caused by existing laser processes, and improves the performance of the solar cell.
[0092] Example 1
[0093] Step a: On the first main surface of an N-type silicon substrate, a tunneling oxide layer, a first doped layer containing phosphorus, and a dielectric layer are sequentially prepared from the inside to the outside; wherein, the thickness of the tunneling oxide layer is 1.5 nm, the thickness of the first doped layer is 200 nm, and the dielectric layer is silicon oxide.
[0094] Step b: Use laser technology to remove the dielectric layer, the first doped layer, and the tunneling oxide layer corresponding to the second region; wherein, the spacer region is set between the first region and the second region;
[0095] Step c: Clean the remaining dielectric layer on the first main surface using hydrofluoric acid;
[0096] Step d: An intrinsic silicon-containing thin film layer is prepared on the first main surface of the silicon substrate, and a passivation layer and an antireflection layer are prepared sequentially from the inside to the outside on the second main surface; wherein, the passivation layer is an intrinsic silicon-containing thin film with a thickness of 10 nm, and the antireflection layer is a stacked structure composed of aluminum oxide, silicon nitride and silicon oxynitride with a thickness of 200 nm.
[0097] Step e: The intrinsic silicon-containing thin film layer in the first region is modified by laser modification process, and the intrinsic silicon-containing thin film layer is transformed into a modified layer by providing a phosphorus doping source through the first doping layer; wherein, the laser process uses an ultraviolet picosecond laser with a laser energy of 18W.
[0098] Step f: Prepare a second doped layer doped with boron on the first main surface of the silicon substrate;
[0099] Step g: Prepare a conductive thin film layer on the outside of the second doped layer, and obtain a first conductive thin film layer corresponding to the first region and a second conductive thin film layer corresponding to the second region by etching the middle region; wherein, the work function of the conductive thin film layer is 4.7eV.
[0100] Step h: Prepare metal electrodes in the first region and the second region respectively.
[0101] Comparative example (without modified layer)
[0102] Step a: On the first main surface of an N-type silicon substrate, a tunneling oxide layer, a first doped layer doped with phosphorus, and a dielectric layer are sequentially prepared from the inside to the outside; wherein, the thickness of the tunneling oxide layer is 2 nm, the thickness of the first doped layer is 200 nm, and the dielectric layer is silicon oxide.
[0103] Step b: Use a first laser process to remove the dielectric layer, the first doped layer, and the tunneling oxide layer corresponding to the second region and part of the spacer region; wherein, the spacer region is set between the first region and the second region;
[0104] Step c: Clean the remaining dielectric layer on the first main surface using hydrofluoric acid;
[0105] Step d: A passivation layer and an antireflection layer are sequentially prepared from the inside to the outside on the second main surface of the silicon substrate; wherein, the passivation layer is an intrinsic silicon-containing thin film with a thickness of 10 nm, and the antireflection layer is a stacked structure composed of aluminum oxide, silicon nitride and silicon oxynitride with a thickness of 200 nm.
[0106] Step e: On the first main surface of the silicon substrate, an intrinsic silicon-containing thin film layer and a second doped layer doped with boron are sequentially prepared from the inside to the outside.
[0107] Step f: Remove the second doped layer and the intrinsic silicon-containing thin film layer in the first region using a second laser process; wherein, the laser process uses an ultraviolet picosecond laser with a laser energy of 28W;
[0108] Step g: Prepare a conductive thin film layer on the outside of the second doped layer, and obtain a first conductive thin film layer corresponding to the first region and a second conductive thin film layer corresponding to the second region by etching the middle region; wherein, the work function of the conductive thin film layer is 4.5eV.
[0109] Step h: Prepare metal electrodes in the first region and the second region respectively.
[0110] Based on the preparation processes of Example 1 and the comparative example, it can be seen that the comparative example is a conventional preparation process of the prior art. That is, after preparing a tunneling oxide layer and a first doped layer in the first region, a whole intrinsic silicon-containing thin film layer and a second doped layer are further prepared. Finally, by removing the second doped layer and the intrinsic silicon-containing thin film layer in the first region, a first region and a second region doped with phosphorus and boron elements are obtained, respectively. However, Example 1, by preparing a modified layer, does not require the removal of the second doped layer and the modified layer in the first region. The first region obtained is a first region in which a tunneling oxide layer, a first doped layer, a modified layer, and a second doped layer are stacked from the inside out.
[0111] The performance of the back-contact solar cells prepared in Example 1 and the comparative example is shown in the table below:
[0112] <![CDATA[Jsc(mA / cm 2 )]]> Voc(mV) FF (%) Eta(%) Example 1 41.15 754.0 86.20 26.75 Comparative Example 41.03 753.2 86.05 26.59
[0113] As shown in the table, the Jsc (short-circuit current density), Voc (open-circuit voltage), FF (fill factor), and Eta (photovoltaic conversion efficiency) of the back-contact solar cell prepared by Example 1 are all higher than the corresponding parameters of the back-contact solar cell prepared by the comparative example. This demonstrates that the laser modification process provided in this embodiment for modifying the intrinsic silicon-containing thin film can avoid damage to the tunneling oxide layer and the first doped layer in the first region during the second laser process, thereby ensuring its passivation performance and guaranteeing the various performance characteristics of the back-contact solar cell.
[0114] The above steps are provided only to help understand the structure, method, and core idea of this utility model. For those skilled in the art, various improvements and modifications can be made to this utility model without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims of this utility model.
Claims
1. A back-contact solar cell, characterized in that, include: A silicon substrate (1) wherein a first region (11), a second region (12) and a spacer region (13) are disposed on a first main surface of the silicon substrate (1), and the spacer region (13) is located between the first region (11) and the second region (12); A first carrier collection layer (2), a modified layer (3), and a second doped layer (4) are stacked from the inside to the outside in the first region (11); wherein the first carrier collection layer (2) and the modified layer (3) extend to the spacer region (13); the first carrier collection layer (2) and the modified layer (3) have the same doping type and the opposite doping type to the second doped layer (4); A second carrier collection layer (6) is provided in the second region (12), the second carrier collection layer (6) extends to the interval region (13) and covers the first carrier collection layer (2), and the second carrier collection layer (6) includes the second doped layer (4).
2. The back-contact solar cell according to claim 1, characterized in that, The interval region (13) includes: a first interval region (131) adjacent to the first region (11), a second interval region (132) adjacent to the second region (12), and a third interval region (133) located between the first interval region (131) and the second interval region (132); wherein, The first carrier collection layer (2) extends to the third interval region (133), the second carrier collection layer (6) extends to the second interval region (132), and extends to the third interval region (133) and covers the first carrier collection layer (2). The modified layer (3) extends to the first interval region (131) and abuts against the second carrier collection layer (6) extending to the third interval region (133); or, the modified layer (3) extends to the third interval region (133) and does not extend to the second interval region (132).
3. The back-contact solar cell according to claim 1, characterized in that, The first carrier collection layer (2) includes a tunneling oxide layer and a first doped layer doped with a first doping element stacked together; or, the first carrier collection layer (2) includes a first intrinsic silicon thin film layer and a first doped layer doped with a first doping element stacked together.
4. The back-contact solar cell according to claim 1, characterized in that, The second carrier collection layer (6) also includes a second intrinsic silicon-containing thin film layer (8) disposed inside the second doped layer (4); The modified layer (3) and the second intrinsic silicon-containing thin film layer (8) are located in the same layer.
5. The back-contact solar cell according to claim 4, characterized in that, The modified layer (3) has the same thickness as the second intrinsic silicon-containing thin film layer (8).
6. The back-contact solar cell according to claim 4, characterized in that, The modified layer (3) is located on the same plane as the side of the silicon substrate (1) and the second intrinsic silicon-containing thin film layer (8) is located on the same plane as the side of the silicon substrate (1).
7. The back-contact solar cell according to claim 2, characterized in that, The back contact solar cell further includes a first conductive thin film layer (5) disposed outside the second doped layer (4) in the first region (11), and a second conductive thin film layer (7) disposed outside the second carrier collection layer (6) in the second region (12). The first conductive thin film layer (5) does not extend to the first spacing region (131), and the second conductive thin film layer (7) does not extend to the second spacing region (132).
8. The back-contact solar cell according to claim 1, characterized in that, Also includes: A passivation layer (9) and an antireflection layer (10) are sequentially disposed from the inside to the outside on the second main surface of the silicon substrate (1). And / or, metal electrodes (100) are respectively provided in the first region (11) and the second region (12). And / or, the first region (11) of the silicon substrate (1) has a polished surface structure, and the second main surface and the second region (12) have a textured surface structure; And / or, the doping type of the silicon substrate is the same as the doping type of the first carrier collection layer (2); and the silicon substrate is an n-type silicon substrate.
9. The back-contact solar cell according to claim 4, characterized in that, The thickness of the second intrinsic silicon-containing thin film layer (8) is 1 nm to 50 nm; And / or, The thickness of the second doped layer (4) is 1 nm to 50 nm.
10. The back-contact solar cell according to claim 3, characterized in that, The thickness of the first doped layer is 30 nm to 300 nm; And / or, The thickness of the tunneling oxide layer is 0.5 nm to 3 nm; And / or, The thickness of the first intrinsic silicon-containing thin film layer is 0.5 nm to 10 nm.