A solar cell and a manufacturing method thereof, a photovoltaic module

Abstract

This invention discloses a solar cell and its manufacturing method, as well as a photovoltaic module, relating to the field of photovoltaic technology. It aims to reduce the risk of damage to a portion of a second region of the semiconductor substrate during the patterning process of a first doped semiconductor layer on a semiconductor substrate using laser technology, thereby improving the performance of the solar cell. The solar cell includes a semiconductor substrate and a first doped semiconductor layer. The semiconductor substrate includes a first surface and a second surface disposed opposite to each other. The first surface has a first region and a second region. The first doped semiconductor layer is disposed on the first region. Specifically, in the first surface, the first region has multiple protrusion structures arranged side-by-side with curved top surface contours. The surface morphology of the second region differs from that of the first region.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic technology, and in particular to a solar cell, its manufacturing method, and a photovoltaic module. Background Technology

[0002] A solar cell is a device that converts sunlight into electrical energy. Specifically, when a solar cell is in operation, sunlight shines on it, creating new electron-hole pairs. Under the influence of the built-in electric field of the pn junction, photogenerated holes flow to the p-region, and photogenerated electrons flow to the n-region. When the circuit is connected, an electric current is generated. In practical applications, one type of solar cell includes at least one type of doped semiconductor layer disposed on a localized area of ​​the semiconductor substrate surface. This reduces the area covered by the doped semiconductor layer on the substrate, decreases parasitic absorption, and improves the light utilization efficiency of the solar cell. Alternatively, another type of solar cell includes a doped semiconductor layer on a localized area of ​​one side of the semiconductor substrate surface, with another type of doped semiconductor layer on the remaining area. Both types of solar cells utilize laser patterning technology.

[0003] However, in existing solar cells, the patterning process of the doped semiconductor layer on the semiconductor substrate using laser technology can easily damage the semiconductor substrate, resulting in poor performance of the solar cell. Summary of the Invention

[0004] The purpose of this invention is to provide a solar cell and its manufacturing method, as well as a photovoltaic module, which reduces the risk of damage to the corresponding second region of the semiconductor substrate during the patterning process of the first doped semiconductor layer on the semiconductor substrate using laser technology, thereby improving the working performance of the solar cell.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a solar cell comprising: a semiconductor substrate and a first doped semiconductor layer. The semiconductor substrate includes a first surface and a second surface disposed opposite to each other. The first surface has a first region and a second region. The first doped semiconductor layer is disposed on the first region. Specifically, in the first surface, the first region has a plurality of protrusion structures arranged side-by-side with curved top surface contours, and the surface morphology of the second region differs from that of the first region.

[0006] When the above technical solution is adopted, in the actual manufacturing process of solar cells, when the first doped semiconductor layer is patterned using laser technology (it can be understood that before the first doped semiconductor layer is patterned, a first surface of the entire first doped semiconductor layer is provided, and the first region and the second region are provided with multiple side-by-side protrusion structures with curved top surface contours). Because the portion below the first doped semiconductor layer consists of multiple parallel, relatively flat, and curved protrusion structures, it prevents the heat generated by the high-temperature laser from accumulating at the sharp corners of textured structures like velvet or at the edges of frustum structures, thus avoiding over-etching of the top surface of the protrusion structure corresponding to the first doped semiconductor layer. If the top surface has sharp protrusions, the transition at the corners is abrupt, and the energy of the laser spot will produce different etching energy due to the abrupt rise and fall of the corners, resulting in uneven etching intensity and easily causing over-etching. It also helps to ensure that the first doped semiconductor layer on the surface of the second region is completely removed while reducing or even preventing thermal damage to the surface of the second region caused by the high-temperature laser, thereby improving the yield of solar cells.

[0007] Furthermore, regarding the surface of the second region, since the functions of the first and second regions are different, its surface morphology can be set according to actual needs, so that the first and second regions respectively meet the corresponding working requirements and improve the working performance of the solar cell.

[0008] As one possible implementation, at least one boss structure is a frustum-like structure with a curved top surface profile; and / or, at least one boss structure is a frustum-shaped structure with a curved top surface profile.

[0009] With the above technical solution, the relatively regular morphology of the quasi-truncated pyramidal structure and the frustum structure with a curved top surface profile is beneficial to ensure a certain macroscopic flatness of the surface of the first region, preventing local heat concentration caused by high-temperature laser in the first region. This also helps to ensure the complete removal of the first doped semiconductor layer on the surface of the second region while reducing or even preventing thermal damage to the surface of the second region caused by the high-temperature laser. Furthermore, it also helps to improve the formation quality and passivation effect of the first doped semiconductor layer formed on the first region. In addition, in the actual manufacturing process, a pre-textured surface treatment can be performed on at least the first region surface of the semiconductor substrate, followed by polishing of the pre-formed textured structure to remove the sharp corners at the top of the textured structure, thus obtaining a boss structure. Since the textured structure has a quasi-pyramidal or quasi-conical morphology, when at least one boss structure is a quasi-truncated pyramidal structure with a curved top surface profile; and / or, when at least one boss structure is a frustum structure with a curved top surface profile, it indicates that no structural defects occurred during the manufacturing of the boss structure, which is beneficial to improving the yield of solar cells.

[0010] As one possible implementation, the height of the boss structure is H, and the one-dimensional dimension of the top surface of the boss structure is W. Specifically, in at least one boss structure, the ratio of H to W is greater than or equal to 0.1 and less than or equal to 3; and / or, in at least one boss structure, H is greater than or equal to 80 nm and less than or equal to 3000 nm; and / or, in at least one boss structure, W is greater than or equal to 160 nm and less than or equal to 6000 nm.

[0011] When the above technical solution is adopted, the ratio of H to W in at least one boss structure is within the above range. This can prevent the ratio of H to W from being too small, resulting in H being too small and / or W being too large (i.e. forming a short and stout boss structure). This would lead to a smaller degree of micro-undulation on the surface of the first region and the side of the first doped semiconductor layer away from the semiconductor substrate due to the setting of the boss structure. This is beneficial to improving the formation quality and passivation effect of the first doped semiconductor layer on the semiconductor substrate.

[0012] As for the beneficial effects of H within the above range, refer to the beneficial effects of preventing H from being too large or too small as described above; the beneficial effects of W within the above range can refer to the beneficial effects of preventing W from being too large or too small as described above.

[0013] As one possible implementation, in the boss structure, the included angle between the side edge and the top surface is greater than or equal to 125° and less than or equal to 140°.

[0014] With the above technical solution, it is understood that the angle between the side edge and the top surface affects the steepness of the side surface of the boss structure itself. Specifically, the larger the angle between the side edge and the top surface, the slower the height change of the side surface of the boss structure, and the smaller the specific surface area of ​​the first region. Conversely, the smaller the angle between the side edge and the top surface, the steeper the height change of the side surface of the boss structure, and the larger the specific surface area of ​​the first region. Based on this, when the angle between the side edge and the top surface of the boss structure is within the above range, it is beneficial to make the surface of the first region have a certain degree of micro-undulation, thereby improving the light-trapping effect of the surface of the first region; at the same time, it is beneficial to increase the bonding pull between the first doped semiconductor layer disposed on the surface of the first region and the corresponding electrode, preventing the electrode from falling off.

[0015] As one possible implementation, the surface reflectivity of the first region is greater than or equal to 10% and less than or equal to 40%.

[0016] With the above technical solution, the surface reflectivity of the first region is within the aforementioned range, which can prevent excessively high reflectivity of the first region (preventing the reflectivity of the first region from being greater than or equal to the reflectivity of a conventionally polished surface). Furthermore, it can also prevent excessively low reflectivity of the first region (preventing the reflectivity of the first region from being less than or equal to the reflectivity of the second region), resulting in a large surface roughness. If the manufacturing method described above is used, first forming a boss structure on the entire first surface and then depositing the first doped semiconductor layer layer in its entirety, it can also prevent the problem of over-etching of the top surface of the boss structure corresponding to the first doped semiconductor layer and / or incomplete removal of the bottom portion of the boss structure corresponding to the first doped semiconductor layer due to excessive surface roughness of the second region during patterning of the first doped semiconductor layer on the entire surface using laser technology. This helps ensure complete removal of the first doped semiconductor layer located on the surface of the second region while reducing or even preventing thermal damage to the surface of the second region caused by high-temperature lasers, thereby improving the yield of the solar cell. Simultaneously, it also helps improve the deposition quality and passivation effect of the first doped semiconductor layer on the surface of the first region.

[0017] As one possible implementation, along the direction from the second surface to the first surface, the surface height of the first region is greater than that of the second region. With this configuration, in the actual manufacturing process, the manufacturing method described above can be adopted. First, a boss structure is formed on the entire surface of the first surface, and a first doped semiconductor layer is deposited layer-by-layer. Then, after patterning the first doped semiconductor layer, the surface of the second region is morphologically processed, thereby forming a boss structure on the surface of the first region and making the surface morphology of the second region different from that of the first region. This allows the morphology of the first and second regions in the solar cell to simultaneously meet the corresponding operational requirements (e.g., high deposition quality and high passivation effect of the first doped semiconductor layer, high-yield patterning processing and stable bonding performance between itself and the electrode, and high light-trapping effect of the second region surface), improving the overall performance of the solar cell.

[0018] As one possible implementation, along the direction from the second surface to the first surface, the surface height difference between the first region and the second region is greater than or equal to 1 μm and less than or equal to 10 μm.

[0019] With the above technical solution, the surface height difference between the first region and the second region is within the aforementioned range. This prevents impurities from remaining on the surface of the second region due to an excessively small surface height difference, thus reducing carrier recombination. This helps ensure high conversion efficiency in the solar cell. Furthermore, it prevents the surface height difference between the first and second regions from becoming too large. Because the textured structure on the surface of the second region is a protrusion structure when the laser process removes the portion of the first doped semiconductor layer corresponding to the second region, the thermal damage to the semiconductor substrate corresponding to the second region is minimal or nonexistent. It eliminates the need to remove, or only requires the removal of a thin layer of damage, thus reducing the surface height difference between the first and second regions. This improves the mechanical strength and light absorption depth of the semiconductor substrate corresponding to the second region, and facilitates thin-film production.

[0020] As one possible implementation, the first doped semiconductor layer includes first strip-shaped portions extending along a first direction and spaced apart along a second direction. The first direction intersects the second direction. The solar cell further includes a first current collector electrode disposed on the side of the first strip-shaped portions facing away from the semiconductor substrate.

[0021] With the above technical solution, the surface of the first region is relatively flat, which is beneficial to improving the formation quality and passivation effect of the first doped semiconductor layer formed on the surface of the first region. The morphology of the first doped semiconductor layer deposited on the surface of the first region, which is away from the semiconductor substrate, is also affected by the surface morphology of the first region, and thus has a roughly the same undulating morphology. Therefore, when the surface of the first region has a relatively large degree of micro-undulation (compared to the polished surface), it is beneficial to increase the degree of micro-undulation of the surface of the first doped semiconductor layer away from the semiconductor substrate, which in turn is beneficial to increase the effective contact area and adhesion between the first doped semiconductor layer and the corresponding electrode, improve the bonding stability between the first doped semiconductor layer and the corresponding electrode in the local area of ​​the semiconductor substrate, and prevent the electrode from falling off.

[0022] Along the second direction, the ratio between the width of at least one first strip and the width of the first current collector electrode is greater than or equal to 2 and less than or equal to 100.

[0023] The ratio between the width of at least one first stripe and the width of the first collector electrode is within the aforementioned range. This prevents the width of the first stripe from being too small and / or the width of the first collector electrode from being too large due to an excessively small ratio. It ensures that the first stripe has a certain width, thus possessing a certain carrier collection capability, and reduces the precision requirements for manufacturing the first collector electrode on the first stripe. Furthermore, it prevents the width of the first stripe from being too large and / or the width of the first collector electrode from being too small due to an excessively large ratio. This helps reduce parasitic absorption in the first doped semiconductor layer and ensures that the first collector electrode has a certain width. This, in turn, helps increase the bonding pull between the first collector electrode and the first stripe, preventing the first collector electrode from detaching.

[0024] As one possible implementation, the ratio between the width of at least one first strip and the distance between two adjacent first strips is greater than or equal to 0.02 and less than or equal to 0.5. The application principle of the beneficial effect in this case can be referred to the application principle of the beneficial effect described above where the ratio between the width of at least one first strip and the width of the first current collector is greater than or equal to 2 and less than or equal to 100, which will not be repeated here.

[0025] As one possible implementation, the surface reflectivity of the second region is lower than that of the first region; and / or, the second region is provided with a textured surface. This configuration allows the surface of the second region to have a higher light-trapping effect, enabling the first surface of the solar cell to simultaneously achieve high deposition quality and passivation effect of the first doped semiconductor layer, high-yield patterning processing, and stable bonding performance between itself and the electrode, as well as the high light-trapping effect of the second region surface, thereby improving the overall performance of the solar cell.

[0026] As one possible implementation, a ridge structure is provided in the second edge sub-region of the second region surface, close to the first region surface, and the tilt direction of the ridge structure is parallel to the extension direction of the side edge of the boss structure.

[0027] With the above technical solution, it is understood that the first region surface has a raised structure with a flat top surface, making the first region surface macroscopically flat; while the surface morphology of the second region is different from that of the first region, and there is a certain difference between the two. Based on this, the surface of the second region, near the surface of the first region, has a ridge structure. This ridge structure refers to a raised structure whose length along one side is more than 1.5 times greater than the length of the opposite side ridge, and the tilt direction of the ridge structure is parallel to the extension direction of the side ridge of the raised structure. At this time, by setting the ridge structure as a structural transition between the first region surface and the second region surface, it is beneficial to improve the quality of the passivation layer deposited on the surface of the edge sub-region, reduce the number of defects on the surface of the edge sub-region, and reduce the carrier recombination rate.

[0028] As one possible implementation, the first edge sub-region near the ridge structure on the surface of the first region is set as a plateau region. This configuration makes the surfaces of the ridge structure and the plateau region smoother than the textured surface, which is beneficial for improving the formation quality of the passivation layer, resulting in better conformal deposition and coverage. This enhances the surface passivation effect of the passivation layer at the interface between the first and second region surfaces, and reduces the carrier recombination rate.

[0029] In a second aspect, the present invention provides a method for manufacturing a solar cell, the method comprising: first, providing a semiconductor substrate. The semiconductor substrate includes a first surface and a second surface disposed opposite to each other. The first surface includes a first region and a second region. Next, at least the first surface of the semiconductor substrate is textured to form a plurality of protrusion structures arranged side by side with curved top surface contours on the first surface. Next, a first doped semiconductor layer is formed on the first surface in a continuous layer. Next, the first doped semiconductor layer is patterned using a laser process to remove the first doped semiconductor layer located on the second region.

[0030] As one possible implementation, at least the first surface of the semiconductor substrate is textured, including: at least the first surface of the semiconductor substrate is subjected to pre-texturing and polishing processes in sequence.

[0031] As one possible implementation, after patterning the first doped semiconductor layer, the method for manufacturing a solar cell further includes: texturing the surface of the second region to form a textured structure on the surface of the second region.

[0032] The beneficial effects of the second aspect and its various implementations in this invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0033] Thirdly, the present invention provides a photovoltaic module comprising: a cell string and an encapsulation layer. The cell string is formed by electrically connecting multiple solar cells as provided in the first aspect and its various implementations; the encapsulation layer covers the surface of the cell string.

[0034] The beneficial effects of the third aspect and its various implementations in this invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. Attached Figure Description

[0035] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 A longitudinal sectional view of the structure of a solar cell provided in an embodiment of the present invention. Figure 1 ; Figure 2 A longitudinal sectional view of the structure of a solar cell provided in an embodiment of the present invention. Figure 2 ; Figure 3 SEM image of the solar cell at the interface between the first region surface and the second region surface provided in the embodiments of the present invention Figure 1 ; Figure 4 SEM image of the solar cell at the interface between the first region surface and the second region surface provided in the embodiments of the present invention Figure 2 ; Figure 5 This is a SEM image of a solar cell at the boss structure provided in an embodiment of the present invention; Figure 6 This is a schematic diagram showing the distribution of the first doped semiconductor layer on the first surface of a solar cell provided in an embodiment of the present invention. Figure 7 A longitudinal sectional view of the structure of a solar cell provided in an embodiment of the present invention. Figure 3 ; Figure 8 A longitudinal sectional view of the structure of a solar cell provided in an embodiment of the present invention. Figure 4 ; Figure 9 A longitudinal sectional view of the structure of a solar cell provided in an embodiment of the present invention. Figure 5 ; Figure 10 A longitudinal sectional view of the structure of a solar cell provided in an embodiment of the present invention. Figure 6 ; Figure 11 A longitudinal sectional view of the structure of a solar cell during the manufacturing process provided in an embodiment of the present invention. Figure 1 ; Figure 12 A longitudinal sectional view of the structure of a solar cell during the manufacturing process provided in an embodiment of the present invention. Figure 2 ; Figure 13 A longitudinal sectional view of the structure of a solar cell during the manufacturing process provided in an embodiment of the present invention. Figure 3 ; Figure 14 A longitudinal sectional view of the structure of a solar cell during the manufacturing process provided in an embodiment of the present invention. Figure 4 ; Figure 15 A longitudinal sectional view of the structure of a solar cell during the manufacturing process provided in an embodiment of the present invention. Figure 5 ; Figure 16 A longitudinal sectional view of the structure of a solar cell during the manufacturing process provided in an embodiment of the present invention. Figure 6 .

[0036] Reference numerals in the figures: 11 is a semiconductor substrate, 12 is a first doped semiconductor layer, 13 is a first region, 14 is a second region, 15 is a boss structure, 16 is a textured structure, 17 is a first strip, 18 is a first collector electrode, 19 is a second edge sub-region, 20 is a ridge structure, 21 is a first edge sub-region, 22 is a plateau region, 23 is a second doped semiconductor layer, 24 is a first interface passivation layer, 25 is a second interface passivation layer, and 26 is a surface passivation layer. Detailed Implementation

[0037] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0038] The accompanying drawings illustrate various structural schematic diagrams according to embodiments of the present invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0039] In the context of this invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0040] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0041] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0042] A solar cell is a device that converts sunlight into electrical energy. Specifically, when a solar cell is in operation, sunlight shines on it, creating new electron-hole pairs. Under the influence of the built-in electric field of the pn junction, photogenerated holes flow to the p-region, and photogenerated electrons flow to the n-region. When the circuit is connected, an electric current is generated. In practical applications, one type of solar cell includes at least one type of doped semiconductor layer disposed on a localized area of ​​the semiconductor substrate surface. This reduces the area covered by the doped semiconductor layer on the substrate, decreases parasitic absorption, and improves the light utilization efficiency of the solar cell. Alternatively, another type of solar cell includes a doped semiconductor layer on a localized area of ​​one side of the semiconductor substrate surface, with another type of doped semiconductor layer on the remaining area. Both types of solar cells utilize laser patterning technology.

[0043] However, in existing solar cells, the patterning process of the doped semiconductor layer on the semiconductor substrate using laser technology can easily damage the semiconductor substrate, resulting in poor performance of the solar cell.

[0044] To address the aforementioned technical problems, in a first aspect, embodiments of the present invention provide a solar cell. The solar cell can be a back-contact cell (i.e., the positive and negative electrodes of the solar cell are spaced apart on one side of the back of the cell) or a double-sided contact cell (i.e., one of the positive and negative electrodes of the solar cell is located on one side of the front of the cell, and the other is located on the back of the cell).

[0045] like Figure 1 As shown, the solar cell includes a semiconductor substrate 11 and a first doped semiconductor layer 12. The semiconductor substrate 11 includes a first surface and a second surface disposed opposite to each other. The first surface has a first region 13 and a second region 14. The first doped semiconductor layer 12 is disposed on the first region 13. With this arrangement, the second region 14 is still exposed outside the first doped semiconductor layer 12 in the first surface of the semiconductor substrate 11, which can reduce the coverage area of ​​the first doped semiconductor layer 12 and reduce the parasitic absorption of the first doped semiconductor layer 12.

[0046] In practical applications, the embodiments of the present invention do not specifically limit the material and conductivity type of the semiconductor substrate. For example, the semiconductor substrate can be any semiconductor material such as a silicon substrate, a germanium-silicon substrate, or a germanium substrate. The conductivity type of the semiconductor substrate can be P-type, N-type, or intrinsic type.

[0047] In terms of materials, the first doped semiconductor layer can be any semiconductor material such as silicon, germanium-silicon, germanium, or gallium arsenide. In terms of the arrangement of matter, the crystal phase of the first doped semiconductor layer can be amorphous, microcrystalline, nanocrystalline, single-crystal, or polycrystalline. Optionally, the first doped semiconductor layer may include a doped polycrystalline silicon layer.

[0048] In addition, such as Figure 1 As shown, the first doped semiconductor layer 12 can be directly disposed on the first region 13. Alternatively, as... Figure 2As shown, the back contact battery may further include a first interface passivation layer 24 disposed between the first doped semiconductor layer 12 and the first region 13 to reduce the carrier recombination rate. The material and thickness of the first interface passivation layer 24 can be set according to the material of the first doped semiconductor layer 12 and actual needs, and are not specifically limited here. For example, when the material of the first doped semiconductor layer is doped polycrystalline silicon, the first interface passivation layer is a tunneling oxide layer. As another example, when the material of the first doped semiconductor layer includes at least one of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon, the first interface passivation layer is an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, an intrinsic nanocrystalline silicon layer, or a mixture of the above three.

[0049] Optionally, the first doped semiconductor layer may include a doped polysilicon layer, and the first interface passivation layer is a tunneling oxide layer including a silicon oxide layer.

[0050] like Figures 2 to 4 As shown, the first region 13 may be provided with multiple side-by-side boss structures 15 with curved top surface contours, and the surface morphology of the second region 14 is different from that of the first region 13.

[0051] In practical applications, the distribution range of the first region and the second region on the first surface can be determined based on the surface morphology of different areas within the first surface. Additionally, the distribution range of the first region and the second region on the first surface can be determined based on the distribution of the first doped semiconductor layer.

[0052] like Figures 2 to 4As shown, the first region 13 corresponding to the first doped semiconductor layer 12 is provided with multiple side-by-side protrusion structures 15 with curved top surface contours. Compared with the textured structure 16 or the truncated pyramid structure, the top surface of the protrusion structure 15 is relatively flat, and the edge of the top surface has a smooth transition curve, which helps to make the first region 13 relatively flat macroscopically (compared to the second region 14). It can be understood that when the first region 13 in the solar cell is provided with protrusion structures 15, before the first doped semiconductor layer 12 is patterned, a first surface of the first doped semiconductor layer 12, which is a whole layer, is provided, and both the first region 13 and the second region 14 are provided with protrusion structures 15. When the first doped semiconductor layer 12 is patterned using laser technology, the portion below the first doped semiconductor layer 12 is a raised structure 15 with a relatively flat top surface and a curved outline. This prevents the heat generated by the high-temperature laser from easily accumulating at the sharp corners of relatively sharp textured structures such as velvet structures, which could lead to over-etching of the top surface of the raised structure 15 corresponding to the first doped semiconductor layer 12 and / or incomplete removal of the bottom portion of the raised structure 15 corresponding to the first doped semiconductor layer 12. This helps to ensure that the first doped semiconductor layer 12 located on the surface of the second region 14 is completely removed, while reducing or even preventing thermal damage to the surface of the second region 14 caused by the high-temperature laser, thereby improving the yield of solar cells. In addition, the relatively flat surface of the first region 13 is beneficial to improving the formation quality and passivation effect of the first doped semiconductor layer 12 formed in the first region 13. The morphology of the first doped semiconductor layer 12 deposited on the first region 13, which is away from the surface of the semiconductor substrate 11, is also affected by the morphology of the first region 13 and thus has a roughly the same undulating morphology. Therefore, when the first region 13 has a relatively large degree of micro-undulation (compared to the polished surface), it is beneficial to increase the degree of micro-undulation on the side of the first doped semiconductor layer 12 away from the semiconductor substrate 11, which in turn is beneficial to increase the effective contact area and adhesion between the first doped semiconductor layer 12 and the corresponding electrode, improve the bonding stability between the first doped semiconductor layer 12 and the corresponding electrode in the local area of ​​the semiconductor substrate 11, and prevent the electrode from falling off. Furthermore, regarding the surface of the second region 14, since the functions of the first region 13 and the second region 14 are different (for example, the first region 13 is used to manufacture the first doped semiconductor layer 12, while the second region 14 is not provided with the first doped semiconductor layer 12), its surface morphology can be set according to actual needs, so that the first region 13 and the second region 14 respectively meet the corresponding working requirements and improve the working performance of the solar cell.

[0053] In practical applications, the morphology and size of the boss structure set in the first region can be determined according to the requirements for laser etching damage in the second region, the requirements for deposition quality and passivation effect of the first doped semiconductor layer, and the requirements for bonding performance between the first doped semiconductor layer and the corresponding battery.

[0054] For example, such as Figure 3 and Figure 4 As shown, at least one boss structure 15 can be a truncated pyramid-like structure with a curved top surface profile; and / or, at least one boss structure 15 can be a frustum-shaped structure with a curved top surface profile. This configuration results in relatively regular morphologies for the truncated pyramid-like structure and the frustum-shaped structure with a curved top surface profile, which helps to ensure a certain degree of macroscopic flatness in the first region 13, preventing heat concentration issues caused by high-temperature lasers in localized areas of the first region 13. It also helps to ensure the complete removal of the first doped semiconductor layer 12 located on the surface of the second region 14 while reducing or even preventing thermal damage to the surface of the second region 14 caused by high-temperature lasers. Furthermore, it also helps to improve the formation quality and passivation effect of the first doped semiconductor layer 12 formed on the first region 13. In addition, in the actual manufacturing process, the boss structure 15 can be obtained by first pre-texturing the first region 13 of the semiconductor substrate 11, and then polishing the pre-formed textured structure 16 to remove the sharp corners at the top of the textured structure 16. Since the textured structure 16 has a shape resembling a quadrangular pyramid or a cone, when at least one boss structure 15 is a quadrangular pyramid structure with a curved top surface profile; and / or when at least one boss structure 15 is a frustum structure with a curved top surface profile, it indicates that no structural defects occurred during the manufacturing of the boss structure 15, which is beneficial to improving the yield of solar cells.

[0055] It should be noted that a truncated pyramid structure with a curved top surface profile can be a truncated pyramid structure with four sides, such as a square, rectangle, parallelogram, or rhombus shape on the bottom surface. The lengths of the different lateral edges in a truncated pyramid structure can be approximately the same, or at least one lateral edge can have a different length than the others. Furthermore, in some truncated pyramid structures with a curved top surface profile, the bottom surface shape can be circular or a polygon other than a quadrilateral; as long as it generally resembles a truncated pyramid shape, it can be considered a truncated pyramid structure. Similarly, in some frustum structures, the bottom surface shape can be polygonal; as long as it generally resembles a frustum of a cone, it can be considered a frustum of a cone structure.

[0056] In addition, in the first region, at least one boss structure can also be a polygonal frustum structure with a bottom surface and a top surface shape other than a quadrilateral.

[0057] like Figure 5As shown, the height of the boss structure 15 is defined as H, and the one-dimensional dimension of the top surface of the boss structure 15 is W. For example, in at least one boss structure 15, the ratio of H to W can be greater than or equal to 0.1 and less than or equal to 3. This setting prevents the first region 13 and the first doped semiconductor layer 12 from having a small microscopic undulation on the side facing away from the semiconductor substrate 11 due to an excessively small ratio of H to W (i.e., forming a short and stout boss structure). This helps ensure a larger effective contact area and adhesion between the first doped semiconductor layer 12 and the corresponding electrode, improving the bonding stability between the first doped semiconductor layer 12 and the corresponding electrode in a local area of ​​the semiconductor substrate 11, and preventing electrode detachment. In addition, it can prevent the roughness of the first region 13 from being too large due to an excessively large ratio of H to W, resulting in H being too large and / or W being too small (i.e. forming a tall and thin boss structure). This helps to ensure that the surface of the first region 13 has a certain degree of macroscopic flatness, prevents the problem of heat concentration in the local area of ​​the high-temperature laser in the first region 13, and reduces or even prevents the high-temperature laser from causing thermal damage to the surface of the second region 14. At the same time, it helps to improve the formation quality and passivation effect of the first doped semiconductor layer 12 on the semiconductor substrate 11.

[0058] For example, in at least one boss structure, H can be greater than or equal to 80 nm and less than or equal to 3000 nm. For instance, H can be 80 nm, 150 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, or 3000 nm, etc. The beneficial effects in this case can be referred to the previously described benefits of preventing H from being too large or too small.

[0059] For example, in at least one boss structure, W can be greater than or equal to 160 nm and less than or equal to 6000 nm. The beneficial effects in this case can be referred to the beneficial effects of preventing W from being too large or too small as described above.

[0060] For example, in at least one boss structure, the angle between the side edge and the top surface can be greater than or equal to 125° and less than or equal to 140°. For instance, in a boss structure, the angle between the side edge and the top surface can be 125°, 126°, 127°, 128°, 130°, 132°, 134°, 136°, 138°, or 140°, etc. It is understood that the angle between the side edge and the top surface affects the steepness of the side surface of the boss structure itself. Specifically, the larger the angle between the side edge and the top surface, the slower the change in height of the side surface of the boss structure, and the smaller the specific surface area of ​​the first region. Conversely, the smaller the angle between the side edge and the top surface, the steeper the change in height of the side surface of the boss structure, and the larger the specific surface area of ​​the first region. Based on this, when the angle between the side edge and the top surface of the boss structure is within the above range, it is beneficial to make the first region have a certain degree of micro-undulation, thereby improving the light trapping effect of the first region; at the same time, it is beneficial to increase the bonding pull between the first doped semiconductor layer disposed on the first region and the corresponding electrode, thereby preventing the electrode from falling off.

[0061] Regarding the surface morphology of the second region, the embodiments of the present invention do not specifically limit the surface morphology of the second region, as long as the surface morphology of the first region and the second region are different.

[0062] For example, the surface reflectivity of the second region is lower than that of the first region. This configuration allows the surface of the second region to have a higher light-trapping effect, enabling the first surface of the solar cell to simultaneously achieve high deposition quality and passivation effect of the first doped semiconductor layer, high-yield patterning processing, and stable bonding performance between itself and the electrode, as well as the high light-trapping effect of the second region surface, thereby improving the overall performance of the solar cell.

[0063] For example, the second region may have a velvety surface. The application principle of the beneficial effect in this case can be referred to the application principle of the beneficial effect of the second region having a lower surface reflectance than the first region, as described above, and will not be repeated here.

[0064] Regarding the textured surface structure in the second region, this embodiment of the invention does not specifically limit the morphology and size of the textured surface structure, but can determine it according to the requirements of the light-trapping and passivation effects of the second region in the actual application scenario. For example, the textured surface structure in the second region can be a pyramid-shaped structure, a porous structure, a V-groove structure, or a nano-columnar textured surface structure, etc.

[0065] The surface reflectivity of the first and second regions can be determined based on the laser etching damage requirements of the second region, the formation quality and passivation effect of the first doped semiconductor layer, the patterning treatment of the first doped semiconductor layer, the bonding performance between the first doped semiconductor layer and the corresponding electrode, and the requirements for the light trapping and passivation effects of the second region.

[0066] For example, the surface reflectivity of the first region can be greater than or equal to 10% and less than or equal to 40%. For instance, the surface reflectivity of the first region can be 10%, 12%, 15%, 18%, 20%, 22%, 25%, 26%, 28%, 30%, 32%, 35%, 38%, or 40%, etc. This setting, with the surface reflectivity of the first region within the aforementioned range, prevents the surface of the first doped semiconductor layer on the side facing away from the semiconductor substrate from becoming too flat due to excessively high surface reflectivity (preventing the reflectivity of the first region from being greater than or equal to the reflectivity of a conventional polished surface). This helps to increase the effective contact area and bonding force between the first doped semiconductor layer on the first region and the corresponding electrode, preventing electrode detachment. Furthermore, this method can prevent the first region from having excessively low surface reflectivity (preventing the reflectivity of the first region from being less than or equal to that of the second region), resulting in a high degree of roughness. If the manufacturing method described above is adopted, firstly forming a boss structure on the entire first surface and depositing the first doped semiconductor layer layer across the entire surface, and then patterning the first doped semiconductor layer before texturing the second region, it can also prevent the second region from having excessive roughness due to laser processing. This would prevent over-etching of the top surface of the boss structure corresponding to the first doped semiconductor layer, causing thermal damage, and / or incomplete removal of the bottom portion of the boss structure corresponding to the first doped semiconductor layer. This helps ensure complete removal of the first doped semiconductor layer in the second region while reducing or even preventing thermal damage to the second region caused by high-temperature lasers, thus improving the yield of the solar cell. Simultaneously, it helps improve the deposition quality and passivation effect of the first doped semiconductor layer in the first region.

[0067] In some embodiments, such as Figures 2 to 4As shown, along the direction from the second surface to the first surface, the surface height of the first region 13 can be greater than the surface height of the second region 14. With this configuration, in the actual manufacturing process, the manufacturing method described above can be adopted. First, a boss structure 15 is formed on the entire surface of the first surface, and a first doped semiconductor layer 12 is deposited in its entirety. Then, after patterning the first doped semiconductor layer 12, the second region 14 is morphologically shaped, thereby forming a boss structure 15 in the first region 13 and making the surface morphology of the second region 14 different from that of the first region 13. This allows the morphology of the first region 13 and the second region 14 in the solar cell to simultaneously meet the corresponding working requirements (e.g., high deposition quality and high passivation effect of the first doped semiconductor layer 12, high-yield patterning treatment and stable bonding performance between itself and the electrode, and high light-trapping effect of the surface of the second region 14), improving the overall performance of the solar cell.

[0068] It should be noted that, along the direction from the second surface to the first surface, the surface height of the first region can be greater than the surface height of the second region. This means that the height of the top surface of the boss structure set in the first region is greater than the maximum surface height of the boss structure set in the second region (for example, if a velvet structure is set on the surface of the second region, it is the top height of the velvet structure).

[0069] As for the surface height difference between the first region and the second region, it can be set according to the surface morphology of the second region and the actual needs, and no specific limitation is made here.

[0070] For example, along the direction from the second surface to the first surface, the surface height difference between the first region and the second region can be greater than or equal to 1 μm and less than or equal to 10 μm. This configuration, with the surface height difference between the first and second regions within this range, prevents impurities from the manufacturing of the first doped semiconductor layer from remaining in the second region due to an excessively small surface height difference, reducing carrier recombination and ensuring higher conversion efficiency of the solar cell. Furthermore, it prevents the surface height difference between the first and second regions from becoming too large. Because the textured structure of the second region is a boss structure when the first doped semiconductor layer is removed using laser technology, the thermal damage to the semiconductor substrate corresponding to the second region by the high-temperature laser is minimal or even non-existent. This eliminates the need to remove or only requires the removal of a thin damaged layer, reducing the surface height difference between the first and second regions, improving the mechanical strength and light absorption depth of the semiconductor substrate corresponding to the second region, and facilitating thin-film production.

[0071] In some embodiments, such as Figure 3 and Figure 4As shown, in the second region 14, a ridge structure 20 can be provided on the second edge sub-region 19 near the first region 13. The inclination direction of the ridge structure 20 is parallel to the extension direction of the side edge of the boss structure 15 near the second region 14. It can be understood that the first region 13 is provided with a boss structure 15 with a flat top surface, making the first region 13 macroscopically flat; while the morphology of the second region 14 is different from the surface morphology of the first region 13, and there is a certain difference between the two. Based on this, the second edge region surface near the first region 13 in the second region 14 is provided with a ridge structure 20. This ridge structure 20 refers to a protruding structure whose length along its own side edge is more than 1.5 times greater than the length of the opposite side edge edge, and the inclination direction of the ridge structure 20 is parallel to the extension direction of the side edge of the boss structure 15 near the second region 14. At this point, setting the ridge structure 20 as a structural transition between the first region 13 and the second region 14 can help improve the quality of the passivation layer deposited on the surface of the edge sub-region, reduce the number of defects on the surface of the edge sub-region, and reduce the carrier recombination rate.

[0072] Alternatively, in the second region, the second edge sub-region near the first region can also be provided with a velvet structure.

[0073] For example, such as Figure 4 As shown, in the first region 13, the first edge sub-region 21 near the ridge structure 20 is set as a plateau region 22. With this setting, the surfaces of the ridge structure 20 and the plateau region 22 are flatter than the textured structure 16, which is beneficial to improving the formation quality of the passivation layer, and the conformal deposition coverage is better. This can improve the surface passivation effect of the passivation layer at the junction of the first region 13 and the second region 14, and reduce the carrier recombination rate.

[0074] The width of the platform area can be determined based on the passivation requirements at the junction of the first and second areas in the actual application scenario, and no specific limitation is made here.

[0075] Of course, in practical applications, a boss structure can also be set on the first edge sub-region included in the first region.

[0076] As for the formation range of the first doped semiconductor layer on the first surface, it can be determined according to the requirements of the carrier collection capability and parasitic absorption of the first doped semiconductor layer in the actual application scenario.

[0077] For example, such as Figure 6As shown, the first doped semiconductor layer 12 may include first strip-shaped portions 17 extending along a first direction and spaced apart along a second direction. The first direction intersects the second direction. Specifically, the first direction and the second direction can be any two directions parallel to the first surface and different from each other. Optionally, the first direction and the second direction are perpendicular. For example, when the first surface is rectangular, the first direction and the second direction are parallel to the extension directions of two intersecting sides of the rectangle, respectively. In addition, the solar cell may also include a first current collector 18, which is disposed on the side of the first strip-shaped portion 17 away from the semiconductor substrate 11 to facilitate the discharge of carriers collected by the first doped semiconductor layer 12. In the above case, for example, along the second direction, the ratio between the width of at least one first strip-shaped portion 17 and the width of the first current collector 18 can be greater than or equal to 2 and less than or equal to 100. For example, the ratio between the width of at least one first strip-shaped portion 17 and the width of the first current collector 18 can be 2, 3, 4, 5, 8, 10, 20, 50, 80, 90, or 100, etc. This configuration ensures that the ratio between the width of at least one first strip 17 and the width of the first collector electrode 18 is within the aforementioned range. This prevents the width of the first strip 17 from being too small and / or the width of the first collector electrode 18 from being too large due to an excessively small ratio. It ensures that the first strip 17 has a certain width, thus providing it with a certain carrier collection capability, and reduces the precision requirements for manufacturing the first collector electrode 18 on the first strip 17. Furthermore, it prevents the width of the first strip 17 from being too large and / or the width of the first collector electrode 18 from being too small due to an excessively large ratio. This helps reduce parasitic absorption in the first doped semiconductor layer 12 and ensures that the first collector electrode 18 has a certain width. This, in turn, helps increase the bonding pull between the first collector electrode 18 and the first strip 17, preventing the first collector electrode 18 from detaching.

[0078] For example, the ratio between the width of at least one first strip and the distance between two adjacent first strips is greater than or equal to 0.02 and less than or equal to 0.5. The application principle of the beneficial effect in this case can be referred to the application principle of the beneficial effect described above where the ratio between the width of at least one first strip and the width of the first current collector is greater than or equal to 2 and less than or equal to 100, which will not be repeated here.

[0079] In some embodiments, such as Figure 7 , Figure 8 and Figure 9 As shown, the solar cell provided in this embodiment of the invention may further include a second doped semiconductor layer 23 with a conductivity type opposite to that of the first doped semiconductor layer 12. The location of the second doped semiconductor layer 23 on the semiconductor substrate 11 can be set according to the type of solar cell and actual needs.

[0080] For example, such as Figure 7 As shown, in the case of a double-sided contact solar cell, the second doped semiconductor layer 23 is disposed on one side of the second surface of the semiconductor substrate 11. Specifically, the second doped semiconductor layer 23 can be disposed on the entire surface of the second surface, or it can be disposed on a partial surface of the second surface.

[0081] For example, such as Figure 8 and Figure 9 As shown, in the case of a back-contact solar cell, the second doped semiconductor layer 23 is disposed on a local area of ​​the first surface of the semiconductor substrate 11. Specifically, the first doped semiconductor layer 12 and the second doped semiconductor layer 23 can be alternately disposed on the first surface in a direction parallel to the first surface. Alternatively, the first doped semiconductor layer and the second doped semiconductor layer can be sidewall-to-side. Or, the second doped semiconductor layer 23 can also cover a portion of the first doped semiconductor layer 12.

[0082] The embodiments of the present invention do not specifically limit the material of the second doped semiconductor layer, and can be set according to actual needs. The materials of the second doped semiconductor layer and the first doped semiconductor layer can be the same or different. For example, both the first and second doped semiconductor layers can include a doped polycrystalline silicon layer. Another example: the first doped semiconductor layer can include a doped polycrystalline silicon layer, and the second doped semiconductor layer includes a doped amorphous silicon layer.

[0083] In addition, such as Figure 8 and Figure 9 As shown, the second doped semiconductor layer 23 can be directly disposed on the semiconductor substrate 11. Alternatively, as... Figure 7 As shown, the solar cell may further include a second interface passivation layer 25, which is located at least between the semiconductor substrate 11 and the second doped semiconductor layer 23 to reduce the carrier recombination rate. The principle governing the material and thickness of the second interface passivation layer 25 can be referenced to the principle governing the material and thickness of the first interface passivation layer 24 described above, and will not be repeated here.

[0084] In some embodiments, such as Figure 10 As shown, the solar cell provided in this embodiment of the invention may further include a surface passivation layer 26. The surface passivation layer 26 covers the first doped semiconductor layer 12 and the first surface to reduce the carrier recombination rate. The material and thickness of the surface passivation layer 26 can be set according to actual needs and are not specifically limited here.

[0085] Secondly, embodiments of the present invention provide a method for manufacturing a solar cell. The following will describe, based on... Figures 11 to 16 The cross-sectional view shown illustrates the manufacturing process. Specifically, the method for manufacturing this solar cell includes: First, a semiconductor substrate is provided. The semiconductor substrate includes a first surface and a second surface disposed opposite to each other. The first surface includes a first region and a second region.

[0086] Next, as Figure 11 and Figure 12 As shown, at least the first surface of the semiconductor substrate 11 is textured to form a plurality of side-by-side boss structures 15 with curved top surface contours on the first surface.

[0087] The morphology of the boss structure can be referred to the previous text and will not be repeated here. In the actual manufacturing process, for example, texturing at least the first surface of the semiconductor substrate may include the steps of performing pre-texturing and polishing processes on at least the first surface of the semiconductor substrate. Specifically, a first etching solution (such as a mixture of sodium hydroxide and / or potassium hydroxide solution, texturing additive, and water) can be used to pre-texturize at least the first surface of the semiconductor substrate, forming a textured structure with sharp corners on at least the first surface. Next, a second etching solution (such as a mixture of sodium hydroxide and / or potassium hydroxide solution, smoothing additive, and water) can be used to polish at least the first surface of the semiconductor substrate to remove the sharp corners at the top of the textured structure, obtaining multiple boss structures arranged side by side with curved top surface contours. The size of the boss structure can be controlled by adjusting the process temperature, process time, and the ratio of different components in the first and second etching solutions, thereby controlling the roughness of the first region. In this embodiment of the invention, the proportions of different components in the first and second etchants and parameters such as process time are not specifically limited, but can be determined according to the size requirements of the boss structure in the actual application scenario.

[0088] Next, as Figures 13 to 15 As shown, a first doped semiconductor layer 12 is formed on the first surface in a continuous manner. A laser process is then used to pattern the first doped semiconductor layer 12 to remove the first doped semiconductor layer 12 located on the second region 14.

[0089] In the actual manufacturing process, deposition and doping processes can be used to first form a first doped semiconductor layer on the first surface. Then, a first mask layer is formed on the first doped semiconductor layer. Next, a laser process can be used to pattern the first doped semiconductor layer and remove the first doped semiconductor layer located in the second region. It is worth noting that during the patterning process of the first doped semiconductor layer, the texture structure set on the second region is also a boss structure with a flat top surface and a curved top surface contour. This is to prevent the problem of over-etching of the top surface of the corresponding boss structure of the first doped semiconductor layer and / or incomplete removal of the bottom part of the corresponding boss structure of the first doped semiconductor layer due to excessive surface roughness in the second region. This helps to ensure that the first doped semiconductor layer located in the second region is completely removed while reducing or even preventing thermal damage to the second region caused by high-temperature laser, thereby improving the yield of solar cells.

[0090] It should be noted that the manufactured solar cell also includes a first interface passivation layer. A first doped semiconductor layer is formed on the first surface, which requires deposition or other processes to first form the first interface passivation layer on the first surface. The first interface passivation layer is a tunneling oxide layer.

[0091] Next, as Figure 16 As shown, the second region 14 can also be texturing to form a texturing structure 16. Texturing reduces the surface reflectivity of the second region 14 and improves its light-trapping effect. The types and dimensions of the texturing structure 16 can be found above and will not be repeated here.

[0092] As for the proportions of different components in the third etching solution (such as a mixture of sodium hydroxide and / or potassium hydroxide solution, texturing additives and water) used for texturing the second region, as well as parameters such as the process duration, these can be set according to actual needs such as the size of the texturing structure.

[0093] In addition, when the solar cell also includes a second doped semiconductor layer, the manufacturing sequence and process of the second doped semiconductor layer can be determined according to the range of the second doped semiconductor layer on the semiconductor substrate and the actual requirements.

[0094] For example, in the case of a double-sided contact solar cell, a second doped semiconductor layer can be formed on the second surface of the semiconductor substrate using deposition and doping processes, either before or after the formation of the first doped semiconductor layer. If the second doped semiconductor layer is disposed in a local area of ​​the second surface, it can be patterned using laser etching, printing etchant etching, or photolithography combined with wet etching.

[0095] For example, in the case where the solar cell is a back-contact cell, such as Figure 8 and Figure 9 As shown, after forming the first doped semiconductor layer 12, a second doped semiconductor layer can be formed on the first surface using processes such as deposition and doping. Then, the patterning process of the second doped semiconductor layer 23 can be achieved by patterning the first doped semiconductor layer 12 as described above.

[0096] It should be noted that if the manufactured solar cell also includes a second interface passivation layer, then before forming the second doped semiconductor layer, a deposition process or similar process is required to first form the second interface passivation layer on the corresponding surface.

[0097] In some embodiments, such as Figure 10 As shown, if the manufactured back contact battery also includes a surface passivation layer 26, then after forming the first doped semiconductor layer 12, a process such as chemical vapor deposition can be used to form the surface passivation layer 26 on the first surface. The material and thickness of the surface passivation layer 26 can be referred to the previous text.

[0098] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0099] Thirdly, embodiments of the present invention provide a photovoltaic module, which includes: a battery string and an encapsulation layer. The battery string is formed by electrically connecting multiple solar cells as provided in the first aspect and its various implementations; the encapsulation layer covers the surface of the battery string.

[0100] The beneficial effects of the third aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0101] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0102] The embodiments of the present invention have been described above. However, these embodiments are merely for clarity and are not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A solar cell, characterized by, The semiconductor substrate comprises a first surface and a second surface arranged oppositely; the first surface comprises a first region and a second region; a first doped semiconductor layer is arranged on the first region; wherein the first region is provided with a plurality of bump structures distributed side by side and having a curved top surface profile; and the surface topography of the second region is different from that of the first region. At least one of the bump structures is a quadrangular prism-like structure with a curved top surface profile; and / or, at least one of the bump structures is a circular prism-like structure with a curved top surface profile.

2. The solar cell according to claim 1, characterized in that, The height of the bump structure is H, and the one-dimensional size of the top surface of the bump structure is W; 3. The solar cell according to claim 1, characterized in that, wherein, in at least one of the bump structures, the ratio of H to W is greater than or equal to 0.1 and less than or equal to 3; and / or, in at least one of the bump structures, H is greater than or equal to 80 nm and less than or equal to 3000 nm; and / or, in at least one of the bump structures, W is greater than or equal to 160 nm and less than or equal to 6000 nm. In the bump structure, the included angle between the side edge and the top surface is greater than or equal to 125° and less than or equal to 140°.

4. The solar cell of claim 1, wherein The surface reflectivity of the first region is greater than or equal to 10% and less than or equal to 40%.

5. The solar cell of claim 1, wherein In the direction from the second surface to the first surface, the surface height of the first region is greater than that of the second region.

6. The solar cell of claim 1, wherein In the direction from the second surface to the first surface, the surface height difference between the first region and the second region is greater than or equal to 1 μm and less than or equal to 10 μm.

7. The solar cell according to claim 6, characterized in that, The first doped semiconductor layer comprises a first strip-shaped part extending in a first direction and spaced apart in a second direction; the first direction intersects the second direction; 8. The solar cell of claim 1, wherein, wherein the solar cell further comprises a first collecting electrode arranged on the side of the first strip-shaped part away from the semiconductor substrate; and / or, in the second direction, the ratio between the width of at least one of the first strip-shaped parts and the width of the first collecting electrode is greater than or equal to 2 and less than or equal to 100; and / or, the ratio between the width of at least one of the first strip-shaped parts and the spacing between adjacent two first strip-shaped parts is greater than or equal to 0.02 and less than or equal to 0.

5. The surface reflectivity of the second region is less than that of the first region; 9. The solar cell of claim 1, wherein, and / or, the second region is provided with a textured structure. In the second region, a second edge sub-region close to the first region is provided with a ridge line structure, and the inclination direction of the ridge line structure is parallel to the extension direction of the side edge of the bump structure.

10. The solar cell according to claim 4 or 9, characterized in that, In the first region, a first edge sub-region close to the ridge line structure is provided as a platform region.

11. The solar cell of claim 10, wherein, The semiconductor substrate is provided; 12. A method for manufacturing a solar cell, characterized by, The semiconductor substrate comprises a first surface and a second surface arranged oppositely; the first surface comprises a first region and a second region; At least the first surface of the semiconductor substrate is subjected to a texturing treatment to form a plurality of bump structures distributed side by side and having a curved top surface profile on the first surface; A first doped semiconductor layer is formed on the first surface; A laser process is adopted to patternize the first doped semiconductor layer to remove the first doped semiconductor layer on the second region. ​ ​ 13. The method of manufacturing a solar cell according to claim 12, wherein The texturing process is performed on at least the first surface of the semiconductor substrate, including: At least the first surface of the semiconductor substrate is subjected to pre-texturing and polishing processes in sequence.

14. The method of manufacturing a solar cell according to claim 12, wherein After patterning the first doped semiconductor layer, the method for manufacturing the solar cell further includes: The second region is subjected to a flocking process to form a flocked structure in the second region.

15. A photovoltaic module, characterized by, include: A battery string, wherein the battery string is formed by electrically connecting a plurality of solar cells as described in any one of claims 1 to 11; And an encapsulation layer that covers the surface of the battery string.

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