A chip module, electronic device

Abstract

The application discloses a chip module and an electronic device, and relates to the technical field of semiconductors, wherein the chip module comprises a first circuit board, an interposer, a second circuit board and a first chip; the second circuit board is electrically connected with the first circuit board through the interposer, and the second circuit board is also electrically connected with the first chip. The application can electrically connect the first chip with the second circuit board, increase the storage capacity without significantly increasing the physical size, support high-speed data transmission and maintain signal integrity; the second circuit board is connected with the first circuit board through the interposer, the vertical interconnection technology not only saves space, but also shortens the signal path, thereby improving the data transmission rate and signal quality; since the first chip generates heat during operation, the structure that the edges of the second circuit board are connected with the interposer improves the heat dissipation efficiency of the first chip.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a chip module and an electronic device. Background Technology

[0002] In mobile phone and automotive cockpit scenarios, the interconnect design of Double Data Rate (DDR) memory is crucial because it directly affects system performance, responsiveness, and overall user experience.

[0003] In related technologies, because Dynamic Random Access Memory (DRAM) occupies a large area on the first circuit board, the signal integrity (SI) quality of the channels in DDR memory is poor, and it also affects the heat dissipation effect in DDR memory.

[0004] new content

[0005] In a first aspect, this disclosure provides a chip module, including: a first circuit board, an interposer layer, a second circuit board, and a first chip;

[0006] The second circuit board is electrically connected to the first circuit board through the interlayer, and the second circuit board is electrically connected to the first chip, with the first chip located on the side of the second circuit board away from the first circuit board.

[0007] In one embodiment of this disclosure, a chip packaging structure is also included;

[0008] The chip package structure is electrically connected to the first circuit board, and the package structure is located on the side of the first circuit board away from the first chip.

[0009] In one embodiment of this disclosure, the chip packaging structure includes a packaging substrate and a second chip on the packaging substrate;

[0010] The packaging substrate is electrically connected to the first circuit board.

[0011] In one embodiment of this disclosure, the interposer layer includes a first dielectric block and a second dielectric block, the first dielectric block and the second dielectric block being located at opposite ends of the first circuit board.

[0012] In embodiments of this disclosure, the first dielectric block and the second dielectric block are disposed separately on the same plane.

[0013] In the embodiments of this disclosure, the chip packaging structure communicates with the first chip through multiple vertical through-holes via the first circuit board, the interposer layer, and the second circuit board.

[0014] In the embodiments of this disclosure, multiple signal lines satisfying a predetermined ground-to-signal ratio condition are provided in the multiple vertical through holes;

[0015] The chip is interconnected with the first chip via the plurality of signal lines.

[0016] In embodiments of this disclosure, the first chip includes a memory chip.

[0017] In embodiments of this disclosure, the second chip includes a logic chip.

[0018] A second aspect of this disclosure provides an electronic device, characterized in that it includes the chip module described in the first aspect of claim.

[0019] By employing the above technical solutions, this application provides a chip module and electronic device. Compared with the prior art, this application adds a second circuit board to the chip module, which can electrically connect the first chip to the second circuit board. This allows the chip module to increase its storage capacity without significantly increasing its physical size, while also supporting high-speed data transmission and maintaining signal integrity. The second circuit board is connected to the first circuit board through an interposer. This vertical interconnection technology not only saves space but also shortens the signal path, thereby improving data transmission rate and signal quality. Since the memory generates heat during operation, the structure of using the second circuit board to connect the interposer improves the heat dissipation efficiency of the memory.

[0020] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, specific embodiments of this application are given below. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0022] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This paper shows a schematic diagram of the structure of a chip module provided in an embodiment of this application;

[0024] Figure 2This illustration shows a structural diagram of an example provided in an embodiment of this application;

[0025] Figure 1 middle:

[0026] 1-First circuit board;

[0027] 2-Intermediate layer;

[0028] 3-Second circuit board;

[0029] 4-First chip;

[0030] 5-Chip. Detailed Implementation

[0031] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0032] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0033] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0034] The present application will be described in detail below with reference to the accompanying drawings and embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in the embodiments of the present application can be combined with each other.

[0035] The following is combined with Figure 1 This application describes a chip module according to some embodiments.

[0036] This application provides a chip module, such as Figure 1 As shown, it includes: a first circuit board 1, an interposer 2, a second circuit board 3, and a first chip 4; the second circuit board 3 is electrically connected to the first circuit board 1 through the interposer 2, and the second circuit board 3 is also electrically connected to the first chip 4.

[0037] In this embodiment, the first circuit board 1 can be a modular printed circuit board (PCB). A modular PCB is a fundamental component in electronic devices used to support and connect various electronic components. To meet complex interconnection requirements, modular PCBs typically employ a multi-layer design. Each layer can be dedicated to a different function, such as a signal layer, power layer, and ground layer. This not only helps optimize wiring but also improves signal integrity and reduces electromagnetic interference.

[0038] In some examples, the interposer board 2 can be used to connect different chips or circuit boards, and the specific interposer board 2 can provide electrical connections between different types of packages.

[0039] In this embodiment, in an interconnect design from a SOC chip to a memory chip (such as a DDR chip), interposer layer 2 is used to support the connection between the module board and the chip board, while ensuring efficient signal transmission in the vertical direction. This design not only optimizes channel interconnection but also improves the overall system performance and stability while maintaining signal integrity.

[0040] In the embodiments of this disclosure, the interposer layer has a cutout area. Exemplarily, the cutout area is located in the middle of the interposer layer so that the edge of the second circuit board 3 is connected to the interposer layer 2. It should be noted that the second circuit board 3 located at both ends of the edge can be obtained by hollowing out, which is not specifically limited here.

[0041] In embodiments of this disclosure, a first dielectric block and a second dielectric block are located at opposite ends of the first circuit board. In embodiments of this disclosure, the first dielectric block and the second dielectric block are disposed separately on the same plane.

[0042] As an alternative, the second circuit board 3 can be a PCB designed for mounting the first chip 4. In this embodiment, using the second circuit board 3 allows for increased storage capacity without significantly increasing physical size, and can also support high-speed data transmission while maintaining signal integrity. The second circuit board 3 is connected to the first circuit board 1 through the interposer layer 2. This vertical interconnect technology not only saves space but also shortens the signal path, thereby improving data transmission rate and signal quality. In addition, since the first chip 4 generates heat during operation, the second circuit board 3 usually considers heat dissipation design to improve the heat dissipation efficiency of the first chip 4.

[0043] In this embodiment, the first chip 4 can be Dynamic Random Access Memory (DRAM), a widely used memory technology in computer systems. Unlike Static RAM (SRAM), DRAM requires periodic refreshing to maintain data integrity. This is because each storage cell in DRAM consists of a transistor and a capacitor, and the capacitor will gradually leak current over time, leading to data loss. Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM) is one of the most commonly used types of DRAM.

[0044] In some examples, an electrical connection can be a physical connection in an electronic device or system used to enable the transmission of electrical signals or power. These connections can be temporary or permanent and are designed to ensure that electrical signals can be transmitted efficiently and reliably from one point to another.

[0045] It's important to note that electrical connections play a crucial role in the interconnect design from the SOC chip to the DDR memory chip. Through electrical connections, vertical vias can be drilled on the module PCB, and the signal travels through the interposer board and the chip board before reaching the DDR chip, achieving efficient channel interconnection. This method not only saves space but also shortens the signal path, contributing to improved data transmission rate and signal integrity. It also maintains a 1:1 signal-to-ground ratio. Specifically, to reduce crosstalk between vias and improve the channel's SI (Signal Integrity) quality, a 1:1 signal-to-ground ratio is adopted. This means that each signal line has a corresponding ground line as a reference, thereby reducing interference and ensuring high-quality data transmission.

[0046] Compared with existing technologies, this embodiment adds a second circuit board to the chip module, which can electrically connect the first chip to the second circuit board. This allows the chip module to increase its storage capacity without significantly increasing its physical size, while also supporting high-speed data transmission and maintaining signal integrity. The second circuit board is connected to the first circuit board through an interposer. This vertical interconnect technology not only saves space but also shortens the signal path, thereby improving data transmission rate and signal quality. Since the memory generates heat during operation, the structure of using the second circuit board to connect the interposer improves the heat dissipation efficiency of the memory.

[0047] Optionally, the chip module in this embodiment of the application further includes a chip packaging structure 5; the chip packaging structure 5 is electrically connected to the first circuit board 1.

[0048] For example, the chip packaging structure includes a packaging substrate and a second chip. The packaging substrate is connected to a first circuit board 1, and the second chip is located on the side of the packaging substrate away from the first circuit board.

[0049] For example, the second chip includes a memory chip.

[0050] In this embodiment, the chip package structure 5 can be considered as a system-on-a-chip (SOC). An SOC is an integrated circuit that integrates all components of a computer or other electronic system onto a single chip. An SOC may include multiple processor cores (such as CPU, GPU), memory controllers, input / output interfaces, communication modules (such as Wi-Fi, Bluetooth), sensor interfaces, and other dedicated accelerators. This high degree of integration reduces the need for external components and helps reduce the overall size of the system. Because all components are integrated on a single chip, the SOC can manage power consumption more effectively.

[0051] In some examples, when interconnecting with DDR (Double Data Rate) chips, the SOC can be directly connected to the DDR chip without the need for an additional chipset or bridge. This approach reduces latency and improves data transmission speed. Alternatively, vertical vias can be used to penetrate the interposer board and the chip board to achieve efficient channel interconnection from the SOC to the DDR chip. In this embodiment, the interconnection between the SOC and the DDR chip is achieved through vertical vias, which not only shortens the signal path but also allows for complex functional layouts within a compact space.

[0052] The chip packaging structure 5 is optional. The first circuit board 1 and the second circuit board 3 both include a first surface and a second surface arranged in the same direction. The chip packaging structure is interconnected with the first surface of the first circuit board 1, and the first chip 4 is located on the side of the second circuit board away from the first circuit board 1.

[0053] For example, the same orientation can be such that the front faces of the first circuit board 1 and the second circuit board 3 are the same, and correspondingly, the back faces of the first circuit board 1 and the second circuit board 3 are also the same.

[0054] In some examples, the first side can be the front of the first circuit board 1 and the second circuit board 3, and the second side can be the back of the first circuit board 1 and the second circuit board 3; conversely, the first side can be the back of the first circuit board 1 and the second circuit board 3, and the second side can be the front of the first circuit board 1 and the second circuit board 3, without any specific limitation.

[0055] In this embodiment, the chip package structure and the first surface of the first circuit board 1 can be interconnected by solder balls or copper pillars.

[0056] It's important to note that when using solder pads for connection, the solder pads serve as the direct physical and electrical connection points between the SOC PKG and the PCB, ensuring accurate data transfer from the SOC to the DDR chips. When using vertical drilling technology to penetrate the interposer board and the chip board, the solder pads provide stable start and end points, guaranteeing an effective signal path. Careful design of the solder pad placement and layout can optimize the overall system routing, shorten signal path lengths, reduce latency, and improve overall performance.

[0057] Optionally, the two ends of the edge of the second side of the first circuit board 1 are electrically connected to the intermediate layer 2, and the intermediate layer 2 is electrically connected to the two ends of the edge of the first side of the second circuit board 3.

[0058] In this embodiment of the application, if the first side is the front side of the first circuit board 1 and the second circuit board 3, and the second side is the back side of the first circuit board 1 and the second circuit board 3, then the two ends of the edge of the back side of the first circuit board 1 are electrically connected to the intermediate layer 2, and the intermediate layer 2 is electrically connected to the two ends of the edge of the front side of the second circuit board 3.

[0059] For example, if the first side is the back side of the first circuit board 1 and the second circuit board 3, and the second side is the front side of the first circuit board 1 and the second circuit board 3, then the two ends of the front edge of the first circuit board 1 are electrically connected to the intermediary layer 2, and the intermediary layer 2 is electrically connected to the two ends of the back edge of the second circuit board 3.

[0060] Optionally, the second side of the second circuit board 3 is interconnected with the first chip 4.

[0061] In this embodiment, the second side of the second circuit board 3 and the first chip 4 can be interconnected by solder balls or copper pillars.

[0062] In some examples, the connection between the second circuit board 3 and the first chip 4 is typically achieved using ball grid array (BGA) packaging technology. In this setup, solder pads play a crucial role; they are metal contact points located on the second circuit board 3, connected to the solder pads on the bottom of the first chip 4 via solder balls.

[0063] Optionally, the chip package structure 5 is interconnected with the first chip 4 through multiple vertical through-holes via the first circuit board 1, the interposer layer 2, and the second circuit board 3.

[0064] In this embodiment, the channel interconnect design between the chip package structure 5 and the first chip 4 is crucial for achieving efficient data transmission. This interconnect not only needs to ensure high-speed data transmission rates but also needs to guarantee signal integrity and system stability.

[0065] Chip package structure 5 typically employs BGA packaging technology, featuring numerous solder balls on its bottom. These solder balls are directly soldered to corresponding pads on the first circuit board 1. The first chip 4 often uses a similar BGA packaging method, allowing it to be directly mounted on the second circuit board 3 or the first circuit board 1. Channel interconnection is achieved by vertically drilling through the first solder balls in chip package structure 5, passing through the interposer layer 2 and the second circuit board 3, to reach the first chip 4. This method shortens the signal path, reduces latency, and improves data transmission efficiency. This design allows for a more compact connection between the SOC and DRAM, while also contributing to optimized signal integrity.

[0066] For example, such as Figure 2 The diagram shows the interface connection between chip package structure 5 and the first chip 4. The diagram illustrates the main signal lines and power lines between them. 1. Power Lines: VDD2C, VDD, and VDDQ are power lines, representing different power supply voltages. VSS is the ground line, used to provide the circuit's reference potential. 2. Data Lines: DQ data line is used for data transmission. WRCK write clock line is used to control the timing of write operations. RDQS read strobe signal line is used for synchronization of read operations. 3. Address and Control Lines: CA command / address line is used to send command and address information. CS chip select signal line is used to select a specific memory chip. CK clock line is used to synchronize data transmission. REST reset signal line is used to initialize or reset the memory.

[0067] Optionally, multiple signal lines satisfying a predetermined ground-to-signal ratio condition are provided in multiple vertical vias; the chip package structure 5 is interconnected with the memory through multiple signal lines.

[0068] In this embodiment, the predetermined signal-to-ground ratio condition can be to maintain a 1:1 ratio. Specifically, maintaining a 1:1 ratio (i.e., the ratio of signal lines to ground lines) during the design process helps reduce crosstalk and improve SI quality. Properly arranging the positions of signal lines and ground lines can effectively reduce electromagnetic interference and ensure high-quality data transmission.

[0069] Compared with existing technologies, this embodiment adds a second circuit board to the chip module, which can electrically connect the first chip to the second circuit board. This allows the chip module to increase its storage capacity without significantly increasing its physical size, while also supporting high-speed data transmission and maintaining signal integrity. The second circuit board is connected to the first circuit board through an interposer. This vertical interconnect technology not only saves space but also shortens the signal path, thereby improving data transmission rate and signal quality. Since the memory generates heat during operation, the structure of connecting the interposer to the edges of the second circuit board improves the heat dissipation efficiency of the memory.

[0070] Based on the above-described chip module, this application embodiment also provides a chip that includes the above-described chip module.

[0071] Optionally, embodiments of this application also provide an electronic device, which includes the above-described chip module or the above-described chip.

[0072] Optionally, the aforementioned electronic device may also include a user interface, a network interface, a camera, radio frequency (RF) circuitry, sensors, audio circuitry, a Wi-Fi module, etc. For example, the aforementioned electronic device may be a mobile terminal, a vehicle, etc. The user interface may include a display screen, an input unit such as a keyboard, etc. Optional user interfaces may also include USB interfaces, card reader interfaces, etc. The network interface may optionally include standard wired interfaces, wireless interfaces (such as Wi-Fi interfaces), etc.

[0073] Those skilled in the art will understand that the physical device structure provided in this embodiment does not constitute a limitation on the physical device, and may include more or fewer components, or combine certain components, or have different component arrangements.

[0074] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms, or it can be implemented by hardware. By applying the solution of this embodiment, compared with the prior art, this embodiment adds a second circuit board to the chip module, which can electrically connect the memory to the second circuit board, so that the chip module can increase the storage capacity without significantly increasing the physical size, and can also support high-speed data transmission and maintain signal integrity; the second circuit board is connected to the first circuit board through an interposer layer. This vertical interconnection technology not only saves space, but also shortens the signal path, thereby improving the data transmission rate and signal quality; since the memory generates heat during operation, the structure of connecting the interposer layer at both ends of the edge of the second circuit board improves the heat dissipation efficiency of the memory.

[0075] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0076] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A chip module, characterized in that, include: First circuit board, interposer layer, second circuit board and first chip; The second circuit board is electrically connected to the first circuit board through the interlayer, and the second circuit board is electrically connected to the first chip, with the first chip located on the side of the second circuit board away from the first circuit board.

2. The chip module according to claim 1, characterized in that, It also includes chip packaging structure; The chip package structure is electrically connected to the first circuit board, and the package structure is located on the side of the first circuit board away from the first chip.

3. The chip module according to claim 2, characterized in that, The chip packaging structure includes a packaging substrate and a second chip on the packaging substrate; The packaging substrate is electrically connected to the first circuit board.

4. The chip module according to claim 1, characterized in that, The interposer layer is divided into a first dielectric block and a second dielectric block, which are located at opposite ends of the first circuit board; and / or, the first dielectric block and the second dielectric block are disposed separately on the same plane.

5. The chip module according to claim 1, characterized in that, The intermediate layer has a hollowed-out area.

6. The chip module according to claim 2, characterized in that, The chip packaging structure communicates with the first chip through multiple vertical through-holes via the first circuit board, the interposer layer, and the second circuit board.

7. The chip module according to claim 6, characterized in that, The plurality of vertical through holes are provided with a plurality of signal lines that meet a predetermined ground-to-signal ratio condition; The chip is interconnected with the first chip via the plurality of signal lines.

8. The chip module according to any one of claims 1-7, characterized in that, The first chip includes a memory chip.

9. The chip module according to claim 3, characterized in that, The second chip includes a logic chip.

10. An electronic device, characterized in that, The chip module includes any one of claims 1 to 9.

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