An FPGA development board circuit structure

Abstract

The utility model discloses a FPGA development board circuit structure in the field of FPGA development board, including microprocessor circuit, memory chip and CPLD chip, and microprocessor circuit includes the main control chip power circuit that has main control chip, working instruction circuit, clock circuit, crystal oscillator circuit, reset circuit, type c interface circuit and JTAG interface circuit, and the main control chip is connected to memory chip and CPLD chip respectively. The utility model discloses can be connected with the computer through with a USB -type -C data line to the development board, and the computer can identify the development board into U disc format, so that the code file of packing good can be directly completed by the mode of drag and drop and burn, reduce the entry threshold of FPGA for the youth, can satisfy the general demand of universal developer.

Description

Technical Field

[0001] This utility model relates to the field of FPGA development boards, specifically an FPGA development board circuit structure. Background Technology

[0002] In the current FPGA development process, to burn the software program onto the development board, we need to select different IDEs depending on the development board manufacturer. This process may involve several different software programs, increasing learning and time costs; at the same time, this process is not stable and increases the possibility of errors.

[0003] In current youth education, learning FPGA development boards is undoubtedly beneficial for stimulating teenagers' thinking and hands-on abilities, cultivating their interest in electronics and circuits, and laying a foundation for future physics studies. However, in actual production practice, sufficient knowledge is often required before encountering FPGA development boards. This includes, but is not limited to, students' mastery of basic circuit knowledge, understanding how the development board interacts with the computer, the required software, and how to install and configure it. Therefore, for teenagers, starting to learn FPGA development boards is often quite difficult; in other words, the effort often does not match the reward.

[0004] Therefore, those skilled in the art provide an FPGA development board circuit structure to solve the problems mentioned in the background art. Utility Model Content

[0005] The purpose of this invention is to provide an FPGA development board circuit structure to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, this utility model provides the following technical solution:

[0007] An FPGA development board circuit structure includes a microprocessor circuit, a memory chip, and a CPLD chip. The microprocessor circuit includes a main control chip power supply circuit, a working indicator circuit, a clock circuit, a crystal oscillator circuit, a reset circuit, a Type-C interface circuit, and a JTAG interface circuit. The main control chip is also connected to the memory chip and the CPLD chip respectively.

[0008] The crystal oscillator circuit consists of quartz crystal resonators Y1 and Y2 connected in series with capacitors C7, C8 and C9, C10 respectively. Quartz crystal resonator Y1 is also connected in parallel with a resistor R13. The two ends of the capacitor in the quartz crystal resonator Y1 circuit are connected to ground, while only the capacitor end of the quartz crystal resonator Y2 circuit is connected to ground. The clock signal is input and output from the two ends of the resonator.

[0009] As a further embodiment of this utility model: the main control chip power supply circuit includes a voltage regulator chip and multiple sets of filter circuits, each set of filter circuits being composed of multiple capacitors C connected in parallel and grounded; the working indicator circuit is composed of at least one light-emitting diode (LED) and a resistor R connected in series.

[0010] As a further embodiment of this utility model: the reset circuit consists of a resistor R14, a button U3, and a capacitor C11. One end of the button U3 is grounded, and the other end is connected to the resistor R14 and the capacitor C11 respectively. The other end of the capacitor C11 is grounded, and the other end of the resistor R14 is connected to the power supply circuit of the main control chip.

[0011] As a further aspect of this utility model: the memory chip is an important component for realizing data storage and management, and the CPLD chip is used to implement data logic functions.

[0012] As a further embodiment of this utility model: the switch button is composed of a tactile button SW connected in series with a resistor R, and the button is composed of a color temperature and brightness adjustment button BIN and a resistor R.

[0013] As a further embodiment of this utility model: the Type-C interface circuit has interfaces A4, B9, B4, A9, B8, A5, B7, A6, A7, B6, A8, B5, A1, B1, A12, B12 and S1. Interface A5 in the Type-C interface circuit is connected to ground after being connected to resistor R7. Interfaces A7 and B7 in the Type-C interface circuit are connected to resistor R8. Interfaces A6 and B6 in the Type-C interface circuit are connected to resistor R9. Interfaces A1, B1, A12, B12 and S1 in the Type-C interface circuit are connected to ground.

[0014] As a further embodiment of this invention, the circuit board has 2428 equivalent LTU4s and 3036 flip-flops, which can meet the general requirements of FPGA and has the characteristics of low cost and clear and simple structure.

[0015] Compared with the prior art, the beneficial effects of this utility model are:

[0016] This invention allows the development board to be connected to a computer using a USB-Type-C data cable. The computer can recognize the development board as a USB flash drive, allowing the packaged code files to be directly burned by dragging and dropping. This lowers the barrier to entry for FPGA for teenagers and meets the general needs of most developers. Moreover, the new burning method greatly simplifies the burning process. While keeping the basic development process unchanged, it greatly reduces the workload of developers and lowers the entry barrier. Attached Figure Description

[0017] Figure 1 This is a circuit diagram of the microprocessor circuit in this utility model;

[0018] Figure 2 This is the circuit diagram of the power supply in this utility model;

[0019] Figure 3 This is a circuit diagram of the switch, button, and light-emitting diode in this utility model;

[0020] Figure 4 This is the circuit diagram of BANK1 in this utility model;

[0021] Figure 5 This is the circuit diagram of BANK2 in this utility model;

[0022] Figure 6 This is the circuit diagram of BANK3 in this utility model;

[0023] Figure 7 This is the circuit diagram of BANK0 in this utility model. Detailed Implementation

[0024] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0025] Please see Figures 1-7 In this embodiment of the present invention, an FPGA development board circuit structure includes a microprocessor circuit, a memory chip, and a CPLD chip. The microprocessor circuit includes a main control chip power supply circuit, a working indicator circuit, a clock circuit, a crystal oscillator circuit, a reset circuit, a Type-C interface circuit, and a JTAG interface circuit. The main control chip is also connected to the memory chip and the CPLD chip respectively.

[0026] The crystal oscillator circuit consists of quartz crystal resonators Y1 and Y2 connected in series with capacitors C7, C8 and C9, C10 respectively. Quartz crystal resonator Y1 is also connected in parallel with a resistor R13. The two ends of the capacitor in the quartz crystal resonator Y1 circuit are connected to ground, while only the capacitor end of the quartz crystal resonator Y2 circuit is connected to ground. The clock signal is input and output from the two ends of the resonator.

[0027] The main control chip power supply circuit includes a voltage regulator chip and multiple filter circuits, each filter circuit consisting of multiple capacitors C connected in parallel and grounded; the working indicator circuit consists of at least one light-emitting diode (LED) and a resistor R connected in series.

[0028] The reset circuit consists of a resistor R14, a button U3, and a capacitor C11. One end of the button U3 is grounded, and the other end is connected to the resistor R14 and the capacitor C11 respectively. The other end of the capacitor C11 is grounded, and the other end of the resistor R14 is connected to the power supply circuit of the main control chip.

[0029] The memory chip is an important component for data storage and management, while the CPLD chip is used to implement data logic functions.

[0030] The switch button consists of a touch button SW connected in series with a resistor R, and the button consists of a color temperature and brightness adjustment button BIN and a resistor R.

[0031] The Type-C interface circuit has interfaces A4, B9, B4, A9, B8, A5, B7, A6, A7, B6, A8, B5, A1, B1, A12, B12, and S1. Interface A5 in the Type-C interface circuit is connected to ground after being connected to resistor R7. Interfaces A7 and B7 in the Type-C interface circuit are connected to resistor R8. Interfaces A6 and B6 in the Type-C interface circuit are connected to resistor R9. Interfaces A1, B1, A12, B12, and S1 in the Type-C interface circuit are connected to ground.

[0032] In this embodiment, the circuit board has 2428 equivalent LTU4s and 3036 flip-flops, which can meet the general requirements of FPGAs. It also features low cost and a clear, simple structure. The memory chip is a crucial component for data storage and management. Furthermore, drag-and-drop programming breaks through the constraints of traditional complex programming methods, requiring only a single data cable to complete the programming process.

[0033] Specifically, programming the development board mainly involves programming the CPLD chip that makes up the main functions of the FPGA development board. The PGC4KG CPLD chip is produced by Unisoc, which also releases Pango Design Suite (PDS), an integrated design and development software that supports its entire series of FPGA chips. Programming the FPGA development board based on the PGC4KG chip requires PDS software. However, this application can use PDS to flash the designed firmware (i.e., program that will not change when the development board is reset) onto the FPGA development board (in this case, onto the STM32F103C8Tx MCU chip) via PDS. Then, the MCU can simulate the desktop PDS and directly perform programming. For users, this is equivalent to skipping the process of using PDS, greatly reducing the software learning cost and the complexity of the process.

[0034] In this embodiment, Figures 4-7 The division is based on the pin supply voltage and corresponding functions of the PGC4KG CPLD chip. Each BANK can independently support different I / O standards, and by burning different programs, it can be adapted to different electrical standards and I / O physical characteristics.

[0035] This invention also features a novel programming method. The development board can be connected to a computer using a USB-Type-C data cable. The computer can recognize the development board as a USB flash drive, allowing the packaged code files to be directly programmed via drag-and-drop. This lowers the barrier to entry for FPGAs for teenagers. First, the FPGA development board possesses common development board functions, meeting the general needs of most developers. Second, the novel programming method greatly simplifies the programming process, significantly reducing the workload for developers and lowering the entry barrier while maintaining the basic development workflow.

[0036] The above description is only a preferred embodiment of the present utility model, but the protection scope of the present utility model is not limited thereto. Any equivalent substitutions or changes made by those skilled in the art within the technical scope disclosed in the present utility model, based on the technical solution and the inventive concept of the present utility model, should be included within the protection scope of the present utility model.

Claims

1. An FPGA development board circuit structure, comprising a microprocessor circuit, a memory chip, and a CPLD chip, characterized in that: The microprocessor circuit includes a main control chip power supply circuit, a working indicator circuit, a clock circuit, a crystal oscillator circuit, a reset circuit, a Type-C interface circuit, and a JTAG interface circuit. The main control chip is also connected to a memory chip and a CPLD chip. The crystal oscillator circuit consists of quartz crystal resonators Y1 and Y2 connected in series with capacitors C7, C8 and C9, C10 respectively. Quartz crystal resonator Y1 is also connected in parallel with a resistor R13. The two ends of the capacitor in the quartz crystal resonator Y1 circuit are connected to ground, while only the capacitor end of the quartz crystal resonator Y2 circuit is connected to ground. The clock signal is input and output from the two ends of the resonator.

2. The FPGA development board circuit structure according to claim 1, characterized in that: The main control chip power supply circuit includes a voltage regulator chip and multiple sets of filter circuits. Each set of filter circuits consists of multiple capacitors C connected in parallel and grounded. The working indicator circuit consists of at least one light-emitting diode (LED) and a resistor R connected in series.

3. The FPGA development board circuit structure according to claim 1, characterized in that: The reset circuit consists of a resistor R14, a button U3, and a capacitor C11. One end of the button U3 is grounded, and the other end is connected to the resistor R14 and the capacitor C11 respectively. The other end of the capacitor C11 is grounded, and the other end of the resistor R14 is connected to the power supply circuit of the main control chip.

4. The FPGA development board circuit structure according to claim 1, characterized in that: It also includes a switch button and a button. The switch button consists of a touch button SW connected in series with a resistor R, and the button consists of a color temperature and brightness adjustment button BIN and a resistor R.

5. The FPGA development board circuit structure according to claim 1, characterized in that: The Type-C interface circuit has interfaces A4, B9, B4, A9, B8, A5, B7, A6, A7, B6, A8, B5, A1, B1, A12, B12, and S1. Interface A5 in the Type-C interface circuit is connected to ground after being connected to resistor R7. Interfaces A7 and B7 in the Type-C interface circuit are connected to resistor R8. Interfaces A6 and B6 in the Type-C interface circuit are connected to resistor R9. Interfaces A1, B1, A12, B12, and S1 in the Type-C interface circuit are connected to ground.

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