Switching device

Abstract

A transition device is used to transmit high-speed signals, and the transition device includes a main board, a first signal pair and a second signal pair. The main board includes a surface layer and a specific layer, and the specific layer is located in a different plane from the surface layer. The first signal pair includes a pair of first wire segments and a plurality of first end points, the plurality of first end points respectively correspond to both ends of each of the pair of first wire segments, and the pair of first wire segments and the plurality of first end points are located in the surface layer. The second signal pair includes a pair of second wire segments and a plurality of second end points, the plurality of second end points respectively correspond to both ends of each of the pair of second wire segments, the plurality of second end points are located in the surface layer, and the pair of second wire segments are located in the specific layer.

Description

Technical Field

[0001] This application relates to a switching device, and more particularly to a switching device for transmitting high-speed signals. Background Technology

[0002] With the development of data centers and high-performance computing systems, the demand for riser cables in these systems is increasing. However, existing high-speed cable modules often suffer from signal loss, crosstalk, and insufficient heat dissipation when faced with high-speed data transmission and high-density cabling. Furthermore, space constraints and assembly difficulties limit the widespread application of existing technologies.

[0003] Furthermore, see accompanying references Figure 1 The adapter 2 of the high-speed cable module uses a surface differential pair with closely parallel routing. However, this routing introduces crosstalk into the high-speed cable module, particularly leading to poor long-range crosstalk characteristics. In high-speed, high-frequency transmission, crosstalk significantly affects the eye diagram, especially in PAM4 (four-level pulse amplitude modulation) signals. Crosstalk causes a decrease in signal voltage amplitude and an increase in jitter, thus narrowing the vertical and horizontal openings of the eye diagram. Because the voltage layer spacing of PAM4 signals is narrow, the requirements for signal integrity are higher. Therefore, crosstalk can lead to an increase in the bit error rate and reduce the reliability of data transmission.

[0004] Therefore, how to design a switching device to improve crosstalk is a major research topic that the applicant intends to study in this case. Utility Model Content

[0005] To address the aforementioned problems, this application provides an adapter to overcome the limitations of prior art. Therefore, the adapter of this application includes a motherboard, a first signal pair, and a second signal pair. The motherboard includes a surface layer and a specific layer, with the specific layer and the surface layer located on different planes. The first signal pair includes a pair of first traces and a plurality of first endpoints, each of which is located at both ends of the pair of first traces. The pair of first traces and the plurality of first endpoints are located on the surface layer. The second signal pair includes a pair of second traces and a plurality of second endpoints, each of which is located at both ends of the pair of second traces. The plurality of second endpoints are located on the surface layer, and the pair of second traces are located on the specific layer.

[0006] In one embodiment, the motherboard includes a ground plane. The ground plane is located on a different plane from the specific layer and the surface layer, and the ground plane does not have a first signal pair and a second signal pair.

[0007] In one embodiment, the angle at which the first signal pair and the second signal pair intersect across layers is 0 to 180 degrees.

[0008] In one embodiment, when the angle at which the first signal pair and the second signal pair intersect across the layers is 0 degrees or 180 degrees, the specific layer is disposed between the ground layer and the surface layer.

[0009] In one embodiment, a ground layer is disposed between the surface layer and a specific layer.

[0010] In one embodiment, the motherboard is a six-layer board. The first and sixth layers of the motherboard are two surface layers, and a first signal pair and the plurality of second endpoints are respectively provided thereon. The third and fifth layers of the motherboard are two specific layers, and a pair of second trace segments are respectively provided thereon. The second and fourth layers of the motherboard are ground layers. The first signal pair of the first layer and the second signal pair of the third layer have a first angle between them, and the first signal pair of the sixth layer and the second signal pair of the fifth layer have a second angle between them. The first angle and the second angle are not the same.

[0011] In one embodiment, the pair of first endpoints of at least one end of the pair of first trace segments extend to form a pair of first signal terminals, and the pair of second signal pairs extend from the pair of second endpoints on the same side as the pair of first signal terminals to form a pair of second signal terminals, and the pair of first signal terminals and the pair of second signal terminals are used for connection to external devices.

[0012] In one embodiment, the motherboard further includes two pairs of conductive vias. Each pair of conductive vias penetrates the surface layer and a specific layer, allowing the two ends of each pair of second trace segments to be electrically connected to the corresponding plurality of second endpoints.

[0013] In one embodiment, the motherboard further includes a pair of ground terminals and a ground region. The pair of ground terminals are disposed on the surface layer and are respectively arranged side-by-side on both sides of the plurality of first end points at at least one end of the pair of second trace segments. The ground region is disposed on the surface layer and is electrically connected to the pair of ground terminals. The pair of ground terminals and the ground region surround the plurality of first end points.

[0014] In one embodiment, the motherboard further includes a ground region. The ground region is disposed on a specific layer and surrounds the pair of second trace segments.

[0015] The main purpose and effect of this application is that the switching device of this application uses a cross-layer structure in which the first signal pair and the second signal pair are respectively set in different layers of the switching device to reduce crosstalk caused to each other, so as to achieve the effect of greatly improving crosstalk.

[0016] To gain a deeper understanding of the techniques, means, and effects employed in achieving the intended purpose of this application, please refer to the following detailed description and accompanying drawings. It is believed that the purpose, features, and characteristics of this application can be understood in a more in-depth and concrete manner from these drawings. However, the accompanying drawings are provided for reference and illustration only and are not intended to limit this application. Attached Figure Description

[0017] Figure 1 This is a diagram of the surface wiring structure of a conventional adapter.

[0018] Figure 2 This is an external structural diagram of the high-speed cable module used in this application for transmitting high-speed signals;

[0019] Figure 3 This is an external structural diagram of the adapter used in this application for transmitting high-speed signals;

[0020] Figure 4A This is a surface wiring structure diagram of the adapter device according to the first embodiment of this application;

[0021] Figure 4B This is a specific layer wiring structure diagram of the adapter device according to the first embodiment of this application;

[0022] Figure 4C This is a schematic diagram of the cross-layer structure of the adapter device according to the first embodiment of this application;

[0023] Figure 4D This is a diagram showing the grounding layer wiring structure of the adapter according to the first embodiment of this application;

[0024] Figure 4E This is a cross-sectional view of the motherboard of the first embodiment of this application along the direction from the first conductive hole to the second conductive hole;

[0025] Figure 5A A comparison diagram of crosstalk between a first signal pair when a conventional switching device and a switching device of the first embodiment of this application transmit signals;

[0026] Figure 5B A comparison diagram of crosstalk between the second signal pair when a conventional switching device and the switching device of the first embodiment of this application transmit signals;

[0027] Figure 6A This is a surface wiring structure diagram of the adapter device according to the second embodiment of this application;

[0028] Figure 6B This is a specific layer wiring structure diagram of the adapter device according to the second embodiment of this application;

[0029] Figure 6C This is a schematic diagram of the cross-layer structure of the adapter device according to the second embodiment of this application; and

[0030] Figure 6D This is a diagram of the grounding layer wiring structure of the adapter device according to the second embodiment of this application.

[0031] Explanation of reference numerals in the attached figures:

[0032] 100: High-speed cable module;

[0033] 1: Connector;

[0034] 2: Adapter device;

[0035] MB: Motherboard;

[0036] 20-1~20-n: layers;

[0037] 2A: First side;

[0038] 2B: Second side;

[0039] 22, 22A, 22B: First signal terminals;

[0040] 22-1, 22A-1, 22B-1: First terminal;

[0041] 22-2, 22A-2, 22B-2: Second terminus;

[0042] 24, 24A, 24B: Second signal terminals;

[0043] 24-1, 24A-1, 24B-1: Third terminal;

[0044] 24-2, 24A-2, 24B-2: Fourth terminal;

[0045] 26: First signal pair;

[0046] 26A: First endpoint;

[0047] 26-1, 26-2: First line segment;

[0048] 26-1: First routing;

[0049] 26-2: Second routing;

[0050] 28: Second signal pair;

[0051] 28A: The two endpoints;

[0052] 28-1, 28-2: Second line segment;

[0053] 28-1: Third routing;

[0054] 28-2: Fourth route;

[0055] H1, H2: Conductive holes;

[0056] H1: First conductive hole;

[0057] H2: Second conductive hole;

[0058] GND: Grounding area;

[0059] Pgnd: ground terminal;

[0060] 3: Cables;

[0061] 200: External device;

[0062] II: Waveform. Detailed Implementation

[0063] The technical content and detailed description of this application are explained below with reference to the accompanying drawings:

[0064] Please see Figure 2 This is an external structural diagram of the high-speed cable module used for transmitting high-speed signals in this application, in conjunction with reference to... Figure 1 The high-speed cable module 100 of this application can be, for example but not limited to, a high-speed cable module 100 such as MCIO (Mini CoolEdgeIO) for transmitting high-speed signals, and the high-speed cable module 100 is used to plug into a connector (not shown) of an external device 200 (e.g., but not limited to, a server motherboard, storage device, etc.). The high-speed cable module 100 includes components such as a connector 1, an adapter 2, and a cable 3. These components are formed by welding and assembly. The adapter 2 generally has differential pairs (i.e., closely parallel traces) on its surface, but this is not a limitation. It can also be a non-differential pair trace, and can be configured according to actual needs.

[0065] Furthermore, the high-speed cable module 100 is widely used in high-density connection systems to achieve high-speed data transmission and stable signal integrity. This application relates to cable assembly technology in the fields of data centers and high-performance computing, specifically focusing on the structural design and performance optimization of the adapter 2 to improve its performance in terms of space utilization, reliability, and transmission performance. It is particularly suitable for high-speed interconnect scenarios such as server motherboards, storage devices, and PCIe.

[0066] Please see Figure 3 This is an external structural diagram of the adapter used to transmit high-speed signals in this application, in conjunction with reference to... Figure 2The adapter 2 is used to transmit high-speed signals and includes a motherboard MB, a first signal pair 26, and a second signal pair 28. The motherboard MB is a multilayer board, and the first signal pair 26 and the second signal pair 28 are located on at least one surface layer 20-1, 20-n of the adapter 2 (shown as surface layer 20-1). Specifically, the first signal pair 26 includes a pair of first trace segments 26-1, 26-2 and a plurality of first endpoints 26A, each corresponding to one end of each of the first trace segments 26-1, 26-2 (i.e., two pairs of first endpoints 26A at each end), and the first trace segments 26-1, 26-2 and the first endpoints 26A are located on surface layer 20-1. The second signal pair 28 includes a pair of second trace segments (not shown) and a plurality of second endpoints 28A, each corresponding to one end of each of the second trace segments (not shown) (i.e., two pairs of second endpoints 28A at each end). The two endpoints 28A are also located on surface layer 20-1, and the second routing segment (not shown) is not located on surface layer 20-1, but is electrically connected to the two endpoints 28A.

[0067] exist Figure 3 In the diagram, at least one end point 26A of the first trace segment 26-1, 26-2 can extend to form a first signal terminal 22 (illustrated here, both pairs of first end points 26A form the first signal terminal 22, and the first signal terminal 22 and the first end point 26A mentioned later can represent the same thing; the distinction is only for illustrative purposes and will not be elaborated further). Similarly, at least one end point 28A of the second trace segment (not shown) can extend to form a second signal terminal 24 (illustrated here, both pairs of second end points 28A form the second signal terminal 24, and the second signal terminal 24 and the second end point 28A mentioned later can represent the same thing; the distinction is only for illustrative purposes and will not be elaborated further). When only one side of the first end point 26A and the second end point 28A forms the first and second signal terminals 22 and 24, they are located on the same side of the motherboard MB. See also... Figure 2The first signal terminal 22 and the second signal terminal 24 are located on the same side of the motherboard MB and can serve as edge connectors (i.e., gold fingers) for external devices 200 to plug into. In another embodiment, the first endpoint 26A and the second endpoint 28A on the other side can also form a signal terminal structure to serve as a relay adapter board, or they can form pads, solder pads, or large soldering areas. All of these structures are beneficial for soldering the cable 3. Furthermore, when the two pairs of first endpoints 26A and the two pairs of second endpoints 28A extend to form the first signal terminal 22 and the second signal terminal 24 respectively, the first signal terminal 22 and the second signal terminal 24 are both located on the surface layer 20-1 of the motherboard MB. A pair of first signal terminals 22 and a pair of second signal terminals 24 are arranged side by side on the first side 2A of the surface layer 20-1 of the adapter device 2. And another pair of first signal terminals 22 and another pair of second signal terminals 24 are arranged side by side on the second side 2B of the surface layer 20-1 of the adapter device 2.

[0068] Taking a differential pair as an example, each pair of first signal terminals 22 includes a first terminal 22-1 and a second terminal 22-2 of the differential pair, and each pair of second signal terminals 24 includes a third terminal 24-1 and a fourth terminal 24-2 of the differential pair. The first terminal 22-1 and the second terminal 22-2 are arranged side-by-side, and the third terminal 24-1 and the fourth terminal 24-2 are also arranged side-by-side. The first side 2A can be a side for connecting an external device 200, and the second side 2B can be a side for soldering the cable 3. In one embodiment, the second side 2B is preferably substantially parallel to the first side 2A, but this is not a limitation; that is, the first side 2A and the second side 2B can be any two sides of the motherboard MB.

[0069] Please see Figure 4A This is a surface wiring structure diagram of the adapter device according to the first embodiment of this application. Figure 4B This is a specific layer wiring structure diagram of the adapter device according to the first embodiment of this application, in conjunction with the following: Figures 2-3 .exist Figures 4A-4B In this description, for the sake of simplicity and convenience, a set of first signal pairs 26 and a set of second signal pairs 28 are used. The subsequent extensions of the first signal pairs 26 and second signal pairs 28 have the same structure and are arranged in the same way. Furthermore, in one embodiment, the description of "generally" in this application can be interpreted as "substantially," with a deviation of, for example but not limited to, 5-10%. For example, two components being "generally parallel" can be considered as two components being "substantially parallel," but with a possible angular difference of 5-10%, and so on.

[0070] exist Figure 4AIn the adapter 2, a first signal pair 26 is located on the surface layer 20-1. A first endpoint 26A at one end of the first signal pair 26 can extend to form a pair of first signal terminals 22A, and a first endpoint 26A at the other end can extend to form another pair of first signal terminals 22B. Taking a differential pair as an example, the first trace segments 26-1 and 26-2 of the first signal pair 26 may include a first trace 26-1 and a second trace 26-2. The first endpoints 26A at both ends of the first trace 26-1 extend to form first terminals 22A-1 and 22B-1, respectively, and the first endpoints 26A at both ends of the second trace 26-2 extend to form second terminals 22A-2 and 22B-2, respectively. An electrically isolated region exists between the first trace 26-1 and the second trace 26-2, and this region may be a hollow area or filled with a non-conductive material (e.g., but not limited to resin). The first trace 26-1 and the second trace 26-2 can be arranged in a generally parallel trace structure, with only slight bends at the electrical connection terminals 22A-1, 22A-2, 22B-1, and 22B-2. However, it is not excluded that they may include compensation-related trace embodiments such as serpentine traces. Preferably, the first trace 26-1 and the second trace 26-2 can be connected along the midpoint between them and arranged in a mirror image.

[0071] On the other hand, Figure 4A In this configuration, one pair of second signal terminals 24A is located on the same side as one pair of first signal terminals 22A and is arranged side-by-side with them. Another pair of second signal terminals 24B is located on the same side as another pair of first signal terminals 22B and is arranged side-by-side with them. (See also...) Figure 4B The adapter 2 includes a second signal pair 28 and two pairs of conductive holes H1 and H2, with the second signal pair 28 located in a specific layer 20-2 (illustrated as the second layer, but not limited thereto). The two pairs of conductive holes H2 are used to connect the surface layer 20-1 and the specific layer 20-2 of the adapter 2, and the two pairs of conductive holes H1 and H2 include a first conductive hole H1 and a second conductive hole H2. The first conductive hole H1 and the second conductive hole H2 are respectively located at the second end points 28A of the two ends of the second signal pair 28, and one end of the second end point 28A is electrically connected to one end of the second trace segments 28-1 and 28-2 located in the specific layer 20-2 through the first conductive hole H1. The other end of the second end point 28A is electrically connected to the other end of the second trace segments 28-1 and 28-2 located in the specific layer 20-2 through the second conductive hole H2. Therefore, the two pairs of conductive holes H1 and H2 are mainly for electrically connecting the two ends of the second trace segments 28-1 and 28-2 to the corresponding second end points 28A.

[0072] The two endpoints 28A at one end of the second signal pair 28 can extend to form a pair of second signal terminals 24A, and the two endpoints 28A at the other end can extend to form another pair of second signal terminals 24B. Taking a differential pair as an example, the second trace segments 28-1 and 28-2 of the second signal pair 28 may include a third trace 28-1 and a fourth trace 28-2. The two endpoints 28A at both ends of the third trace 28-1 extend to form third terminals 24A-1 and 24B-1, respectively, and the two endpoints 28A at both ends of the fourth trace 28-2 extend to form fourth terminals 24A-2 and 24B-2, respectively. Similar to the first signal pair 26, there is an electrically isolated area between the third trace 28-1 and the fourth trace 28-2, and the third trace 28-1 and the fourth trace 28-2 may have a generally parallel trace structure, and the third trace 28-1 and the fourth trace 28-2 may be mirrored by connecting along the midpoint between them.

[0073] See also Figure 4C This is a schematic diagram of the cross-layer structure of the adapter device according to the first embodiment of this application, in conjunction with reference to... Figures 2-4B The first signal pair 26 and the second signal pair 28 are arranged in a generally parallel structure across layers, and the straight line connecting the first signal terminals 22A and 22B is generally parallel to the straight line connecting the second signal terminals 24A and 24B. In other words, from a bird's-eye view or from above, the first signal pair 26 located on surface layer 20-1 and the second signal pair 28 located on surface layer 20-1 or on a specific layer 20-2 are generally parallel to each other. Taking a differential pair as an example, the first trace 26-1, the second trace 26-2, the third trace 28-1, and the fourth trace 28-2 are arranged in a generally parallel structure across layers. Therefore, the straight lines connecting the first terminals 22A-1, 22B-1 and the second terminals 22A-2, 22B-2 of the third terminals 24A-1, 24B-1 are substantially parallel to each other, and the straight lines connecting the second terminals 22A-2, 22B-2 and the fourth terminals 24A-2, 24B-2 are also substantially parallel to each other. Since the second signal pair 28 is located on a specific layer 20-2, the surface layer 20-1 of the motherboard MB can reduce crosstalk between the first signal pair 26 and the second signal pair 28 by interleaving the first signal pair 26 with the ground region GND, thus significantly improving crosstalk.

[0074] On the other hand, Figure 4ATwo pairs of grounding terminals Pgnd and a grounding region GND can also be provided in the surface layer 20-1. The two pairs of grounding terminals Pgnd are respectively arranged side by side on both sides of the two pairs of second signal terminals 24A and 24B (i.e., the second signal terminals 24A and 24B formed by the two pairs of second terminal points 28A), so that the second signal terminals 24A and 24B are isolated from the first signal terminals 22A and 22B through the grounding terminals Pgnd. The grounding region GND is electrically connected to the grounding terminal Pgnd, and the grounding terminal Pgnd and the grounding region GND surround the second signal terminals 24A and 24B, so that the grounding terminal Pgnd, the grounding region GND and the second signal terminals 24A and 24B are electrically isolated. Specifically, in Figure 4A In the surface layer 20-1, the area other than the first signal pair 26, the first signal terminals 22A and 22B, the second signal terminals 24A and 24B, and the two terminal points 28A can be set as ground (i.e., ground terminal Pgnd and ground area GND), and the ground terminal Pgnd and ground area GND are electrically isolated from the aforementioned components. Alternatively, the surface layer 20-1 may only have one pair of ground terminals Pgnd, arranged side-by-side with the second signal terminal 24A or the second signal terminal 24B, so that the ground terminal Pgnd is electrically connected to the ground area GND and surrounds the second signal terminal 24A or the second signal terminal 24B. The electrically isolated area can be a hollow area or filled with a non-conductive material (e.g., but not limited to resin). Thus, the crosstalk between the first signal pair 26 and the second signal pair 28 can be further reduced by the parallel arrangement of the first signal pair 26 and the second signal pair 28 across layers, resulting in a significant improvement in crosstalk.

[0075] It is worth mentioning that, in one embodiment, Figure 4B The grounding area GND setting method is similar to Figure 4A The difference lies in that the grounding region GND is set in a specific layer 20-2, outside the second signal pair 28 and surrounding the second signal pair 28, and can achieve a similar effect. Figure 4A Its effects. (See also...) Figure 4A , 4B The areas of the first signal terminals 22A and 22B and the second signal terminals 24A and 24B may be used as electrically isolated areas without copper plating, but this is not a limitation. Furthermore, please refer to... Figure 4D This is a diagram of the grounding layer wiring structure of the adapter device according to the first embodiment of this application, in conjunction with other relevant documents. Figures 2-4C .exist Figure 4DIn this adapter 2, one layer can be configured as a ground layer 20-3 (illustrated as the third layer, but not limited to this), and the ground layer 20-3 is located on a different plane from the specific layer 20-2 and the surface layer 20-1. The ground layer 20-3 can be provided with a large area of ​​copper plating to serve as a large grounding area GND. Furthermore, the adapter 2 does not have a first signal pair 26 and a second signal pair 28 in the ground layer 20-3 to reduce signal interference, signal loss, and instability in the adapter 2.

[0076] On the other hand, see also Figure 4E This is a cross-sectional view of the motherboard of the first embodiment of this application along the direction from the first conductive hole to the second conductive hole, and can be further referenced. Figures 2-4D .exist Figure 4E The diagram primarily shows a cross-section of the motherboard MB along the direction of the third terminal 24A-1, the first conductive hole H1, the second conductive hole H2, and the third terminal 24B-1. The first conductive hole H1 and the second conductive hole H2 are through-holes (also called blind vias) between the surface layer 20-1 and the specific layer 20-2 of the motherboard MB, and are made conductive by filling them with conductive materials (such as, but not limited to, copper, tin, etc.). Therefore, the third terminal 24A-1 (extended from the two end points 28A) located outside the surface layer 20-1 can be electrically connected to one end of the third trace 28-1 in the specific layer 20-2 through the first conductive hole H1, and the third terminal 24B-1 (extended from the two end points 28A) can also be electrically connected to the other end of the third trace 28-1 in the specific layer 20-2 through the second conductive hole H2. The cross-sectional structure of the fourth trace 28-2 is similar and will not be described further here. In addition, grounding layer 20-3 has a large grounding area GND due to the large area of ​​copper plating.

[0077] In one embodiment, when the adapter 2 has only one surface layer 20-1 provided with first signal terminals 22A, 22B, second signal terminals 24A, 24B, first signal pair 26 and second terminal point 28A, the ground layer 20-3 may be disposed between the surface layer 20-1 and the specific layer 20-2, or the specific layer 20-2 may be disposed between the surface layer 20-1 and the ground layer 20-3. Conversely, when the two outer layers 20-1 and 20-n of the adapter 2 are respectively provided with first signal terminals 22A and 22B, second signal terminals 24A and 24B, first signal pair 26, and second endpoint 28A, the ground layer 20-3 must isolate the first signal terminals 22A and 22B, second signal terminals 24A and 24B, first signal pair 26, and second endpoint 28A of the two outer layers 20-1 and 20-n, as well as the second signal pair 28 located on different layers, to avoid mutual interference between the signals transmitted by the first signal pair 26 and the second signal pair 28. Therefore, when the two outer layers 20-1 and 20-n of the adapter 2 are respectively provided with first signal terminals 22A and 22B, second signal terminals 24A and 24B, first signal pair 26, and second endpoint 28A, two ground layers 20-3 are required for high-speed signal isolation.

[0078] Specifically, when the two outer layers 20-1 and 20-n of the adapter 2 are respectively provided with first signal terminals 22A and 22B, second signal terminals 24A and 24B, first signal pair 26, and second terminal point 28A, the adapter 2 needs to use a board with six or more layers. (Six-layer board setup) Figures 4A-4D Taking the circuit structure as an example, the first layer 20-1 and the sixth layer 20-6 of the adapter 2 are respectively provided with first signal terminals 22A and 22B, second signal terminals 24A and 24B, first signal pair 26 and second terminal 28A (see reference). Figure 4A Furthermore, the second layer 20-2 and the fifth layer 20-5 of the adapter 2 are specific layers, and each is provided with a second signal pair 28. The second signal pair 28 is electrically connected to the two endpoints 28A through the first conductive hole H1 and the second conductive hole H2 that penetrate to the two surface layers 20-1 and 20-n (see reference). Figure 4B Furthermore, the third layer 20-3 and the fourth layer 20-4 of the adapter 2 are grounding layers (see reference). Figure 4DThis is to isolate high-speed signals transmitted on surface layer 20-1, second layer 20-2, surface layer 20-6, and fifth layer 20-5. It is worth noting that, in one embodiment, the numbering of all components in the signal pairs herein is merely a structural designation for illustrative purposes and has no relation to the type or waveform of the signal transmitted. For example, the signals transmitted by the first signal terminals 22A and 22B of the first layer 20-1 can be completely different from the signals transmitted by the second signal terminals 24A and 24B of the first layer 20-1, and the signals transmitted by the first signal terminals 22A and 22B of the first layer 20-1 can also be completely different from the signals transmitted by the first signal terminals 22A and 22B of the sixth layer 20-6. Furthermore, refer to... Figure 4A The signals transmitted by the first signal terminals 22A and 22B on the same layer can be completely different. However, this is not a limitation; they can transmit the same signal as needed, and so on. This will not be elaborated further here.

[0079] Please see Figure 5A When a conventional switching device transmits signals with the switching device of the first embodiment of this application, a crosstalk comparison diagram of the first signal pair is provided. Figure 5B When a conventional switching device transmits signals with the switching device of the first embodiment of this application, a crosstalk comparison diagram of the second signal pair is provided, in conjunction with the reference diagram. Figures 1-4E .exist Figure 5A , Figure 5B Waveform I (solid line) in the image is mainly used Figure 1 The waveform curves of the conventional adapter 2 when transmitting Rx and Tx signals are shown. Figure 5A , Figure 5B Waveform II (dashed line) in the diagram mainly represents the waveform curves when transmitting Rx and Tx signals using the first signal pair 26 and the second signal pair 28 of the adapter 2 of this application. Furthermore, by... Figure 5A , Figure 5B It is evident that by using the wiring structure of this application, the crosstalk of the Rx signal can be reduced by more than 10dB when the adapter 2 transmits Rx and Tx signals simultaneously.

[0080] Please see Figure 6A This is a surface wiring structure diagram of the adapter device according to the second embodiment of this application. Figure 6B This is a specific layer wiring structure diagram of the adapter device according to the second embodiment of this application, in conjunction with the following: Figures 2-5B . Figure 6A , 6B Wiring structure and Figure 4A , 4B Similar, the difference lies in the fact that the first signal pair 26 and the second signal pair 28 intersect across layers. Specifically, Figure 6A , 6BThe first endpoints 26A of the first signal pair 26 are misaligned, causing the positions of the first signal terminal 22A and the second signal terminal 24A to be interchanged. Therefore, the straight line connecting the first signal terminal 22A and the second signal terminal 24B is approximately parallel to the straight line connecting the second signal terminal 24A and the first signal terminal 22B. Furthermore, the first endpoints 26A of the first signal pair 26 can also extend to form the first signal terminals 22A and 22B, respectively, and the two endpoints 28A of the second signal pair 28 can also extend to form the second signal terminals 24A and 24B, respectively.

[0081] Therefore, the first signal terminal 22A is electrically connected to the first signal terminal 22B after a secondary bend in the first signal pair 26, and the second signal terminal 24A is similarly electrically connected to the second signal terminal 24B after a secondary bend in the second signal pair 28. (See also...) Figure 6C This is a schematic diagram of the cross-layer structure of the adapter device according to the second embodiment of this application, in conjunction with the following references. Figures 2-6B Since the first signal pair 26 and the second signal pair 28 are respectively angled on different layers of the adapter 2, the first signal pair 26 and the second signal pair 28 include two pairs of intersection points Pc that intersect across layers, and the first signal pair 26 and the second signal pair 28 form a specific angle θ with the intersection point Pc as the center. The specific angle θ can be 0 to 180 degrees, with a preferred embodiment being 90 degrees, but it is not limited to this; it can also be 45 degrees, 120 degrees, 135 degrees, etc., and can be adjusted to the optimal angle according to the actual situation, which will not be elaborated here. In other words, as viewed from above or from above the motherboard MB, the first signal pair 26 located on surface layer 20-1 and the second signal pair 28 located on surface layer 20-1 or on a specific layer 20-2 intersect across layers. In one embodiment, since a magnetic field (right-hand rule) is generated when the signal is transmitted along the line, and if the signal transmission paths happen to intersect perpendicularly, the magnetic fields can cancel each other out, reducing crosstalk caused by each other. Therefore, the angle θ at which the first signal pair 26 and the second signal pair 28 intersect across layers is approximately 90 degrees, which can achieve better crosstalk reduction and is a better implementation method.

[0082] Figure 6B and Figure 4B Another difference is that, in a specific layer 20-2 (20-5), the area corresponding to the positions of the first signal terminals 22A, 22B and the second signal terminals 24A, 24B can be copper-plated to serve as a large-scale grounding area GND, and Figure 6B and Figure 4B The aforementioned features can be selected for application based on the actual needs of the adapter 2. Furthermore, Figure 6D and Figure 4DThe difference lies in that, in ground plane 20-3 (20-4), the areas corresponding to the positions of the first signal terminals 22A, 22B, the second signal terminals 24A, 24B, and the two endpoints 28A can be used as electrically isolated areas without copper plating. Figure 6D and Figure 4D The aforementioned features can also be selected for application depending on the actual needs of the adapter 2. Therefore, Figure 6D The adapter 2 also includes a large grounding area GND grounding layer 20-3 (20-4), which can also reduce signal interference, signal loss, and instability of the adapter 2. On the other hand, the cross-sectional structure of the motherboard MB in the second embodiment along the direction from the first conductive hole H1 to the second conductive hole H2 can be obtained from... Figure 4E and Figures 6A-6D Therefore, it is assumed that its sectional view will not be shown here.

[0083] It is worth mentioning that the crosstalk comparison diagram of the adapter 2 in the two embodiments can be obtained from... Figure 5A , 5B and Figures 6A-6D Therefore, it is inferred that the crosstalk comparison diagram will not be specifically presented here. Furthermore, since the cross-layer intersection of the first signal pair 26 and the second signal pair 28 provides a better crosstalk suppression effect, therefore... Figures 6A-6D When transmitting Rx and Tx signals simultaneously, the adapter 2 can exhibit better performance than... Figures 4A-4D The adapter 2 provides better crosstalk reduction (i.e., a reduction of more than 10dB).

[0084] On the other hand, in one embodiment, Figures 6A-6D The circuit structure and wiring methods not specifically described are all similar to Figures 4A-4E , or may be by Figures 4A-4E Therefore, further details are omitted here. In another embodiment, where the adapter 2 is a six-layer plate, Figures 4A-4E The settings for 6A to 6D can be integrated and applied together. For example, but not limited to, the settings for the first to third layers. Figures 4A-4E The shelves, and the sixth to fourth layers are set Figures 6A-6D The layers are arranged in a specific pattern. Thus, the first signal pair 26 and the second signal pair 28 of the first layer 20-1 and the second layer 20-2 of the motherboard MB should ideally have a first angle (e.g., but not limited to 0 degrees), and the first signal pair 26 and the second signal pair 28 of the sixth layer 20-6 and the fifth layer 20-5 should ideally have a second angle (e.g., but not limited to a 90-degree intersection across layers). Furthermore, the first angle and the second angle are different, allowing the adapter 2 of this application to selectively configure its transmission position according to signal accuracy requirements (e.g., but not limited to, signals requiring high accuracy can travel through the sixth to fourth layers), and so on, which will not be elaborated further here.

[0085] Furthermore, since the first signal pair 26 and the second signal pair 28 intersect across layers, they can provide better crosstalk suppression. Figures 6A-6D The grounding layer can be configured more flexibly. Specifically, when the angle θ between the first signal pair 26 and the second signal pair 28 across the layer is similar to... Figures 4A-4E When the intersection angle θ is 0 degrees or 180 degrees, the crosstalk suppression effect is relatively small. Therefore, it is preferable to place the specific layer between the ground layer and the surface layer. Conversely, when the intersection angle θ between the first signal pair 26 and the second signal pair 28 across layers is similar to... Figures 6A-6D When the intersection angle θ is not 0 degrees or 180 degrees, the crosstalk suppression effect is greater, so it is preferable to place the grounding layer between the surface layer and a specific layer. Therefore, if the first angle and the second angle are not the same, and assuming the first to third layers are set... Figures 6A-6D Shelves, with the sixth to fourth layers set up Figures 4A-4E The structure of the first to third layers is such that the grounding layer 20-2 is set between the surface layer 20-1 and the specific layer 20-3, and the structure of the sixth to fourth layers is such that the specific layer 20-5 is set between the grounding layer 20-4 and the surface layer 20-6, and so on. It will not be described in detail here.

[0086] However, the above description is only a detailed description and accompanying drawings of preferred embodiments of this application. The features of this application are not limited thereto and are not intended to limit this application. All scope of this application shall be determined by the following patent claims. All embodiments that conform to the spirit of the patent claims and similar variations thereof shall be included in the scope of this application. Any variations or modifications that can be easily conceived by those skilled in the art within the field of this application shall be covered by the following patent claims.

Claims

1. A switching device, characterized in that, The adapter is used to transmit high-speed signals and includes: A motherboard includes a surface layer and a specific layer, wherein the specific layer and the surface layer are located on different planes; A first signal pair includes a pair of first trace segments and a plurality of first endpoints, wherein the plurality of first endpoints are respectively located at both ends of each of the pair of first trace segments, and the pair of first trace segments and the plurality of first endpoints are located on the surface layer; and The second signal pair includes a pair of second trace segments and a plurality of second endpoints, wherein the plurality of second endpoints are respectively located at the two ends of each of the pair of second trace segments, the plurality of second endpoints are located on the surface layer, and the pair of second trace segments are located on the specific layer.

2. The adapter as described in claim 1, characterized in that, The motherboard includes: The grounding layer is located on a different plane from the specific layer and the surface layer, and the grounding layer does not have the first signal pair and the second signal pair.

3. The adapter as described in claim 2, characterized in that, The angle at which the first signal pair and the second signal pair intersect across layers is 0 to 180 degrees.

4. The adapter as described in claim 2 or 3, characterized in that, When the angle at which the first signal pair and the second signal pair intersect across layers is 0 degrees or 180 degrees, the specific layer is disposed between the ground layer and the surface layer.

5. The adapter as described in claim 2 or 3, characterized in that, The grounding layer is positioned between the surface layer and the specific layer.

6. The adapter as described in claim 2 or 3, characterized in that, The motherboard is a six-layer board. The first and sixth layers of the motherboard are two surface layers, and the first signal pair and the plurality of second endpoints are respectively provided thereon. The third and fifth layers of the motherboard are two specific layers, and the pair of second trace segments are respectively provided thereon. The second and fourth layers of the motherboard are the ground layers. The first signal pair of the first layer and the second signal pair of the third layer have a first angle between them, and the first signal pair of the sixth layer and the second signal pair of the fifth layer have a second angle between them. The first angle and the second angle are different.

7. The adapter as described in claim 1, characterized in that, At least one end of the pair of first endpoints of the pair of first traces extends to form a pair of first signal terminals, and the pair of second signal terminals on the same side as the pair of first signal terminals extend to form a pair of second signal terminals, and the pair of first signal terminals and the pair of second signal terminals are used for external device insertion.

8. The adapter as described in claim 1, characterized in that, The motherboard also includes: Two pairs of conductive holes, penetrating the surface layer and the specific layer, allow the two ends of the pair of second trace segments to be electrically connected to the corresponding plurality of second endpoints.

9. The adapter as claimed in claim 1, characterized in that, The motherboard also includes: A pair of grounding terminals are disposed on the surface layer and are respectively arranged side by side on both sides of the plurality of second terminal points at at least one end of the pair of second trace segments; and A grounding area is provided on the surface layer and is electrically connected to the pair of grounding terminals; The pair of grounding terminals and the grounding area surround the plurality of second terminals.

10. The adapter as claimed in claim 1, characterized in that, The motherboard also includes: A grounding area is provided on the specific layer and surrounds the pair of second trace segments.

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