An SGT MOSFET device structure

Abstract

This utility model relates to the field of semiconductor technology, and in particular to an SGT MOSFET device structure. The device structure includes: a substrate, an epitaxial layer, a doped region, a gate region, and a buffer layer. The epitaxial layer is located on the substrate; the doped region is located on the epitaxial layer; the gate region is located on the epitaxial layer and extends through the doped region; the buffer layer is located in the epitaxial layer and below the doped region, and surrounds the gate trench of the gate region. This device structure reduces the specific on-resistance Rsp of the SGT MOSFET device while maintaining a minimal change in the device's breakdown voltage BVDSS, thus reducing the device's production cost and offering advantages such as affordability and ease of operation.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to an SGT MOSFET device structure. Background Technology

[0002] The SGT MOSFET (Split-Gate-Trench Metal-Oxide-Semiconductor Field-Effect Transistor) device structure, due to its charge-coupling effect, introduces horizontal depletion into the traditional trench MOSFET structure's vertical depletion layer (such as the P-body region and N-Epi junction), changing the device's electric field distribution from a triangular distribution to an approximately rectangular wavy distribution. With the same doping concentration and epitaxial specifications, SGT MOSFET devices can achieve higher breakdown voltages, and this device structure is widely used in low- and medium-voltage power devices.

[0003] In the structure of a traditional N-channel SGT MOSFET, the gate (G) is connected to a positive potential, and the source (S) is connected to zero potential. If the voltage difference VGS between the G and S terminals exceeds the threshold voltage VTH, the N-channel of the device is in the ON state. The drain (D) is connected to a positive potential, and current flows from the D terminal to the S terminal. Due to the voltage difference between the D and S terminals, the S terminal (i.e., the shielding gate) is equivalent to the negative terminal. According to the principle of a parallel-plate capacitor, the S terminal will attract positive charges on the side of the gate trench that contacts the epitaxial layer, forming depletion broadening. However, the N-channel SGT MOSFET is a unipolar device, where electrons are the majority carriers. The depletion broadening region is positively charged, and electrons cannot pass through. Therefore, the current path when the device is turned on is compressed, thereby increasing the specific on resistance (Rsp).

[0004] Currently, to address the high specific on-resistance issue of traditional SGT MOSFET devices, existing solutions aim to achieve an optimal trade-off between breakdown voltage (BVDSS) and on-resistance (Rdson) by adjusting the epitaxial layer. This can be achieved by employing a gradient epitaxial resistivity or a multi-layer epitaxial structure. However, this increases the difficulty of epitaxial layer manufacturing and makes post-production management challenging. Even slight fluctuations in the epitaxial layer can lead to significant changes in device parameters, causing the high specific on-resistance problem to persist in SGT MOSFET devices. Utility Model Content

[0005] This application provides an SGT MOSFET device structure that solves the technical problem of high specific on-resistance in existing SGT MOSFET devices. It reduces the specific on-resistance Rsp of the SGT MOSFET device while keeping the device's breakdown voltage BVDSS unchanged, thereby reducing the device's production cost. It has the technical advantages of being economical and easy to operate.

[0006] In a first aspect, this utility model provides an SGT MOSFET device structure, including: a substrate, an epitaxial layer, a doped region, a gate region, and a buffer layer;

[0007] The epitaxial layer is located on the substrate;

[0008] The doped region is located on the epitaxial layer;

[0009] The gate region is located on the epitaxial layer and extends through the doped region;

[0010] The buffer layer is located in the epitaxial layer and below the doped region, and surrounds the gate trench of the gate region.

[0011] Optionally, the conductivity type of the buffer layer is N-type.

[0012] Optionally, the doping concentration of the buffer layer ranges from 5E15cm-3 to 1E16cm-3.

[0013] Optionally, the thickness of the buffer layer ranges from 0.2µm to 0.5µm.

[0014] Optionally, the buffer layer includes: a first buffer sub-layer and a second buffer sub-layer;

[0015] Both the first buffer sublayer and the second buffer sublayer are located in the epitaxial layer and below the doped region;

[0016] The tops of both the first and second buffer sublayers are in contact with the doped region, and the bottoms of the first and second buffer sublayers are in contact with the bottoms of the second buffer sublayers, so as to enclose the gate trench through the first and second buffer sublayers.

[0017] Optionally, the doped region includes: a P-well region and an N+ source region;

[0018] The P-well region is located on the epitaxial layer;

[0019] The N+ source region is located on the P-well region, wherein the surface of the N+ source region is at the same horizontal plane as the surface of the epitaxial layer.

[0020] Optionally, the gate region includes: the gate trench, the control gate, the shielding gate, and the gate oxide layer;

[0021] The gate trench extends through the P-well region and the N+ source region and is located in the epitaxial layer, with the bottom of the gate trench contacting the epitaxial layer;

[0022] The shielding gate is located at the bottom of the gate trench;

[0023] The control gate is located within the gate trench and above the shielding gate;

[0024] The gate oxide layer fills the gate trench, between the shielding gate and the inner wall of the gate trench, between the control gate and the inner wall of the gate trench, and between the shielding gate and the control gate.

[0025] Optionally, both the substrate and the epitaxial layer are N-type.

[0026] Optionally, it may further include: a dielectric layer, which is located above the epitaxial layer and covers the doped region and the gate region.

[0027] Optionally, it further includes: a front metal layer and a back metal layer; the front metal layer is located above the dielectric layer and covers the doped region and the gate region; the back metal layer is located below the substrate.

[0028] One or more technical solutions in the embodiments of this utility model have at least the following technical effects or advantages:

[0029] In this embodiment of the invention, a buffer layer is provided between the gate trench in the gate region and the epitaxial layer on the substrate. This buffer layer encapsulates the gate trench and, consequently, the gate oxide layer, thereby reducing the depletion broadening caused by the positive charge attracted in the gate region. When the device is turned on, the width of the depletion broadening caused by the positive charge is shortened, the current path is increased, further reducing the on-resistance and the specific on-resistance of the device, while maintaining the stability of the breakdown voltage (BVDSS), i.e., without affecting the original breakdown voltage (BVDSS) of the device. Thus, the device structure of this embodiment of the invention also reduces the production cost of the device, offering advantages such as affordability and ease of operation. Attached Figure Description

[0030] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, the same reference figures denote the same parts throughout the drawings. In the drawings:

[0031] Figure 1 A schematic diagram of the SGT MOSFET device structure in an embodiment of the present invention is shown;

[0032] Figure 2 A schematic diagram showing the output characteristic curves of the SGT MOSFET device structure in this embodiment and the SGT MOSFET device structure without a buffer layer is presented.

[0033] In the attached figures, 110 is the substrate; 120 is the epitaxial layer; 130 is the doped region; 140 is the gate region; 150 is the buffer layer; 160 is the front metal layer; 170 is the back metal layer; and 180 is the dielectric layer.

[0034] 131. P-well region; 132. N+ source region;

[0035] 141. Gate trench; 142. Control gate; 143. Shielding gate; 144. Gate oxide layer. Detailed Implementation

[0036] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0037] Example 1

[0038] The first embodiment of this utility model provides an SGT MOSFET device structure, such as... Figure 1 As shown, the structure includes: a substrate 110, an epitaxial layer 120, a doped region 130, a gate region 140, and a buffer layer 150. The epitaxial layer 120 is located above the substrate 110, and the doped region 130 is located on the epitaxial layer 120. The gate region 140 is located on the epitaxial layer 120 and extends through the doped region 130. The buffer layer 150 is located in the epitaxial layer 120 and below the doped region 130, and surrounds the gate trench 141 of the gate region 140.

[0039] In this embodiment, a buffer layer 150 is provided between the gate trench 141 of the gate region 140 and the epitaxial layer 120 on the substrate 110. The buffer layer 150 surrounds the gate trench 141, and further surrounds the gate oxide layer 144, thereby reducing the depletion broadening caused by the positive charge attracted by the gate region 140. Thus, when the device is turned on, the width of the depletion broadening caused by the positive charge is shortened, the current path is increased, further reducing the on-resistance and the specific on-resistance of the device, while maintaining the stability of the breakdown voltage BVDSS (Breakdown Voltage Drain to Source), i.e., without affecting the original breakdown voltage BVDSS of the device. Therefore, the device structure of this embodiment can also reduce the production cost of the device, offering advantages such as affordability and ease of operation.

[0040] Below, in conjunction with Figure 1 The structure of the SGT MOSFET device provided in this embodiment is described in detail below:

[0041] Both the substrate 110 and the epitaxial layer 120 are N-type conductive. The doping concentration of the epitaxial layer 120 is lower than that of the substrate 110. The substrate 110 is an N-type heavily doped silicon substrate, i.e., an N+ substrate. The epitaxial layer 120 is an N-type lightly doped epitaxial layer, i.e., an N- epitaxial layer. The thickness of the epitaxial layer 120 can be set according to actual requirements.

[0042] The doped region 130 includes a P-well region 131 and an N+ source region 132. The P-well region 131 is located on the epitaxial layer 120. The N+ source region 132 is located on the P-well region 131, wherein the surface of the N+ source region 132 is at the same horizontal plane as the surface of the epitaxial layer 120.

[0043] Specifically, the P-well region 131 is a lightly doped P-type well region, and the N+ source region 132 is a heavily doped N-type source region. In the fabrication process, after forming the buffer layer 150 and the gate region 140, P-type impurities are implanted and pushed together on the epitaxial layer 120 to form the P-well region 131. Subsequently, N-type impurities are implanted and pushed together on the P-well region 131 to form the N+ source region 132. Thus, both the P-well region 131 and the N+ source region 132 are distributed on the epitaxial layer 120 and on both sides of the gate region 140.

[0044] Gate region 140 includes: gate trench 141, control gate 142, shielding gate 143, and gate oxide layer 144. Gate trench 141 extends through P-well region 131 and N+ source region 132, and is located in epitaxial layer 120, with the bottom of gate trench 141 contacting epitaxial layer 120. Shielding gate 143 is located at the bottom of gate trench 141. Control gate 142 is located within gate trench 141 and above shielding gate 143. Gate oxide layer 144 fills within gate trench 141, between shielding gate 143 and the inner wall of gate trench 141, between control gate 142 and the inner wall of gate trench 141, and between shielding gate 143 and control gate 142. Shielding gate 143 and control gate 142 are made of polysilicon. Gate oxide layer 144 is made of, but is not limited to, silicon dioxide (SiO2). The thickness of the gate oxide layer 144 can be determined based on the withstand voltage that the device can withstand during reverse breakdown.

[0045] In this embodiment, the buffer layer 150 surrounds the gate trench 141, making the buffer layer 150 U-shaped. The conductivity type of the buffer layer 150 is N-type. The doping concentration range of the buffer layer 150 is 5E15cm⁻¹. -3 ~1E16cm -3 The doping concentration of the buffer layer 150 is greater than that of the epitaxial layer 120. The doping concentration of the buffer layer 150 can be 5 to 10 times that of the epitaxial layer 120. The specific values ​​of the doping concentrations of the buffer layer 150 and the epitaxial layer 120 can also be determined according to the voltage specifications of the device. The thickness of the buffer layer 150 ranges from 0.2 μm to 0.5 μm. The ionic materials of the buffer layer 150 include, but are not limited to, phosphorus (P), arsenic (As), and nitrogen (N). During the formation of the buffer layer 150, the implantation energy is 28 keV to 32 keV, such as 30 keV.

[0046] The buffer layer 150 includes a first buffer sublayer and a second buffer sublayer. Both the first and second buffer sublayers are located in the epitaxial layer 120 and below the doped region 130. The tops of both the first and second buffer sublayers are in contact with the doped region 130, and the bottom of the first buffer sublayer is in contact with the bottom of the second buffer sublayer, so as to enclose the gate trench 141 through the first and second buffer sublayers.

[0047] Specifically, in the fabrication process, a deep trench corresponding to the gate trench 141 is formed on the epitaxial layer 120 above the substrate 110, before the gate trench 141 is formed. In the deep trench, after placing the epitaxial layer 120 and the substrate 110 at 0°, phosphorus P ion implantation is performed at an implantation angle of 7°, forming a first buffer sublayer in the left "L" shape in the deep trench. Then, after rotating the epitaxial layer 120 and the substrate 110 180°, phosphorus P ion implantation is performed again at an implantation angle of 7°, forming a second buffer sublayer in the right reverse "L" shape in the deep trench. The implantation angle can be set according to actual needs. A "U"-shaped buffer layer 150 is formed through the bottom contact of the first and second buffer sublayers to enclose the gate trench 141.

[0048] The buffer layer 150 operates based on the principle of a parallel-plate capacitor formed by the shielding gate 143 (connected to the source) and the drain. Capacitance * voltage = charge. Therefore, the side of the shielding gate 143 corresponding to the epitaxial layer 120 (i.e., the area around the gate trench 141 within the epitaxial layer 120) will attract an equal amount of charge. If the doping concentration of the buffer layer 150 is high, the required charge formation thickness (i.e., the depletion broadening thickness of positive charge formation) will be thinner. This thinner thickness widens the current flow path. The buffer layer 150 is used to widen the current flow path, thereby reducing the on-resistance of the device.

[0049] In this embodiment, the buffer layer 150 surrounds the gate trench 141, and further surrounds the gate oxide layer 144, thus buffering the depletion broadening formed by the positive charge attracted by the gate region 140. When the device is turned on, the buffer layer 150 provides additional free electrons, improving the conductivity of the drift region of the epitaxial layer 120, further reducing the on-resistance, lowering the specific on-resistance of the device, and maintaining the stability of the breakdown voltage BVDSS (Breakdown Voltage Drain to Source). Therefore, the device structure of this embodiment also reduces the manufacturing cost of the device, offering advantages such as affordability and ease of operation.

[0050] The device structure in this embodiment also includes a dielectric layer 180, namely an ILD (Interlayer Dielectric) dielectric layer. The dielectric layer 180 is located above the epitaxial layer 120 and covers the doped region 130 and the gate region 140. The dielectric layer 180 serves to provide electrical isolation, mechanical support, and other functions.

[0051] The device structure of this embodiment further includes a front metal layer 160 as the source of the device. The front metal layer 160 is located above the dielectric layer 180 and covers the doped region 130 and the gate region 140. The device structure of this embodiment further includes a back metal layer 170 as the drain of the device. The back metal layer 170 is located below the substrate 110.

[0052] The performance of the SGT MOSFET device structure in this embodiment and the SGT MOSFET device structure without buffer layer 150 will be analyzed below:

[0053] The only difference between the SGT MOSFET device structure without buffer layer 150 and the SGT MOSFDET device structure of this embodiment is that the SGT MOSFDET device structure of this embodiment has buffer layer 150, and buffer layer 150 covers the gate trench 141 of the gate region 140. The SGT MOSFET device structure without buffer layer 150 is identical to the SGT MOSFET device structure of this embodiment except for the absence of buffer layer 150. Figure 2 As shown, the horizontal axis represents the drain voltage, and the vertical axis represents the drain current. The "new" curve represents the output characteristic curve of the SGT MOSFET device structure in this embodiment, and the "old" curve represents the output characteristic curve of the SGT MOSFET device structure without the buffer layer 150. Figure 2 It can be seen that, under the same drain voltage, the drain current of the SGT MOSFDET device structure in this embodiment is larger than that of the SGT MOSFDET device structure without buffer layer 150.

[0054] The principle behind this comparative analysis is that, under the same voltage conditions, the buffer layer shortens the depletion broadening width formed by the positive charge attracted by the gate region 140, thus increasing the current path. Under the same voltage conditions, compared to the SGT MOSFET device structure without the buffer layer 150, the SGT MOSFET device structure in this embodiment has a larger current path, lower on-resistance, and consequently lower specific on-resistance.

[0055] This demonstrates that the SGT MOSFET device structure in this embodiment reduces the specific on-resistance Rsp while maintaining a minimal change in breakdown voltage BVDSS, consistent with the breakdown voltage BVDSS of an SGT MOSFET device structure without the buffer layer 150. Furthermore, the SGT MOSFET device structure in this embodiment is compatible with existing processes, reducing production costs and offering advantages such as affordability and ease of operation.

[0056] One or more technical solutions in the embodiments of this utility model have at least the following technical effects or advantages:

[0057] In this embodiment, a buffer layer is provided between the gate trench in the gate region and the epitaxial layer on the substrate. This buffer layer encapsulates the gate trench and, in turn, the gate oxide layer, thereby reducing the depletion broadening caused by the positive charge attracted in the gate region. When the device is turned on, the width of the depletion broadening caused by the positive charge is shortened, the current path is increased, further reducing the on-resistance and the specific on-resistance of the device, while maintaining the stability of the breakdown voltage BVDSS (Breakdown Voltage Drain to Source), i.e., without affecting the original breakdown voltage BVDSS of the device. Thus, the device structure of this embodiment also reduces the manufacturing cost of the device, offering advantages such as affordability and ease of operation.

[0058] Those skilled in the art will understand that although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the present invention.

[0059] Obviously, those skilled in the art can make various modifications and variations to this utility model without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this utility model and their equivalents, this utility model also intends to include these modifications and variations.

Claims

1. An SGT MOSFET device structure, characterized in that, include: Substrate, epitaxial layer, doped region, gate region, and buffer layer; The epitaxial layer is located on the substrate; The doped region is located on the epitaxial layer; The gate region is located on the epitaxial layer and extends through the doped region; The buffer layer is located in the epitaxial layer and below the doped region, and surrounds the gate trench of the gate region.

2. The SGT MOSFET device structure as described in claim 1, characterized in that, The conductivity type of the buffer layer is N-type.

3. The SGT MOSFET device structure as described in claim 2, characterized in that, The thickness of the buffer layer ranges from 0.2µm to 0.5µm.

4. The SGT MOSFET device structure as described in claim 3, characterized in that, The buffer layer includes: a first buffer sub-layer and a second buffer sub-layer; Both the first buffer sublayer and the second buffer sublayer are located in the epitaxial layer and below the doped region; The tops of both the first and second buffer sublayers are in contact with the doped region, and the bottoms of the first and second buffer sublayers are in contact with the bottoms of the second buffer sublayers, so as to enclose the gate trench through the first and second buffer sublayers.

5. The SGT MOSFET device structure as described in any one of claims 1 to 4, characterized in that, The doped region includes: a P-well region and an N+ source region; The P-well region is located on the epitaxial layer; The N+ source region is located on the P-well region, wherein the surface of the N+ source region is at the same horizontal plane as the surface of the epitaxial layer.

6. The SGT MOSFET device structure as described in claim 5, characterized in that, The gate region includes: the gate trench, the control gate, the shielding gate, and the gate oxide layer; The gate trench extends through the P-well region and the N+ source region and is located in the epitaxial layer, with the bottom of the gate trench contacting the epitaxial layer; The shielding gate is located at the bottom of the gate trench; The control gate is located within the gate trench and above the shielding gate; The gate oxide layer fills the gate trench, between the shielding gate and the inner wall of the gate trench, between the control gate and the inner wall of the gate trench, and between the shielding gate and the control gate.

7. The SGT MOSFET device structure as described in any one of claims 1 to 4, characterized in that, Both the substrate and the epitaxial layer are N-type.

8. The SGT MOSFET device structure as described in any one of claims 1 to 4, characterized in that, Also includes: A dielectric layer, which is located above the epitaxial layer and covers the doped region and the gate region.

9. The SGT MOSFET device structure as described in claim 8, characterized in that, Also includes: Front metal layer and back metal layer; The front metal layer is located above the dielectric layer and covers the doped region and the gate region; The back metal layer is located beneath the substrate.

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