Semiconductor structure

Abstract

Some implementations of the present disclosure provide a semiconductor structure. The semiconductor structure includes a first dielectric layer on a substrate, a conductive layer including a plurality of conductive layer portions on the first dielectric layer, an isolation structure between a first conductive layer portion and a second conductive layer portion of the conductive layer portions, and a first selective metal layer on the first conductive layer portion. The isolation structure is bounded by a dielectric liner and includes a dielectric layer disposed on an air gap between sidewalls of the dielectric liner.

Description

Technical Field

[0001] This disclosure pertains to semiconductor structures. Background Technology

[0002] Semiconductor devices are used in a variety of electronic devices, such as personal computers, mobile phones, digital cameras, and other electronic devices. The manufacture of semiconductor devices typically involves depositing insulating or dielectric layers, conductive layers, and semiconductor layers sequentially on a semiconductor substrate and using lithography to pattern the various material layers to form circuit elements and units on them.

[0003] The semiconductor industry continuously increases the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, thereby allowing more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Utility Model Content

[0004] In some embodiments, a semiconductor structure includes a substrate, a first dielectric layer, a conductive layer, an isolation structure, and a first selective metal layer. The first dielectric layer is on the substrate. A conductive layer comprising multiple conductive layer portions is on the first dielectric layer. An isolation structure is located between the first conductive layer portion and a second conductive layer portion of these conductive layer portions, wherein the isolation structure is bounded by a dielectric pad and includes a dielectric layer disposed in air gaps between multiple sidewalls of the dielectric pad. The first selective metal layer is on the first conductive layer portion.

[0005] In some embodiments, a semiconductor structure includes a semiconductor structure having a ruthenium layer, an isolation structure, a first via dielectric layer, a first selective metal layer, and a second via dielectric layer. The isolation structure divides the ruthenium layer into multiple conductive layer portions, including a first conductive layer portion and a second conductive layer portion. The isolation structure is bounded by a dielectric pad and includes a dielectric layer disposed in an air gap between multiple sidewalls of the dielectric pad. The first via dielectric layer is on the semiconductor structure. The first selective metal layer extends through the first via dielectric layer to the first conductive layer portion. The second via dielectric layer is on the semiconductor structure.

[0006] In some embodiments, a semiconductor structure includes a substrate, a first dielectric layer, a conductive layer, an isolation structure, and a support layer. The first dielectric layer is on the substrate. The conductive layer is disposed on the first dielectric layer. The isolation structure divides the conductive layer into multiple conductive layer portions, including a first conductive layer portion and a second conductive layer portion, wherein the isolation structure is bounded by a dielectric pad and includes a dielectric layer disposed in an air gap between multiple sidewalls of the dielectric pad. The support layer is disposed between the dielectric layer and the air gap. Attached Figure Description

[0007] With accompanyingFigure 1 Reading this document will provide the best understanding of its various aspects from the following detailed description. It should be noted that, in accordance with industry standard practice, features may not be drawn to scale. In fact, for ease of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0008] Figure 1 This is a cross-sectional view of a portion of an exemplary semiconductor device in a stage of the integrated circuit manufacturing process, according to some embodiments.

[0009] Figure 2 This is a process flow diagram of an exemplary method for semiconductor manufacturing according to some embodiments, the method including forming a conductive structure including a wide metal portion;

[0010] Figures 3 to 20 These are cross-sectional views of a semiconductor structure at different stages of manufacturing, according to some implementation methods.

[0011] [Symbol Explanation]

[0012] 100: Semiconductor devices

[0013] 102: Substrate

[0014] 103: Conductive Structure

[0015] 104: Top Floor

[0016] 105: Dielectric layer

[0017] 106: Through-hole connection point

[0018] 107: Conductive layer

[0019] 108: Titanium nitride layer

[0020] 108-1: First titanium nitride layer

[0021] 108-2: Second titanium nitride layer

[0022] 108-3: Third titanium nitride layer

[0023] 109: Metal layer

[0024] 109-1: First metal layer portion

[0025] 109-2: Second metal layer portion

[0026] 109-3: Third metal layer portion

[0027] 110: Isolation Structure

[0028] 111: Dielectric Pad

[0029] 112: Dielectric material layer

[0030] 114: Air gap

[0031] 116: Support layer

[0032] 117: Altitude

[0033] 118: Thickness

[0034] 120: First selective metal layer

[0035] 122: Second selective metal layer

[0036] 123: First Metal Height

[0037] 124: Second Metal Height

[0038] 126: Dielectric layer

[0039] 128: Dielectric pad layer

[0040] 130: Dielectric material layer

[0041] 132: Etching Stop Layer

[0042] 200: Method

[0043] 202: Square

[0044] 204: Square

[0045] 206: Square

[0046] 208: Square

[0047] 210: Square

[0048] 212: Square

[0049] 214: Square

[0050] 216: Square

[0051] 218: Square

[0052] 220: Square

[0053] 222: Square

[0054] 224: Square

[0055] 226: Square

[0056] 228: Square

[0057] 230: Square

[0058] 232: Square

[0059] 234: Square

[0060] 236: Square

[0061] 300: Semiconductor Structure

[0062] 302: Substrate

[0063] 303: Through hole

[0064] 304: Interlayer dielectric layer

[0065] 305: Top Floor

[0066] 306: First titanium nitride layer

[0067] 307: Conductive layer

[0068] 308: Metallic layer

[0069] 308-1: First metal layer portion

[0070] 308-2: Second metal layer portion

[0071] 308-3: Third metal layer portion

[0072] 309: Altitude

[0073] 310: Second titanium nitride layer

[0074] 311: Masking layer

[0075] 312: Silicon nitride layer

[0076] 314: Silicon oxide layer

[0077] 316: Opening

[0078] 317: Top width

[0079] 318: Dielectric Pad

[0080] 319: Bottom width

[0081] 320: Sacrificial polymer layer

[0082] 321: Thickness

[0083] 322: Support layer

[0084] 323: Isolation Structure

[0085] 324: Air gap

[0086] 325: Height

[0087] 326: Dielectric layer

[0088] 327: Dielectric layer of the first via

[0089] 328: Silicon nitride layer

[0090] 329: Wide metal opening

[0091] 330: Low-k dielectric material layer

[0092] 331: Second via dielectric layer

[0093] 332: Silicon nitride layer

[0094] 334: Dielectric layer

[0095] 335: Through-hole opening

[0096] 336: Through hole

[0097] 338: Wide metal layer

[0098] 339: Altitude

[0099] 340: Etching Stop Layer

[0100] 341: Altitude Detailed Implementation

[0101] The following disclosure provides many different implementations or examples for achieving different functions. To simplify this disclosure, specific examples of elements and compositions are described below. Of course, these are merely examples and are not intended to limit the scope of this disclosure. For example, in the following description, forming a first feature on or above a second feature can include implementations where the first and second features are formed through direct contact, or implementations where additional features may be formed between the first and second features, allowing the first and second features to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various implementations. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various implementations and / or configurations discussed.

[0102] Furthermore, for ease of description, this document may use spatial relative terms such as "above," "upper layer," "upper part," "above," "top," "bottom," "lower layer," "lower part," "below," "below," "bottom," "side," etc., to describe the relationship between one element or feature and another element or feature in the figures. In addition to the directions depicted in the figures, spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or other orientations), and the spatial relative terms used herein will be interpreted accordingly.

[0103] When spatial relative terms (such as those listed above) are used to describe the first element relative to the second element, the first element may be directly on top of the other element, or there may be intermediate elements or layers. When an element or layer is said to be "above" another element or layer, it may be directly on top of the other element or layer and in contact with other elements or layers.

[0104] In some embodiments herein, "material layer" means a layer comprising at least 50 wt% of the material, for example, at least 60 wt% of the material, or at least 75 wt% of the material, or at least 90 wt% of the material; a layer as "material" means comprising at least 50 wt% of the material, for example, at least 60 wt% of the material, at least 75 wt% of the material, or at least 90 wt% of the material. For example, in some embodiments, a titanium nitride layer and a layer of titanium nitride both refer to a layer of at least 50 wt%, at least 60 wt%, at least 75 wt%, or at least 90 wt% titanium nitride.

[0105] For the sake of brevity, this document may not describe in detail the conventional techniques associated with the manufacture of conventional semiconductor devices. Furthermore, the various operations and processes described herein may be incorporated into a more comprehensive process or procedure, which may have additional functionalities not described in detail herein. In particular, the various processes involved in the manufacture of semiconductor devices may be well-known; therefore, for the sake of brevity, many conventional processes will only be briefly mentioned or omitted entirely without providing well-known process details. As will be apparent to those skilled in the art upon a full reading of this disclosure, the structures disclosed herein may be used with various techniques and may be incorporated into various semiconductor devices and products. Furthermore, it should be noted that the structure of a semiconductor device includes a varying number of elements, and a single element shown in a figure may represent multiple elements.

[0106] The embodiments described herein are used to form conductive interconnect structures. Specifically, the embodiments described herein can provide the use of metals such as ruthenium (Ru) to form conductive interconnect structures. For example, the embodiments described herein can provide the formation of an isolation structure in a conductive interconnect formed using ruthenium, and the interface between the low-k dielectric layer and the metal conductor layer is not damaged by the low-k dielectric, thus resulting in a higher capacitance value. The embodiments described herein can provide conductive interconnect structures with reduced or adjustable resistance. Compared to metal conductors (e.g., copper (Cu)), the embodiments described herein can provide lower carrier scattering (and thus lower resistance). The embodiments described herein can provide lower resistance because there is no barrier between the low-k dielectric layer and the conductive metal layer. The embodiments described herein can provide lower resistance because there is less electron scattering. The embodiments described herein can provide lower resistance because selective metal growth is performed on the conductive metal layer. The embodiments described herein can provide lower capacitance values ​​because the isolation structure includes an air gap. The embodiments described herein can be applied to various semiconductor devices, such as those using fin field-effect transistors (FinFETs), gate-all-around field-effect transistors (GAAFETs), and complementary field-effect transistors (CFETs).

[0107] Figure 1This is a cross-sectional view of a portion of an exemplary semiconductor device 100 in a stage of an integrated circuit manufacturing process according to one embodiment. The semiconductor device 100 shown has circuitry formed in and / or on a substrate 102 and conductive structures 103 formed on the substrate. The substrate 102 can be one of many types of semiconductor substrates commonly used in the manufacture of semiconductor integrated circuits, and integrated circuits may be formed therein and / or on it. The semiconductor substrate can be any structure comprising semiconductor materials, such as, but not limited to, bulk silicon, semiconductor wafers, silicon-on-insulator (SOI) substrates, or silicon-germanium substrates. Other semiconductor materials can be used, such as semiconductors comprising Group III, Group IV, and / or Group V. Although not shown, the substrate 102 may also include multiple isolation features, such as shallow trench isolation (STI) features or local oxidation of silicon (LOCOS) features. The isolation features can isolate various microelectronic components formed in and / or on the substrate 102. Examples of types of microelectronic components that can be formed in substrate 102 include, but are not limited to: transistors, such as metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, p-channel field effect transistors (PFETs) and / or n-channel field effect transistors (NFETs); resistors; diodes; capacitors; inductors; fuses and / or other suitable components. Various processes can be performed to form various microelectronic components, including, but not limited to, deposition, etching, placement, lithography, annealing, and one or more other suitable processes. These microelectronic components are interconnected to form an integrated circuit, and the device may include one or more of logic devices, memory devices (e.g., static random-access memory, SRAM), radio frequency (RF) devices, input / output (I / O) devices, system-on-chip (SoC) devices, and other suitable types of devices.

[0108] The exemplary substrate 102 also includes a top layer 104. The top layer 104 may include various structures, such as a dielectric layer 105 (e.g., an interlayer dielectric (ILD) layer) and one or more via (VIA) connection points 106 for electrical connection to microelectronic components on or within the substrate 102.

[0109] An exemplary conductive structure 103 includes a conductive layer 107 disposed on a dielectric layer 105, wherein the conductive layer 107 includes a titanium nitride (TiN) layer 108 and a metal layer 109, and one or more isolation structures 110 are configured to divide the conductive layer 107 into multiple conductive layer portions (e.g., a first conductive layer portion includes a first metal layer portion 109-1 and a first titanium nitride layer portion 108-1, a second conductive layer portion includes a second metal layer portion 109-2 and a second titanium nitride layer portion 108-2, and a third conductive layer portion includes a third metal layer portion 109-3 and a third titanium nitride layer portion 108-3). In various embodiments, the metal layer 109 is formed of ruthenium (Ru).

[0110] One or more isolation structures 110 in the examples define boundaries through dielectric pads 111 and include a dielectric material layer 112 disposed above an air gap 114 located between the sidewalls of the dielectric pads 111. One or more isolation structures 110 in the examples may include a support layer 116 disposed between the dielectric material layer 112 and the air gap 114. In various embodiments, the dielectric pads 111 are formed of a polymer (e.g., silicon oxycarbide (SiOC)), the dielectric material layer 112 is formed of a low-k dielectric (e.g., porous silicon oxycarbide), and the support layer 116 is formed of silicon oxide (SiO). In various embodiments, the dielectric constant (k-value) of the low-k dielectric material may be less than about 3.9 or less than about 2.8. In various embodiments, the height 117 of the air gap is from about 10 nm to about 20 nm. In various embodiments, the thickness 118 of the dielectric pads 111 is from about 0.5 nm to about 3 nm.

[0111] The exemplary conductive structure 103 further includes a first selective metal layer 120 formed on a first metal layer portion 109-1 and a second selective metal layer 122 formed on a third metal layer portion 109-3. The resistivity of the first selective metal layer 120 is lower than that of the first metal layer portion 109-1. The resistivity of the second selective metal layer 122 is lower than that of the third metal layer portion 109-3. The first metal layer portion 109-1 is configured to provide a wide metal region in the semiconductor device 100, such as providing a wire, metal trace, or metal conductor. The third metal layer portion 109-3 is configured to provide a connection between an element located in a substrate and a metal trace located in a conductive layer on the conductive structure 103.

[0112] The first selective metal layer 120 has a first metal height 123, which is selected to achieve a predetermined resistance range for the first hybrid metal portion, which includes a first metal layer portion 109-1 and the first selective metal layer 120. The required resistance of the first hybrid metal portion can be achieved by increasing the first metal height 123 and correspondingly decreasing the height of the first metal layer portion 109-1. In various embodiments, the first metal height 123 of the first selective metal layer 120 is between about 5 nm and about 20 nm. The combination of the first metal layer portion 109-1 and the first selective metal layer 120 constitutes the first hybrid metal portion, which is configured to provide adjustable resistance, and the adjustable resistance is adjusted based on the height of the first metal layer portion 109-1 and the height of the first selective metal layer 120. In various embodiments, the first selective metal layer 120 is formed of one or more of tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru), rhodium (Rh), iridium (Ir), or other suitable materials. In various embodiments, the first selective metal layer 120 is formed of materials having λ*ρ0 < 7 x 10⁻⁶. -16 Ω*m 2 The metal is formed, where ρ0 is the resistivity of the metal and λ is the mean free path of electrons in the metal at room temperature. In various embodiments, the desired resistance range can be achieved by selecting the metal used in the first selective metal layer 120. This is particularly useful for wide metal regions (e.g., metal traces) and static random access memory regions, where these regions may suffer from resistance-capacitance (RC) degradation when Ru is used as the metal layer 109.

[0113] The second selective metal layer 122 has a second metal height 124, which is selected to achieve a predetermined resistance range for the second mixed metal portion, and this second mixed metal portion includes a third metal layer portion 109-3 and the second selective metal layer 122. In various embodiments, the second metal height 124 of the second selective metal layer 122 is between about 0 nm and about 5 nm and is less than the first metal height 123. The combination of the third metal layer portion 109-3 and the second selective metal layer 122 constitutes the second mixed metal portion, which is configured to provide adjustable resistance, and the adjustable resistance is adjusted based on the height of the third metal layer portion 109-3 and the height of the second selective metal layer 122. In various embodiments, the second selective metal layer 122 is formed of one or more of tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru), rhodium (Rh), iridium (Ir), or other suitable materials. In various embodiments, the second selective metal layer 122 is formed of the same metallic material as the first selective metal layer 120. In various embodiments, the second selective metal layer 122 is composed of metals having λ*ρ0 < 7x10 -16 Ω*m 2 The metal is formed, where ρ0 is the resistivity of the metal and λ is the mean free path of electrons in the metal at room temperature. In various embodiments, the desired resistance range can be achieved by selecting the metal used in the second selective metal layer 122. The second selective metal layer 122 is configured as a via (VIA) between the third metal layer portion 109-3 and the upper conductive layer on the subsequently formed conductive structure 103.

[0114] The exemplary conductive structure 103 further includes a second dielectric layer 126, which includes a dielectric pad layer 128 and a dielectric material layer 130. The dielectric layer 126 is formed on multiple portions of the metal layer 109, including the second metal layer portion 109-2, on one or more isolation structures 110, on the sidewalls of the first selective metal layer 120, and on the sidewalls of the second selective metal layer 122. The exemplary conductive structure 103 also includes an etch stop layer 132 formed on the dielectric layer and the first selective metal layer.

[0115] Figure 2 This is a process flow diagram describing an exemplary method 200 in semiconductor manufacturing, which includes forming a conductive structure (e.g., conductive structure 103) including a wide metal portion (e.g., a first metal layer portion 109-1). Figure 2 Combination Figures 3 to 20 Describe, and Figures 3 to 20Semiconductor structure 300 at various stages of manufacturing according to some embodiments is shown. Method 200 is merely an example and is not intended to limit the scope of this disclosure beyond that expressly set forth in the claims. Additional steps may be provided before, between, and after method 200, and some steps described may be moved, replaced, or eliminated for additional embodiments of method 200. Additional features may be added to the semiconductor structure 300 depicted in the figures, and some features described below may be replaced, modified, or eliminated in other embodiments.

[0116] As can be understood from the other methods and exemplary apparatus discussed herein, multiple parts of a semiconductor structure can be manufactured using typical semiconductor technology processes; therefore, only some processes are briefly described herein. Furthermore, exemplary semiconductor structures may include a variety of other devices and features, such as other types of devices, such as additional transistors, bipolar transistors, resistors, capacitors, inductors, dials, fuses, and / or other logic devices, but these may be simplified for a better understanding of the concepts disclosed herein.

[0117] At block 202, the exemplary method 200 includes providing a substrate having an interlayer dielectric (ILD) layer and one or more vias disposed in the top layer of the substrate, providing a first titanium nitride layer disposed on the top layer, providing a conductive layer disposed on the first titanium nitride layer, and providing a second titanium nitride layer disposed on the conductive layer. (Reference) Figure 3 For example, in the embodiment of block 202, substrate 302 has an interlayer dielectric layer 304 and one or more vias 303 disposed in the top layer 305 of the substrate, and a conductive layer 307 disposed on the top layer 305, wherein the conductive layer 307 includes a first titanium nitride layer 306 disposed on the top layer 305, a metal layer 308 disposed on the first titanium nitride layer 306, and a second titanium nitride layer 310 disposed on the metal layer 308. In various embodiments, the metal layer 308 includes a transition metal. In various embodiments, the transition metal includes ruthenium (Ru). In various embodiments, the metal layer 308 has a height 309 of about 15 nm to about 40 nm.

[0118] At block 204, exemplary method 200 includes forming a masking layer on the conductive layer. In various embodiments, the masking layer is disposed on a second titanium nitride layer. (See reference...) Figure 4For example, in the embodiment of block 204, the masking layer 311 is formed on the second titanium nitride layer. In various embodiments, the masking layer 311 includes multiple sublayers. In various embodiments, the multiple layers of the masking layer 311 include a silicon nitride layer 312 and a silicon oxide layer 314. The masking layer can be formed by any suitable method, such as by chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0119] At block 206, exemplary method 200 includes patterning a conductive layer to form openings. Patterning the conductive layer includes forming openings that separate the conductive layer into different conductive portions. Forming the openings may include using a reactive ion etching (RIE) technique on the conductive layer. (Reference) Figure 5 For example, in the embodiment of block 206, the conductive layer 307 is patterned to form multiple patterned portions of the conductive layer 307. The multiple patterned portions of the conductive layer 307 are separated by openings 316 formed by patterning and etching the mask layer 311, the second titanium nitride layer 310, the metal layer 308, and the first titanium nitride layer 306, and are located on the interlayer dielectric layer 304. Etching can be performed using a suitable etching technique (e.g., by reactive ion etching). In various embodiments, the openings 316 are wider at the top and narrower at the bottom, and slope inwards from top to bottom. In various embodiments, the multiple patterned portions of the conductive layer 307 are narrower at the top and wider at the bottom, and have sidewalls that slope outwards from top to bottom. The multiple patterned portions of the conductive layer 307 can serve as via portions and wide metal portions. The via portions are used to support vias to higher metal layers, and the wide metal portions are used to provide metal traces or wires in a semiconductor structure. In various embodiments, the upper width 317 of the via portion is about 6 nm to about 10 nm, and the lower width 319 is about 8 nm to about 12 nm.

[0120] At block 208, the exemplary method 200 includes forming a dielectric pad on the mask layer and in the opening. (Reference) Figure 6 For example, in the embodiment of block 208, a dielectric pad 318 is formed on the mask layer 311 and in the opening 316. In various embodiments, the dielectric pad 318 is formed of a polymer-derived ceramic (e.g., silicon carbide (SiOC)). In various embodiments, the thickness 321 of the dielectric pad 318 is from about 0.5 nm to about 3 nm.

[0121] At block 210, exemplary method 200 includes forming a sacrificial polymer layer on a dielectric pad. (Reference) Figure 7For example, in the embodiment of block 210, a sacrificial polymer layer 320 is formed on the dielectric pad 318. In various embodiments, the sacrificial polymer layer 320 is formed of ashless carbon (ALC). The sacrificial polymer layer 320 can be formed by any suitable method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0122] At block 212, exemplary method 200 includes etching back the sacrificial polymer layer to a predetermined height. The predetermined height is set to the height of the subsequently formed air gap. (See reference...) Figure 8 For example, in the embodiment of block 212, the sacrificial polymer layer 320 is etched back to a predetermined height in the opening 316.

[0123] On block 214, exemplary method 200 includes forming a support layer on a dielectric pad and a sacrificial polymer layer. (Reference) Figure 9 For example, in the embodiment of block 214, a support layer 322 is formed on the dielectric pad 318 and the sacrificial polymer layer 320. In various embodiments, the support layer 322 is made of a dielectric material (e.g., silicon oxide (SiO2)). x The support layer 322 can be formed by any suitable deposition method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. In various embodiments, the sacrificial polymer layer 320 has a concave top surface after etch-back, and the support layer 322 has a rounded bottom surface.

[0124] At block 216, exemplary method 200 includes removing the sacrificial polymer layer to form an air gap. In various embodiments, removing the sacrificial polymer layer 320 includes performing an ashing operation, wherein the sacrificial polymer layer 320 is burned off. Reference Figure 10 For example, in the embodiment of block 216, an air gap 324 is formed in the opening 316 between the support layer 322 and the dielectric pad 318. In various embodiments, the air gap 324 has a height 325 of about 10 nm to about 20 nm. In various embodiments, not all of the sacrificial polymer layer 320 is burned off, and a small portion of the sacrificial polymer layer 320 may remain in the air gap 324.

[0125] At block 218, the exemplary method 200 includes forming a dielectric layer on the support layer. (See reference...) Figure 11 For example, in the embodiment of block 218, a dielectric layer 326 is formed on the support layer 322. In various embodiments, the dielectric layer 326 is formed of a low-k oxide (e.g., porous silicon carbide). The dielectric layer 326 can be formed by any suitable deposition method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0126] In various implementations, blocks 206 to 218 are formed as follows: Figure 13 One or more isolation structures 323 (also refer to isolation structure 110) are provided in the metal layer 308, which divide the metal layer 308 into multiple metal layer portions, namely a first metal layer portion 308-1, a second metal layer portion 308-2 and a third metal layer portion 308-3.

[0127] At block 220, exemplary method 200 includes planarizing a semiconductor structure. In various embodiments, planarizing the structure includes removing the top layer of dielectric layer 326, support layer 322, dielectric pad 318, and removing mask layer 311 and second titanium nitride layer 310. In various embodiments, planarizing the semiconductor structure includes performing a chemical mechanical polishing (CMP) operation on the semiconductor structure. Reference Figure 12 For example, in the embodiment of block 220, the semiconductor structure 300 is planarized to remove the top layer of dielectric layer 326, support layer 322, and dielectric pad 318, as well as the mask layer 311 and the second titanium nitride layer 310. The portions of conductive layer 307 remain. The portions of conductive layer 307 are separated by dielectric pad 318, air gap 324, support layer 322, and dielectric layer 326.

[0128] At block 222, exemplary method 200 includes forming a first via dielectric layer on a semiconductor structure. In various embodiments, the first via dielectric layer includes a silicon nitride layer and a low-k dielectric material layer. (See reference...) Figure 13 For example, in the embodiment of block 222, a first via dielectric layer 327 is formed on the semiconductor structure 300. The first via dielectric layer 327 includes a silicon nitride layer 328 and a low-k dielectric material layer 330. The silicon nitride layer 328 is formed on the semiconductor structure 300, and the low-k dielectric material layer 330 is formed on the silicon nitride layer 328. In various embodiments, the low-k dielectric material layer 330 is formed of a low-k oxide (e.g., porous silicon carbide). The low-k dielectric material layer 330 can be formed by any suitable deposition method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. The silicon nitride layer 328 can be formed by any suitable deposition method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0129] At block 224, exemplary method 200 includes forming a wide metal opening through the first via dielectric layer to reach a metal layer. In various embodiments, forming the wide metal opening includes a photolithography operation to define the location of the wide metal opening and an etching operation to etch out the wide metal opening. The etching operation to etch out the wide metal opening may include a reactive ion etching (RIE) operation. Reference Figure 14 For example, in the embodiment of block 224, a wide metal opening 329 is formed through the first via dielectric layer to reach the metal layer 308.

[0130] At block 226, exemplary method 200 includes forming a wide metal layer in a wide metal opening on a wide metal portion of the metal layer. In various embodiments, forming the wide metal layer includes selective growth operations, such as selective atomic layer deposition or selective chemical vapor deposition. Reference Figure 15 For example, in the embodiment of block 226, a wide metal layer 338 is formed in a wide metal opening 329. The wide metal layer 338 is configured to provide a low-resistance electrical connection between the wide metal portion located in metal layer 308 and the conductive portion subsequently formed in a higher layer.

[0131] The wide metal layer 338 can be formed from one or more of tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru), rhodium (Rh), iridium (Ir), or other suitable materials. The wide metal layer 338 can also be formed from materials having λ*ρ0 < 7x10 -16 Ω*m 2 Metal formation.

[0132] At block 228, exemplary method 200 includes forming a second via dielectric layer on a semiconductor structure. In various embodiments, the second via dielectric layer includes a silicon nitride layer and a low-k dielectric layer. (See reference...) Figure 16 For example, in the embodiment of block 228, a second via dielectric layer 331 is formed on the semiconductor structure 300. The second via dielectric layer 331 includes a silicon nitride layer 332 and a dielectric layer 334. The silicon nitride layer 332 is formed on the semiconductor structure 300, and the dielectric layer 334 is formed on the silicon nitride layer 332. In various embodiments, the dielectric layer 334 is formed of a low-k oxide (e.g., porous silicon oxide). The dielectric layer 334 can be formed by any suitable deposition method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. The silicon nitride layer 332 can be formed by any suitable deposition method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0133] At block 230, exemplary method 200 includes forming a via opening through a first via dielectric layer and a second via dielectric layer to reach a metal layer. In various embodiments, forming the via opening includes a photolithography operation to define the location of the opening and an etching operation to etch the opening. (See also...) Figure 17 For example, in the embodiment of block 230, the via opening 335 is formed in the first via dielectric layer 327 and the second via dielectric layer 331.

[0134] At block 232, exemplary method 200 includes forming a via (VIA) in the via opening. In various embodiments, forming the via includes selective growth operations, such as selective atomic layer deposition or selective chemical vapor deposition. Reference Figure 18 For example, in the embodiment of block 232, a via 336 is formed in the via opening 335. The via 336 is configured to provide a low-resistance electrical connection between conductive portions of two or more horizontal planes and / or layers in the semiconductor structure 300. The via 336 may be formed from one or more of copper (Cu), silver (Ag), tungsten (W), titanium (Ti), nickel (Ni), tin (Sn), aluminum (Al), or other metals or materials suitable for providing a low-resistance electrical connection between layers of a semiconductor structure. In some embodiments, the bottom of the via 336 may partially cover (i.e., contact) the top surface of one or more of the dielectric pad 318, support layer 322, and / or dielectric layer 326.

[0135] At block 234, exemplary method 200 includes planarizing a semiconductor structure. In various embodiments, planarizing the semiconductor structure includes performing a chemical mechanical planarization operation to planarize the via 336, the first via dielectric layer 327, and the wide metal layer 338 to a predetermined height. (Refer to...) Figure 19 For example, in the embodiment of block 234, via 336, the first via dielectric layer 327, and the wide metal layer 338 are planarized to a predetermined height. In various embodiments, via 336 has a wider top and a narrower bottom, wherein the sidewalls of via 336 slope inward. In various embodiments, the metal layer 308 located directly below via 336 has a narrower top portion and a wider bottom portion, wherein the sidewalls of metal layer 308 slope outward from top to bottom. In some embodiments, the bottom of the wide metal layer 338 may partially cover (i.e., contact) the top surface of one or more of the dielectric pad 318, support layer 322, and / or dielectric layer 326.

[0136] At block 236, exemplary method 200 includes forming an etch stop layer (ESL) on the semiconductor structure. (Refer to...) Figure 20For example, in the embodiment of block 236, an etch stop layer 340 is formed on via 336, a first via dielectric layer 327, and a wide metal layer 338. In various embodiments, the wide metal layer 338 has a height 339 of about 5 nm to about 20 nm. In various embodiments, the height 341 of via 336 is about 0 nm to about 5 nm lower than the height 339.

[0137] In various embodiments, the mixed height (e.g., the first metal height 123 plus the height of the first metal layer portion 109-1) provides adjustable resistance-capacitance (RC). This is beneficial for logic and static random access memory devices. In various embodiments, the use of a second selective metal layer (e.g., second selective metal layer 122) can alleviate gap filling problems when forming vias. In various embodiments, reactive ion etching of the metal layer (e.g., metal layer 109) with ruthenium can provide lower bulk resistance, protection against damage at low k values, and suitability for barrier-less integration. The various embodiments described herein are applicable to devices using fin field-effect transistors, all-gate field-effect transistors, and complementary field-effect transistors.

[0138] Some embodiments of this disclosure provide a method for manufacturing a semiconductor structure. The method includes the following operations: providing a semiconductor structure having an interlayer dielectric layer and one or more vias (VIAs) disposed in a top layer of a substrate, having a first dielectric layer (e.g., a first titanium nitride) disposed on the top layer, having a conductive layer disposed on the first dielectric layer, and having a second dielectric layer (e.g., a second titanium nitride) disposed on the conductive layer; forming an isolation structure that divides the conductive layer into multiple conductive layer portions, each conductive layer portion including a first conductive layer portion and a second conductive layer portion, wherein the isolation structure includes a dielectric layer disposed in an air gap; forming a first via dielectric layer on the semiconductor structure; forming a first metal opening through the first via dielectric layer to reach a metal layer in the first conductive layer portion; and forming a first selective metal layer in the first metal opening.

[0139] In some embodiments, the method further includes the following operations: forming a second via dielectric layer on the semiconductor structure; planarizing the semiconductor structure; and forming an etch stop layer on the semiconductor structure.

[0140] In some implementations, the conductive layer is formed of ruthenium (Ru).

[0141] In some embodiments, forming the isolation structure includes the following operations: forming an opening in the conductive layer; forming a dielectric pad on the second dielectric layer and in the opening of the isolation structure; forming a sacrificial polymer layer on the dielectric pad; etching back the sacrificial polymer layer; forming a support layer on the dielectric pad and the sacrificial polymer layer; removing the sacrificial polymer layer to form an air gap; and forming a dielectric layer on the support layer.

[0142] In some embodiments, the first selective metal layer and the first conductive layer constitute a first hybrid metal portion, which is configured to provide adjustable resistance by adjusting a plurality of heights of the first selective metal layer and the first conductive layer.

[0143] In some embodiments, the first selective metal layer and the first conductive layer constitute a first mixed metal portion, which is configured to provide adjustable resistance by adjusting the metal material used in the first selective metal layer.

[0144] In some implementations, the first selective metal layer has a metal height between 5 nm and 20 nm.

[0145] In some implementations, the first conductive layer portion is configured to form a metal wire for a semiconductor structure.

[0146] In some embodiments, the first selective metal layer is formed of one or more of tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru), rhodium (Rh), or iridium (Ir).

[0147] In some embodiments, the first selective metal layer is composed of a metal having λ*ρ0 < 7x10 -16 Ω*m 2 Metal formation.

[0148] In some embodiments, the conductive layer portion includes a third conductive layer portion, and the method further includes the following operations: forming a via opening through a first via dielectric layer, through a second via dielectric layer, and in the third conductive layer portion; forming a second selective metal layer in the via opening on the third conductive layer portion, wherein the second selective metal layer is configured as a via located between the third conductive layer portion and a subsequently formed upper conductive layer.

[0149] In some embodiments, the second selective metal layer has a metal height between 0 nm and 5 nm and is less than the height of the first selective metal layer.

[0150] In some embodiments, the second selective metal layer has a metal height, which is selected to achieve a predetermined resistance range for the second mixed metal portion, which includes the second selective metal layer and the third conductive layer portion.

[0151] In some embodiments, the second selective metal layer is formed from a metallic material used to form the first selective metal layer.

[0152] In some embodiments, the second selective metal layer and the third conductive layer constitute a second mixed metal portion, which is configured to provide adjustable resistance by adjusting the metal material used in the second selective metal layer.

[0153] In some embodiments, the conductive layer portion includes a third conductive layer portion, and the method further includes the following operations: forming a via opening through a first via dielectric layer and in the third conductive layer portion; forming a second selective metal layer in the via opening on the third conductive layer portion, wherein the second selective metal layer is configured as a via located between the third conductive layer portion and a subsequently formed upper conductive layer.

[0154] Some embodiments of this disclosure also provide a semiconductor structure. The semiconductor structure includes a first dielectric layer on a substrate, a conductive layer comprising multiple conductive layer portions on the first dielectric layer, an isolation structure located between the first conductive layer portion and a second conductive layer portion, and a first selective metal layer formed on the first conductive layer portion. The isolation structure is bounded by a dielectric pad and includes a dielectric material layer disposed in an air gap between multiple sidewalls of the dielectric pad. The first selective metal layer has a resistivity lower than that of the first conductive layer portion.

[0155] In some embodiments, the semiconductor structure further includes a second dielectric layer formed on the second conductive layer portion and the isolation structure and on the sidewall of the first selective metal layer, and also includes an etch stop layer formed on the second dielectric layer and the first selective metal layer.

[0156] In some implementations, the conductive layer is formed of ruthenium (Ru).

[0157] In some embodiments, the semiconductor structure further includes a support layer disposed between the dielectric material layer and the air gap.

[0158] In some embodiments, the first selective metal layer has a metal height, which is selected to achieve a predetermined resistance range for the first mixed metal portion, which includes the first selective metal layer and the first conductive layer portion.

[0159] In some implementations, the first selective metal layer has a metal height between 5 nm and 20 nm.

[0160] In some implementations, the first conductive layer portion is configured to form a metal wire for a semiconductor structure.

[0161] In some embodiments, the first selective metal layer and the first conductive layer constitute a first mixed metal portion, which is configured to provide adjustable resistance by adjusting the metal material used in the first selective metal layer.

[0162] In some embodiments, the first selective metal layer is formed of one or more of tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru), rhodium (Rh), or iridium (Ir).

[0163] In some embodiments, the first selective metal layer is composed of a metal having λ*ρ0 < 7x10 -16 Ω*m 2 Metal formation.

[0164] In some embodiments, the semiconductor structure further includes a third conductive layer portion of the conductive layer portion; and a second selective metal layer formed on the third conductive layer portion, below the etch stop layer, and in an opening in the second dielectric layer. The resistivity of the second selective metal layer is lower than that of the second conductive layer portion. The second selective metal layer is configured as a via between the third conductive layer portion and the subsequently formed upper conductive layer.

[0165] In some embodiments, the second selective metal layer has a metal height between 0 nm and 5 nm and is less than the height of the first selective metal layer.

[0166] In some embodiments, the second selective metal layer has a metal height, which is selected to achieve a predetermined resistance range for the second mixed metal portion, which includes the second selective metal layer and the third conductive layer portion.

[0167] In some embodiments, the second selective metal layer is formed from a metallic material used to form the first selective metal layer.

[0168] In some embodiments, the second selective metal layer and the third conductive layer constitute a second mixed metal portion, which is configured to provide adjustable resistance by adjusting the metal material used in the second selective metal layer.

[0169] In some embodiments, the second selective metal layer is formed of one or more of tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru), rhodium (Rh), or iridium (Ir).

[0170] In some embodiments, the second selective metal layer is composed of a metal having λ*ρ0 < 7x10 -16 Ω*m 2 Metal formation.

[0171] In some embodiments, the first selective metal layer is made of tungsten, molybdenum, cobalt, ruthenium, rhodium, iridium, or has a λ*ρ0 < 7x10 -16 Ω*m 2 Metal formation.

[0172] Some embodiments of this disclosure also provide a method for manufacturing a semiconductor structure. The method includes the following operations: providing a semiconductor structure having a ruthenium layer; forming an isolation structure that divides the ruthenium layer into multiple conductive layer portions, each conductive layer portion including a first conductive layer portion and a second conductive layer portion, wherein the isolation structure includes a dielectric layer disposed on an air gap; forming a first via dielectric layer on the semiconductor structure; forming a first metal opening through the first via dielectric layer to reach the first conductive layer portion; forming a first selective metal layer in the first metal opening, the first selective metal layer being selected to achieve a desired resistance in a first mixed metal portion including the first selective metal layer and the first conductive layer portion; forming a second via dielectric layer on the semiconductor structure; planarizing the semiconductor structure; and forming an etch stop layer on the semiconductor structure.

[0173] In some embodiments, forming the isolation structure includes the following operations: forming an opening in the ruthenium layer; forming a dielectric pad on the second titanium nitride layer and in the opening of the isolation structure; forming a sacrificial polymer layer on the dielectric pad; etching back the sacrificial polymer layer to a predetermined height; forming a support layer on the dielectric pad and the sacrificial polymer layer; removing the sacrificial polymer layer to form an air gap; and forming a dielectric layer on the support layer.

[0174] In some embodiments, the first selective metal layer and the first conductive layer constitute a first hybrid metal portion, which is configured to provide adjustable resistance by adjusting a plurality of heights of the first selective metal layer and the first conductive layer.

[0175] In some embodiments, the first selective metal layer and the first conductive layer constitute a first mixed metal portion, which is configured to provide adjustable resistance by adjusting the metal material used in the first selective metal layer.

[0176] In some implementations, the first selective metal layer has a metal height between 5 nm and 20 nm.

[0177] In some implementations, the first conductive layer portion is configured to form a metal wire for a semiconductor structure.

[0178] In some embodiments, the first selective metal layer is formed of one or more of tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru), rhodium (Rh), or iridium (Ir).

[0179] In some embodiments, the first selective metal layer is composed of a metal having λ*ρ0 < 7x10 -16 Ω*m 2 Metal formation.

[0180] In some embodiments, the ruthenium layer includes a third conductive layer portion, and the method further includes the following operations: forming a via opening through a first via dielectric layer, through a second via dielectric layer, and in the third conductive layer portion; forming a second selective metal layer in the via opening on the third conductive layer portion, wherein the second selective metal layer is configured as a via located between the third conductive layer portion and a subsequently formed upper conductive layer.

[0181] In some embodiments, the second selective metal layer has a metal height between 0 nm and 5 nm and is less than the height of the first selective metal layer.

[0182] In some embodiments, the second selective metal layer has a metal height, which is selected to achieve a predetermined resistance range for the second mixed metal portion, which includes the second selective metal layer and the third conductive layer portion.

[0183] In some embodiments, the second selective metal layer is formed from a metallic material used to form the first selective metal layer.

[0184] In some embodiments, the second selective metal layer and the third conductive layer constitute a second mixed metal portion, which is configured to provide adjustable resistance by adjusting the metal material used in the second selective metal layer.

[0185] In some embodiments, a ruthenium layer is disposed on a first titanium nitride layer, and a second titanium nitride layer is disposed on a ruthenium layer.

[0186] In some embodiments, a semiconductor structure includes a substrate, a first dielectric layer, a conductive layer, an isolation structure, and a first selective metal layer. The first dielectric layer is on the substrate. A conductive layer comprising multiple conductive layer portions is on the first dielectric layer. An isolation structure is located between the first conductive layer portion and a second conductive layer portion of these conductive layer portions, wherein the isolation structure is bounded by a dielectric pad and includes a dielectric layer disposed in air gaps between multiple sidewalls of the dielectric pad. The first selective metal layer is on the first conductive layer portion.

[0187] In some embodiments, the semiconductor structure further includes a second dielectric layer and an etch stop layer. The second dielectric layer is located on the second conductive layer portion and the isolation structure, as well as on the sidewalls of the first selective metal layer. The etch stop layer is located on the second dielectric layer and the first selective metal layer.

[0188] In some embodiments, the semiconductor structure further includes a support layer disposed between the dielectric layer and the air gap.

[0189] In some implementations, the first selective metal layer has a metal height between 5 nm and 20 nm.

[0190] In some embodiments, a semiconductor structure includes a semiconductor structure having a ruthenium layer, an isolation structure, a first via dielectric layer, a first selective metal layer, and a second via dielectric layer. The isolation structure divides the ruthenium layer into multiple conductive layer portions, including a first conductive layer portion and a second conductive layer portion. The isolation structure is bounded by a dielectric pad and includes a dielectric layer disposed in an air gap between multiple sidewalls of the dielectric pad. The first via dielectric layer is on the semiconductor structure. The first selective metal layer extends through the first via dielectric layer to the first conductive layer portion. The second via dielectric layer is on the semiconductor structure.

[0191] In some embodiments, the semiconductor structure further includes a first titanium nitride layer and a second titanium nitride layer, wherein a ruthenium layer is disposed on the first titanium nitride layer and the second titanium nitride layer is disposed on the ruthenium layer.

[0192] In some implementations, the first selective metal layer has a metal height between 5 nm and 20 nm.

[0193] In some embodiments, a semiconductor structure includes a substrate, a first dielectric layer, a conductive layer, an isolation structure, and a support layer. The first dielectric layer is on the substrate. The conductive layer is disposed on the first dielectric layer. The isolation structure divides the conductive layer into multiple conductive layer portions, including a first conductive layer portion and a second conductive layer portion, wherein the isolation structure is bounded by a dielectric pad and includes a dielectric layer disposed in an air gap between multiple sidewalls of the dielectric pad. The support layer is disposed between the dielectric layer and the air gap.

[0194] In some implementations, the thickness of the dielectric pad is from 0.5 nm to 3 nm.

[0195] In some implementations, the height of the air gap is 10 nm to 20 nm.

[0196] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications to this disclosure without departing from its spirit and scope.

Claims

1. A semiconductor structure, characterized in that, include: A first dielectric layer is on a substrate; A conductive layer comprising multiple conductive layer portions is on the first dielectric layer; An isolation structure is located between a first conductive layer portion and a second conductive layer portion of the plurality of conductive layer portions, wherein the isolation structure is bounded by a dielectric pad and includes a dielectric layer disposed on an air gap between a plurality of sidewalls of the dielectric pad. as well as A first selective metal layer is applied to the first conductive layer portion.

2. The semiconductor structure as described in claim 1, characterized in that, Also includes: A second dielectric layer is applied to the second conductive layer portion, the isolation structure, and one sidewall of the first selective metal layer. as well as An etch stop layer is formed on the second dielectric layer and the first selective metal layer.

3. The semiconductor structure as described in claim 1, characterized in that, It also includes a support layer disposed between the dielectric layer and the air gap.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that, The first selective metal layer has a metal height between 5 nm and 20 nm.

5. A semiconductor structure, characterized in that, include: A semiconductor structure having a ruthenium layer; An isolation structure is provided to divide the ruthenium layer into multiple conductive layer portions, the multiple conductive layer portions including a first conductive layer portion and a second conductive layer portion, wherein the isolation structure is bounded by a dielectric pad and includes a dielectric layer disposed on an air gap between multiple sidewalls of the dielectric pad. A first via dielectric layer is present on the semiconductor structure; A first selective metal layer passes through the first via dielectric layer to the first conductive layer portion; as well as A second via dielectric layer is applied to the semiconductor structure.

6. The semiconductor structure as described in claim 5, characterized in that, Also includes: A first titanium nitride layer and a second titanium nitride layer, wherein the ruthenium layer is disposed on the first titanium nitride layer and the second titanium nitride layer is disposed on the ruthenium layer.

7. The semiconductor structure as described in claim 5 or claim 6, characterized in that, The first selective metal layer has a metal height between 5 nm and 20 nm.

8. A semiconductor structure, characterized in that, include: A first dielectric layer is on a substrate; A conductive layer is disposed on the first dielectric layer; An isolation structure divides the conductive layer into multiple conductive layer portions, each including a first conductive layer portion and a second conductive layer portion. The isolation structure is bounded by a dielectric pad and includes a dielectric layer disposed on an air gap between multiple sidewalls of the dielectric pad. A support layer is disposed between the dielectric layer and the air gap.

9. The semiconductor structure as described in claim 8, characterized in that, The thickness of the dielectric pad is 0.5 nm to 3 nm.

10. The semiconductor structure as claimed in claim 8 or claim 9, characterized in that, The height of this air gap is 10 nm to 20 nm.

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